KR910003834A - 반도체장치의 제조방법 - Google Patents

반도체장치의 제조방법 Download PDF

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Publication number
KR910003834A
KR910003834A KR1019900011153A KR900011153A KR910003834A KR 910003834 A KR910003834 A KR 910003834A KR 1019900011153 A KR1019900011153 A KR 1019900011153A KR 900011153 A KR900011153 A KR 900011153A KR 910003834 A KR910003834 A KR 910003834A
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South Korea
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heat treatment
conductivity type
region
semiconductor device
forming
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KR1019900011153A
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English (en)
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가쯔히꼬 사가라
기요오 이또
고로 기쯔까와
요시후미 가와모또
요시끼 가와지리
Original Assignee
미다 가쓰시게
가부시끼가이샤 히다찌세이사꾸쇼
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Publication of KR910003834A publication Critical patent/KR910003834A/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H01L21/8249—Bipolar and MOS technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/318—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor the storage electrode having multiple segments
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/144—Shallow diffusion

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

내용 없음.

Description

반도체장치의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명의 1실시예를 도시한 공정도.

Claims (10)

  1. (a) 제1의 도전형을 갖는 불순물과 상기 제1의 도전형과 반대인 제2의 도전형을 갖는 불순물을 반도체 기판의 표면영역의 소정의 부분에 선택적으로 도프하여 바이폴라 트랜지스터를 형성할 제1의 웰영역, 상기 제1의 도전형을 갖는 제2의 웰영역 및 제2의 도전형을 갖는 제3의 웰영역을 형성하는 공정, (b) 상기 불순물을 상기 제1의 영역의 표면영역에 도프하여 상기 제1의 웰영역의 것과 반대인 도전형을 갖는 베이스를 형성하는 공정, (c)소정의 패턴을 가지며, 상기 베이스의 표면의 소정의 부분에 상기 제1의 웰영역의 것과 같은 도전형의 많은 불순물양을 함유한 다결정 실리콘막을 형성하고, 제1의 열처리를 실행하여 상기 베이스에 상기 다결정 실리콘막에 함유된 불순물을 확산시켜 이미터를 형성하는 공정, (d) 상기 제2 및 제3의 웰영역 각각의 표면에 절연막을 형성하는 공정, (e) 상기 절연막의 각각에 소정의 형상을 갖는 도전막의 게이트전극을 형성하는 공정과 (f) 상기 제2 및 제1의 도전형의 불순물을 각각 상기 제2 및 제3의 웰 영역의 표면영역의 소정부분에 도프하고, 상기 제1의 열처리보다 낮은 온도에서 제2의 열처리를 실행하여 상기 이미터보다 얇은 MOS트랜지스터의 소스 및 드레인을 형성하는 공정을 포함하는 반도체장치의 제조방법.
  2. 특허청구의 범위 제1항에 있어서, 상기 제1 및 제2의 도전형은 각각 P형 및 N형인 반도체장치의 제조방법.
  3. 특허청구의 범위 제2항에 있어서, 상기 제1의 웰영역은 N형 영역이고, 상기 바이폴라 트랜지스터는 npn바이폴라 트랜지스터인 반도체장치의 제조방법.
  4. 특허청구의 범위 제1항에 있어서, 상기 제1의 열처리는 900℃이상의 온도에서 실행되는 반도체장치의 제조방법.
  5. 특허청구의 범위 제2항에 있어서, 상기 제2의 열처리는 850℃이하의 온도에서 실시되는 반도체장치의 제조방법.
  6. 특허청구의 범위 제1항에 있어서, 상기 이미터의 두께는 0.15㎛이하인 반도체장치의 제조방법.
  7. 특허청구의 범위 제1항에 있어서, 상기 반도체장치는 1개의 MOS트랜지스터 및 1개의 커패시터로 구성되는 다이나믹 메모리셀을 갖는 BiCMOS인 반도체장치의 제조방법.
  8. 특허청구의 범위 제1항에 있어서, 상기 반도체장치는 스테이틱 메모리셀을 갖는 BiCMOS인 반도체장치의 제조방법.
  9. 특허청구의 범위 제1항에 있어서, 상기 소스 및 드레인의 형성은 또 마스크로써 형성된 상기 게이트전극 및 절연막을 사용하는 이온주입 및 상기 제2의 열처리에 의해 실행되는 반도체장치의 제조방법.
  10. 특허청구의 범위 제1항에 있어서, 상기 공정(f)는 상기 제2 및 제3의 웰영역의 표면영역의 소정부분에 상기 제2 및 제1의 도전형의 불순물을 이온주입하고, 상기 게이트 전극 각각의 사이드웰에 절연막을 형성하고, 상기 제2 및 제1의 도전형의 불순물을 각각 이온주입하고, 상기 제1의 열처리보다 낮은 온도에서 열처리를 실행하여 상기 이미터의 두께보다 얇은 부분의 두께와 부분적으로 다른 두께로 MOS트랜지스터의 소스 및 드레인을 형성하는 공정(f′)로 대체되는 반도체장치의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019900011153A 1989-07-31 1990-07-23 반도체장치의 제조방법 KR910003834A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP1-196569 1989-07-31
JP1196569A JPH0362568A (ja) 1989-07-31 1989-07-31 半導体装置の製造方法

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US (1) US5118633A (ko)
EP (1) EP0418505A3 (ko)
JP (1) JPH0362568A (ko)
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US6350640B1 (en) * 1994-07-18 2002-02-26 Intersil Americas Inc. CMOS integrated circuit architecture incorporating deep implanted emitter region to form auxiliary bipolar transistor
JP2616569B2 (ja) * 1994-09-29 1997-06-04 日本電気株式会社 半導体集積回路装置の製造方法
KR100190029B1 (ko) * 1996-03-19 1999-06-01 윤종용 바이씨모스 에스램 소자의 제조방법
US5780329A (en) * 1997-04-03 1998-07-14 Symbios, Inc. Process for fabricating a moderate-depth diffused emitter bipolar transistor in a BICMOS device without using an additional mask
JPH10289961A (ja) * 1997-04-15 1998-10-27 Nec Corp 半導体装置の製造方法
JP5817205B2 (ja) * 2011-04-28 2015-11-18 株式会社デンソー 半導体装置の製造方法

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EP0418505A3 (en) 1991-09-25
JPH0362568A (ja) 1991-03-18
US5118633A (en) 1992-06-02
EP0418505A2 (en) 1991-03-27

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