KR850002177A - 얕은 n형 영역을 형성하는 방법 - Google Patents

얕은 n형 영역을 형성하는 방법 Download PDF

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Publication number
KR850002177A
KR850002177A KR1019840005080A KR840005080A KR850002177A KR 850002177 A KR850002177 A KR 850002177A KR 1019840005080 A KR1019840005080 A KR 1019840005080A KR 840005080 A KR840005080 A KR 840005080A KR 850002177 A KR850002177 A KR 850002177A
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South Korea
Prior art keywords
film
shallow
type region
antimony
doped
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KR1019840005080A
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English (en)
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KR890003381B1 (en
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가쓰노부 우에노 (외 1)
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야마모도 다꾸마
후지쓰 가부시끼 가이샤
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Publication of KR850002177A publication Critical patent/KR850002177A/ko
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Publication of KR890003381B1 publication Critical patent/KR890003381B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Bipolar Transistors (AREA)
  • Photovoltaic Devices (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

내용 없음

Description

얕은 N형 영역을 형성하는 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제4도 내지 제7도는 본 발명의 N형 영역 형성방법에 따른 여러 생산단계의 바이포울러 트랜지스터의 개략단면도.

Claims (9)

  1. 반도체 장치의 얕은 n형 영역을 형성하는 방법에 있어서, 실리콘 반도체 기판위에 비스 또는 안티몬을 포함하는 제1막을 형성하는 단계, 상기 제1막 위에 인을 포함하는 제2막을 형성하는 단계, 및 열처리에 의해 상기 제1 및 제2막으로부터 상기 반도체 기판으로 상기 비소 또는 안티몬 및 상기인을 확산시키는 단계로 이루어지는 것을 특징으로 하는 얕은 n형 영역을 형성하는 방법.
  2. 제1항에 있어서, 상기 제1막 및 상기 제2막은 다결정 실리콘, 아모로퍼스 실리콘, 백금규화물 및 텅스텐규화물로 구성되는 그룹에서 선택된 하나의 물질로 이루어지는 것을 특징으로 하는 얕은 n형 영역을 형성하는 방법.
  3. 제2항에 있어서, 상기 비소 또는 안티몬은 이온주입법에 의해 상기 제1막으로 도우핑되며 상기 인은 이온주입방법에 의해 상기 제2막으로 도우핑되는 것을 특징으로 하는 얕은 n형 영역을 형성하는 방법.
  4. 제2항에 있어서, 상기 비소 또는 안티몬은 기상 성장법에 의해 상기 제1막을 형성하는 동안 상기 제1막으로 도우핑되며 상기인은 기상성장법에 의해 상기 제2막을 형성하는 동안 상기 제2막으로 도우핑되는 것을 특징으로 하는 얕은 n형 영역을 형성하는 방법.
  5. 제2항에 있어서, 상기 제1막은 0.05 내지 0.15㎛의 두께인 것을 특징으로 하는 얕은 n형 영역을 형성하는 방법.
  6. 제2항에 있어서, 상기 제2막은 0.1 내지 0.25㎛의 두께인 것을 특징으로 하는 얕은 n형 영역을 형성하는 방법.
  7. 제1항에 있어서, 상기 얕은 n형 영역은 바이포울러 트랜지스터와 에미티 영역인 것을 특징으로 하는 얕은 n형 영역을 형성하는 방법.
  8. 제1항에 있어서, 상기 얕은 n형 영역은 MOS FET의 드레인 영역 및 소오스 영역인 것을 특징으로 하는 얕은 n형 영역을 형성하는 방법.
  9. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR8405080A 1983-08-30 1984-08-22 Forming method of thin n-type area KR890003381B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP58159949A JPS6063961A (ja) 1983-08-30 1983-08-30 半導体装置の製造方法
JP???58-159949 1983-08-30

Publications (2)

Publication Number Publication Date
KR850002177A true KR850002177A (ko) 1985-05-06
KR890003381B1 KR890003381B1 (en) 1989-09-19

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KR8405080A KR890003381B1 (en) 1983-08-30 1984-08-22 Forming method of thin n-type area

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US (2) US4629520A (ko)
EP (1) EP0137645B1 (ko)
JP (1) JPS6063961A (ko)
KR (1) KR890003381B1 (ko)
DE (1) DE3484814D1 (ko)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4682404A (en) * 1986-10-23 1987-07-28 Ncr Corporation MOSFET process using implantation through silicon
IT1197523B (it) * 1986-10-30 1988-11-30 Sgs Microelettronica Spa Processo per la fabbricazione di transistori ad effetto di campo a "gate" isolata con giunzioni aventi profondita' estremamente ridotta
US4740478A (en) * 1987-01-30 1988-04-26 Motorola Inc. Integrated circuit method using double implant doping
JPH01123417A (ja) * 1987-11-07 1989-05-16 Mitsubishi Electric Corp 半導体装置の製造方法
JPH01147829A (ja) * 1987-12-04 1989-06-09 Toshiba Corp 半導体装置の製造方法
US5047357A (en) * 1989-02-03 1991-09-10 Texas Instruments Incorporated Method for forming emitters in a BiCMOS process
US4927773A (en) * 1989-06-05 1990-05-22 Santa Barbara Research Center Method of minimizing implant-related damage to a group II-VI semiconductor material
US5296388A (en) * 1990-07-13 1994-03-22 Matsushita Electric Industrial Co., Ltd. Fabrication method for semiconductor devices
SG71664A1 (en) * 1992-04-29 2000-04-18 Siemens Ag Method for the production of a contact hole to a doped region
US5345104A (en) * 1992-05-15 1994-09-06 Micron Technology, Inc. Flash memory cell having antimony drain for reduced drain voltage during programming
IT1256362B (it) * 1992-08-19 1995-12-04 St Microelectronics Srl Processo di realizzazione su semiconduttori di regioni impiantate a basso rischio di channeling
JP3133667B2 (ja) * 1995-02-23 2001-02-13 三洋電機株式会社 スプリットゲート型トランジスタ、スプリットゲート型トランジスタの製造方法、不揮発性半導体メモリ
DE19511251A1 (de) * 1995-03-27 1996-10-02 Siemens Ag Bipolarer Siliziumtransistor
US5994182A (en) * 1996-01-18 1999-11-30 Micron Technology, Inc. Method of reducing outdiffusion from a doped three-dimensional polysilicon film into substrate by using angled implants
JP3075204B2 (ja) * 1997-02-28 2000-08-14 日本電気株式会社 半導体装置の製造方法
US5937299A (en) * 1997-04-21 1999-08-10 Advanced Micro Devices, Inc. Method for forming an IGFET with silicide source/drain contacts in close proximity to a gate with sloped sidewalls
US6011272A (en) * 1997-12-06 2000-01-04 Advanced Micro Devices, Inc. Silicided shallow junction formation and structure with high and low breakdown voltages
US6576521B1 (en) * 1998-04-07 2003-06-10 Agere Systems Inc. Method of forming semiconductor device with LDD structure
US6331468B1 (en) * 1998-05-11 2001-12-18 Lsi Logic Corporation Formation of integrated circuit structure using one or more silicon layers for implantation and out-diffusion in formation of defect-free source/drain regions and also for subsequent formation of silicon nitride spacers
DE10058031B4 (de) * 2000-11-23 2007-11-22 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Bildung leicht dotierter Halogebiete und Erweiterungsgebiete in einem Halbleiterbauelement
US6682992B2 (en) * 2002-05-15 2004-01-27 International Business Machines Corporation Method of controlling grain size in a polysilicon layer and in semiconductor devices having polysilicon structures
US20040121524A1 (en) * 2002-12-20 2004-06-24 Micron Technology, Inc. Apparatus and method for controlling diffusion
US7297617B2 (en) * 2003-04-22 2007-11-20 Micron Technology, Inc. Method for controlling diffusion in semiconductor regions
US20060234484A1 (en) * 2005-04-14 2006-10-19 International Business Machines Corporation Method and structure for ion implantation by ion scattering
US8110469B2 (en) 2005-08-30 2012-02-07 Micron Technology, Inc. Graded dielectric layers
US10164043B2 (en) * 2012-01-11 2018-12-25 Infineon Technologies Ag Semiconductor diode and method for forming a semiconductor diode
US9306010B2 (en) * 2012-03-14 2016-04-05 Infineon Technologies Ag Semiconductor arrangement
DE102018111213A1 (de) 2018-05-09 2019-11-14 Infineon Technologies Ag Halbleitervorrichtung und Herstellungsverfahren

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4364166A (en) * 1979-03-01 1982-12-21 International Business Machines Corporation Semiconductor integrated circuit interconnections
JPS55153365A (en) * 1979-05-17 1980-11-29 Toshiba Corp Manufacturing method of semiconductor device
JPS6043656B2 (ja) * 1979-06-06 1985-09-30 株式会社東芝 半導体装置の製造方法
DE2946963A1 (de) * 1979-11-21 1981-06-04 Siemens AG, 1000 Berlin und 8000 München Schnelle bipolare transistoren
NL8006827A (nl) * 1980-12-17 1982-07-16 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting.
US4419810A (en) * 1981-12-30 1983-12-13 International Business Machines Corporation Self-aligned field effect transistor process
JPS5919354A (ja) * 1982-07-24 1984-01-31 Fujitsu Ltd 半導体装置
JPS5946065A (ja) * 1982-09-09 1984-03-15 Toshiba Corp 半導体装置の製造方法
US4542580A (en) * 1983-02-14 1985-09-24 Prime Computer, Inc. Method of fabricating n-type silicon regions and associated contacts

Also Published As

Publication number Publication date
DE3484814D1 (de) 1991-08-22
EP0137645A3 (en) 1987-10-07
EP0137645A2 (en) 1985-04-17
US4875085A (en) 1989-10-17
KR890003381B1 (en) 1989-09-19
EP0137645B1 (en) 1991-07-17
JPS6063961A (ja) 1985-04-12
US4629520A (en) 1986-12-16

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