KR850002177A - 얕은 n형 영역을 형성하는 방법 - Google Patents

얕은 n형 영역을 형성하는 방법 Download PDF

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Publication number
KR850002177A
KR850002177A KR1019840005080A KR840005080A KR850002177A KR 850002177 A KR850002177 A KR 850002177A KR 1019840005080 A KR1019840005080 A KR 1019840005080A KR 840005080 A KR840005080 A KR 840005080A KR 850002177 A KR850002177 A KR 850002177A
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South Korea
Prior art keywords
film
shallow
type region
antimony
doped
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KR1019840005080A
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KR890003381B1 (en
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가쓰노부 우에노 (외 1)
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야마모도 다꾸마
후지쓰 가부시끼 가이샤
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Publication of KR850002177A publication Critical patent/KR850002177A/ko
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Publication of KR890003381B1 publication Critical patent/KR890003381B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Bipolar Transistors (AREA)
  • Photovoltaic Devices (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

내용 없음

Description

얕은 N형 영역을 형성하는 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제4도 내지 제7도는 본 발명의 N형 영역 형성방법에 따른 여러 생산단계의 바이포울러 트랜지스터의 개략단면도.

Claims (9)

  1. 반도체 장치의 얕은 n형 영역을 형성하는 방법에 있어서, 실리콘 반도체 기판위에 비스 또는 안티몬을 포함하는 제1막을 형성하는 단계, 상기 제1막 위에 인을 포함하는 제2막을 형성하는 단계, 및 열처리에 의해 상기 제1 및 제2막으로부터 상기 반도체 기판으로 상기 비소 또는 안티몬 및 상기인을 확산시키는 단계로 이루어지는 것을 특징으로 하는 얕은 n형 영역을 형성하는 방법.
  2. 제1항에 있어서, 상기 제1막 및 상기 제2막은 다결정 실리콘, 아모로퍼스 실리콘, 백금규화물 및 텅스텐규화물로 구성되는 그룹에서 선택된 하나의 물질로 이루어지는 것을 특징으로 하는 얕은 n형 영역을 형성하는 방법.
  3. 제2항에 있어서, 상기 비소 또는 안티몬은 이온주입법에 의해 상기 제1막으로 도우핑되며 상기 인은 이온주입방법에 의해 상기 제2막으로 도우핑되는 것을 특징으로 하는 얕은 n형 영역을 형성하는 방법.
  4. 제2항에 있어서, 상기 비소 또는 안티몬은 기상 성장법에 의해 상기 제1막을 형성하는 동안 상기 제1막으로 도우핑되며 상기인은 기상성장법에 의해 상기 제2막을 형성하는 동안 상기 제2막으로 도우핑되는 것을 특징으로 하는 얕은 n형 영역을 형성하는 방법.
  5. 제2항에 있어서, 상기 제1막은 0.05 내지 0.15㎛의 두께인 것을 특징으로 하는 얕은 n형 영역을 형성하는 방법.
  6. 제2항에 있어서, 상기 제2막은 0.1 내지 0.25㎛의 두께인 것을 특징으로 하는 얕은 n형 영역을 형성하는 방법.
  7. 제1항에 있어서, 상기 얕은 n형 영역은 바이포울러 트랜지스터와 에미티 영역인 것을 특징으로 하는 얕은 n형 영역을 형성하는 방법.
  8. 제1항에 있어서, 상기 얕은 n형 영역은 MOS FET의 드레인 영역 및 소오스 영역인 것을 특징으로 하는 얕은 n형 영역을 형성하는 방법.
  9. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR8405080A 1983-08-30 1984-08-22 Forming method of thin n-type area KR890003381B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP???58-159949 1983-08-30
JP58159949A JPS6063961A (ja) 1983-08-30 1983-08-30 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
KR850002177A true KR850002177A (ko) 1985-05-06
KR890003381B1 KR890003381B1 (en) 1989-09-19

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KR8405080A KR890003381B1 (en) 1983-08-30 1984-08-22 Forming method of thin n-type area

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US (2) US4629520A (ko)
EP (1) EP0137645B1 (ko)
JP (1) JPS6063961A (ko)
KR (1) KR890003381B1 (ko)
DE (1) DE3484814D1 (ko)

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Also Published As

Publication number Publication date
EP0137645A2 (en) 1985-04-17
EP0137645B1 (en) 1991-07-17
KR890003381B1 (en) 1989-09-19
US4629520A (en) 1986-12-16
US4875085A (en) 1989-10-17
DE3484814D1 (de) 1991-08-22
JPS6063961A (ja) 1985-04-12
EP0137645A3 (en) 1987-10-07

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