KR970054458A - 반도체 장치의 제조 방법 - Google Patents

반도체 장치의 제조 방법 Download PDF

Info

Publication number
KR970054458A
KR970054458A KR1019950049704A KR19950049704A KR970054458A KR 970054458 A KR970054458 A KR 970054458A KR 1019950049704 A KR1019950049704 A KR 1019950049704A KR 19950049704 A KR19950049704 A KR 19950049704A KR 970054458 A KR970054458 A KR 970054458A
Authority
KR
South Korea
Prior art keywords
pattern
conductive film
source
semiconductor device
manufacturing
Prior art date
Application number
KR1019950049704A
Other languages
English (en)
Other versions
KR0165355B1 (ko
Inventor
이용재
나종진
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950049704A priority Critical patent/KR0165355B1/ko
Publication of KR970054458A publication Critical patent/KR970054458A/ko
Application granted granted Critical
Publication of KR0165355B1 publication Critical patent/KR0165355B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3215—Doping the layers
    • H01L21/32155—Doping polycristalline - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

고신뢰성 쌍극성 트랜지스터와 낮은 콘택저항의 소오스/드레인 전극을 갖는 MOS 트랜지스터를 구비한 반도체 장치 제조 방법이 개시되어 있다. 본 발명은 비소 또는 안티몬을 포함하는 제1도전막과 인을 포함하는 제2도전막을 이용하여 쌍극성 트랜지스터를 완성하는 동시에 에미터 전극 및 MOS 트랜지스터의 소오스/드레인 전극을 완성한다. 본 발명에 의하면, NMOS 트랜지스터의 소오스/드레인 전극의 낮은 콘택저항과 NPN 쌍극성 트랜지스터의 에미터 영역의 격자결함에 감소에 의한 신뢰성 확보 및 얕은 에미터 접합을 함께 구비하는 반도체 장치의 제조 방법을 제공한다.

Description

반도체 장치의 제조 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제8도는 본 발명의 실시예에 따른 반도체 장치의 제조방법을 설명하기 위한 단면도들이다.

Claims (5)

  1. NMOS 트랜지스터와 NPN 쌍극성 트랜지스터를 구비한 반도체 장치의 제조방법에 있어서, 반도체 기판 표면에 형성된 소오스/드레인 영역 및 베이스 영역을 포함하는 반도체 기판 전면에 절연막을 형성하는 단계; 상기 절연막을 패터닝하여 상기 베이스 영역을 노출시키는 절연막의 제1패턴을 형성하는 단계; 상기 절연막의 제1패턴 및 노출된 베이스 영역 상에 비소(As) 및 안티몬(Sb) 중에서 선택된 어느 하나를 포함하는 제1도전막을 형성하는 단계; 상기 소오스/드레인 영역 상부의 제1도전막 및 상기 절연막의 제1패턴을 패터닝하여 상기 소오스/드레인 영역을 노출시키는 제1도전막 패턴 및 절연막의 제2패턴을 형성하는 단계; 상기 노출된 소오스/드레인 영역 및 상기 제1도전막 패턴 상에 인(P)을 포함하는 제2도전막을 형성하는 단계; 및 상기 결과물을 열처리함으로써 상기 제1도전막 패턴 및 상기 제2도전막에 함유되어 있는 불순물을 상기 베이스 영역 표면으로 확산시켜 상기 제1도전막 하부에 있는 베이스 영역의 표면에 에미터 영역을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 장치의 제조방법.
  2. 제1항에 있어서, 상기 제1도전막은 다결정 실리콘 및 비정질 실리콘 중에서 선택된 어느 하나인 것을 특징으로 하는 반도체 장치의 제조 방법.
  3. 제1항에 있어서, 상기 제2도전막은 다결정 실리콘 및 비정질 실리콘 중에서 선택된 어느 하나인 것을 특징으로 하는 반도체 장치 소자의 제조방법.
  4. 제1항에 있어서, 상기 열처리는 급속 열처리(Rapid Thermal Annealing)인 것을 특징으로 하는 반도체 장치의 제조방법.
  5. 제1항에 있어서, 상기 에미터 전극을 형성하는 단계 이후에 상기 제2도전막 및 제1도전막 패턴을 패터닝하여 소오스/드레인 전극 및 에미터 전극을 형성하는 단계를 더 포함하는 것을 특징으로 하는 반도체 장치의 제조 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950049704A 1995-12-14 1995-12-14 반도체 장치의 제조 방법 KR0165355B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950049704A KR0165355B1 (ko) 1995-12-14 1995-12-14 반도체 장치의 제조 방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950049704A KR0165355B1 (ko) 1995-12-14 1995-12-14 반도체 장치의 제조 방법

Publications (2)

Publication Number Publication Date
KR970054458A true KR970054458A (ko) 1997-07-31
KR0165355B1 KR0165355B1 (ko) 1998-12-15

Family

ID=19439957

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950049704A KR0165355B1 (ko) 1995-12-14 1995-12-14 반도체 장치의 제조 방법

Country Status (1)

Country Link
KR (1) KR0165355B1 (ko)

Also Published As

Publication number Publication date
KR0165355B1 (ko) 1998-12-15

Similar Documents

Publication Publication Date Title
KR840005926A (ko) 반도체 집적 회로 장치의 제조 방법
KR850002177A (ko) 얕은 n형 영역을 형성하는 방법
KR910013577A (ko) 반도체 장치의 제조방법
KR880014679A (ko) 샐로우 npn 에미터 및 mosfet 소오스/드레인을 형성하기 위한 bicmos 방법
KR880006781A (ko) 반도체 집적회로 및 그 제조방법
KR960002884A (ko) 바이폴라 트랜지스터 및 mos 트랜지스터를 포함한 반도체 장치 제조 방법
KR840005927A (ko) 반도체 집적 회로 장치 및 그의 제조 방법
KR960026747A (ko) 반도체 집적회로장치의 제조방법
KR910007133A (ko) 고 성능 BiCMOS 회로를 제조하는 방법
KR930001456A (ko) 자기 정합된 플레이너 모놀리딕 집적회로의 종적 트랜지스터 프로세스
KR920001750A (ko) 반도체 장치 및 그 제조방법
KR930001460A (ko) 반도체 집적회로장치 및 그 제조방법
KR850005139A (ko) 반도체 장치의 제조방법
KR910003834A (ko) 반도체장치의 제조방법
KR890016620A (ko) 반도체 집적회로장치의 제조방법
JPS5660063A (en) Manufacture of semiconductor device
KR900015311A (ko) 반도체장치 및 그 제조방법
KR970054458A (ko) 반도체 장치의 제조 방법
KR970003934A (ko) BiCMOS 반도체장치 및 그 제조방법
KR950021730A (ko) 바이폴라 트랜지스터를 갖는 반도체 장치 및 그 제조방법
KR970013206A (ko) 반도체 디바이스 제조 방법
KR910001876A (ko) 반도체 장치 제조방법
KR950004584A (ko) 오프셋 구조의 다결정 실리콘 박막 트랜지스터 제조방법
KR980005801A (ko) 고저항과 저저항의 저항층을 갖는 반도체 소자의 제조방법
KR970063750A (ko) 반도체 장치 및 그 제조 방법

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20060830

Year of fee payment: 9

LAPS Lapse due to unpaid annual fee