KR930001460A - 반도체 집적회로장치 및 그 제조방법 - Google Patents

반도체 집적회로장치 및 그 제조방법 Download PDF

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KR930001460A
KR930001460A KR1019920011331A KR920011331A KR930001460A KR 930001460 A KR930001460 A KR 930001460A KR 1019920011331 A KR1019920011331 A KR 1019920011331A KR 920011331 A KR920011331 A KR 920011331A KR 930001460 A KR930001460 A KR 930001460A
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film
insulating film
conductive
forming
integrated circuit
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KR1019920011331A
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KR960006104B1 (ko
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다이라 마츠나가
분시로 야마키
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아오이 죠이치
가부시키가이샤 도시바
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/298—Semiconductor material, e.g. amorphous silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H01L21/8249—Bipolar and MOS technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0635—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors and diodes, or resistors, or capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
  • Bipolar Integrated Circuits (AREA)

Abstract

내용 없음

Description

반도체 집적회로장치 및 그 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 제1실시예에 따른 반도체 집적회로장치의 제조공정을 나타낸 제1단면도.
제2도는 본 발명의 제1실시예에 따른 반도체 집적회로장치의 제조공정을 나타낸 제2단면도.
제3도는 본 발명의 제1실시예에 따른 반도체 집적회로장치의 제조공정을 나타낸 제3단면도.

Claims (9)

  1. 반도체기체(15,105)내에 설치된 바이폴라 트랜지스터(Q2)의 콜렉터와 베이스 및 에미터 각각의 영역(18,38,40,62)과, 상기 기체(15,105)상에 도출된 콜렉터와 베이스 및 에미터 각각의 전극(52,78,54),상기 기체(15,105)상에 설치되면서 상기 각 전극(52,78,54)을 상기 기체(15,105)상에서 서로 절연하는 에칭 내성이 각각 다른 복수 종류의 절연막(34,42)을 적충하여 구성된 적충절연막, 상기 기체(15,105)내에 설치된 절연게이트형 트랜지스터(Q1)의 소오스 및 드레인 각각의 영역(58,60), 이 소오스영역(58)과 드레인영역(60)과의 사이의 상기 기체(15,105)상에 설치된 게이트 절연막(24)및,이 게이트 절연막(24)상에 설치된 게이트전극(56)을 구비하여 구성된 것을 특징으로 하는 반도체 집적회로장치.
  2. 제1항에 있어서, 상기 절연게이트형 트랜지스터(Q1)는 상기 게이트 절연막(24)상에 설치된 게이트 절연막(24)의 보호피박(26)을 구비하여 구성된 것을 특징으로 반도체 집적회로장치.
  3. 제1항 또는 제2항에 있어서, 상기 적충절연막은 상기 기체(15,105)상에서 순차적으로 산화규소막(34)과 질화규소막(42)을 적층한 막으로 구성된 것을 특징으로 하는 반도체 집적회로장치.
  4. 제2항에 있어서,상기 게이트 절연막(24)의 보호피막(26)은 다결정 규소막으로 구성된 것을 특징으로 하는 반도체 집적회로장치.
  5. 제1도전형 반도체기체(15,105)내에 제2도전형 콜렉터영역(18)을 형성하는 공정과, 상기 기체(15,105)표면에 절연게이트형 트랜지스터(Q1)의 게이트 절연막(24)으로 되는 제1절연막을 형성하는 공정, 상기 제1절연막상에 게이트 절연막 보호피막(26)을 형성하는 공정,상기 게이트 절연막 보호피막(26)을 적어도 상기 콜렉터영역(18)상에서 선택적으로 제거하는 공정, 전체면에 제2절연막(34,36)을 형성하는 공정, 상기 콜렉터영역(18)내에 베이스영역 형성용의 제1도전형 불순물을 선택적으로 도입하는공정, 상기 제2절연막(34,36)상에 이 제2절연막(34,36)과 다른 에칭내성을 갖춘 제3절연막(42)을 형성하는 공정, 상기 제2및 제3절연막(34,36;42)을 절연게이트형 트랜지스터 형성예정영역(28)상 및 적어도 에미터 개구부 형성예정영역상에서 선택적으로 제거하는 공정, 전체면에 제1도전막(48,50)을 형성하는 공정, 상기 제1도전막(48,50)을 적어도 절연게이트형 트랜지스터의 게이트전극(56)패턴과 바이폴라 트랜지스터의 에미터전극(54)패턴으로 패터닝하는 공정, 상기 절연게이트형 트랜지스터의 게이트전극(56)패턴을 마스크로 이용하여 상기기체(15,105)내에 소오스/드레인 영역형성용의 제2도전형 불순물을 선택적으로 도입하는 공정, 전체면에 제4절연막(64)을 형성하는 공정, 상기 제4절연막(64)을 적어도 상기 콜렉터영역(18)상에서 제거함과 더불어 상기 제4절연막(64)에 소오스/드레인영역(58,60)으로 통하는 개구부(68)를 개구하는 공정, 전체면에 제2도전막을 형성하는 공정및, 상기 제2도전막을 소정의 배선 패턴으로 패터닝하는 공정을 구비하여 이루어진 것을 특징으로 하는 반도체 집적회로장치의 제조방법.
  6. 제5항에 있어서, 상기 제3절연막(42)이 질화규소막인 것을 특징으로 하는 반도체 집적회로장치의 제조방법.
  7. 제5항에 있어서, 상기 제2절연막(34,36)이 산화규소막인 것을 특징으로 하는 반도체 집적회로장치의 제조방법.
  8. 제5항에 있어서, 상기 게이트 절연막 보호피막(26)이 폴리실리콘막인 것을 특징으로 하는 반도체 집적회로장치의 제조방법.
  9. 제5항에 있어서, 상기 제1전도막(48,50)이 제2도전형 불순물을 포함하는 다결정 규소막(48)과, 고융점 금속막 또는 고융점 금속의 실리콘막(50)을 적층한 구조로 이루어진 것을 특징으로 하는 반도체 집적회로장치의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.
KR1019920011331A 1991-06-27 1992-06-27 반도체 집적회로장치 및 그 제조방법 KR960006104B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP03157057A JP3128267B2 (ja) 1991-06-27 1991-06-27 半導体集積回路装置の製造方法
JP91-157057 1991-06-27

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KR930001460A true KR930001460A (ko) 1993-01-16
KR960006104B1 KR960006104B1 (ko) 1996-05-08

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JP (1) JP3128267B2 (ko)
KR (1) KR960006104B1 (ko)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2997123B2 (ja) * 1992-04-03 2000-01-11 株式会社東芝 半導体装置の製造方法
US5420056A (en) * 1994-01-14 1995-05-30 Texas Instruments Incorporated Junction contact process and structure for semiconductor technologies
US5932922A (en) * 1994-08-08 1999-08-03 Semicoa Semiconductors Uniform current density and high current gain bipolar transistor
JP3583228B2 (ja) 1996-06-07 2004-11-04 株式会社ルネサステクノロジ 半導体装置およびその製造方法
FR2756101B1 (fr) * 1996-11-19 1999-02-12 Sgs Thomson Microelectronics Procede de fabrication d'un transistor npn dans une technologie bicmos
FR2756100B1 (fr) 1996-11-19 1999-02-12 Sgs Thomson Microelectronics Transistor bipolaire a emetteur inhomogene dans un circuit integre bicmos
FR2756104B1 (fr) * 1996-11-19 1999-01-29 Sgs Thomson Microelectronics Fabrication de circuits integres bipolaires/cmos
FR2756103B1 (fr) * 1996-11-19 1999-05-14 Sgs Thomson Microelectronics Fabrication de circuits integres bipolaires/cmos et d'un condensateur
JP3001045B2 (ja) 1997-03-28 2000-01-17 日本電気株式会社 半導体装置及びその製造方法
US20010029079A1 (en) 1997-03-28 2001-10-11 Nec Corporation Semiconductor device with multiple emitter contact plugs
JP3780189B2 (ja) * 2001-09-25 2006-05-31 富士通株式会社 半導体装置の製造方法及び半導体装置
US7098509B2 (en) * 2004-01-02 2006-08-29 Semiconductor Components Industries, L.L.C. High energy ESD structure and method
US8361699B2 (en) * 2008-02-05 2013-01-29 Nil Technology Aps Method for performing electron beam lithography

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US5023690A (en) * 1986-10-24 1991-06-11 Texas Instruments Incorporated Merged bipolar and complementary metal oxide semiconductor transistor device
US4978626A (en) * 1988-09-02 1990-12-18 Motorola, Inc. LDD transistor process having doping sensitive endpoint etching
US4984042A (en) * 1989-02-13 1991-01-08 Motorola, Inc. MOS transistors using selective polysilicon deposition
US5148252A (en) * 1990-02-13 1992-09-15 Kabushiki Kaisha Toshiba Bipolar transistor

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KR960006104B1 (ko) 1996-05-08
JP3128267B2 (ja) 2001-01-29
JPH056963A (ja) 1993-01-14

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