KR880006781A - 반도체 집적회로 및 그 제조방법 - Google Patents

반도체 집적회로 및 그 제조방법 Download PDF

Info

Publication number
KR880006781A
KR880006781A KR870012957A KR870012957A KR880006781A KR 880006781 A KR880006781 A KR 880006781A KR 870012957 A KR870012957 A KR 870012957A KR 870012957 A KR870012957 A KR 870012957A KR 880006781 A KR880006781 A KR 880006781A
Authority
KR
South Korea
Prior art keywords
integrated circuit
emitter
layer
semiconductor integrated
polycrystalline silicon
Prior art date
Application number
KR870012957A
Other languages
English (en)
Other versions
KR970000426B1 (ko
Inventor
빈너를 요셉
네플 프란츠
Original Assignee
휘티쉬 , 네테부쉬
지멘스 악티엔게젤샤프트
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 휘티쉬 , 네테부쉬, 지멘스 악티엔게젤샤프트 filed Critical 휘티쉬 , 네테부쉬
Publication of KR880006781A publication Critical patent/KR880006781A/ko
Application granted granted Critical
Publication of KR970000426B1 publication Critical patent/KR970000426B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76889—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

내용 없음

Description

반도체 집적회로 및 그 재작방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도 내지 3도는 본 발명의 1실시예의 제작에 있어 3개의 연속적인 단계를 나타내기 위한 반도체기판 및 그의 구조에 대한 부분 측단면도.

Claims (6)

  1. 다결정 실리콘 및 고융점의 금속실리사이드로 2중층으로 형성된 게이트 전극 및 또는 에미터와 베이스 단자를 가지는 CMOS 또는 바이폴라/CMOS 트랜지스터와 집적회로의 활성트랜지스터 지역을 분리시키는 피일드 산화물 지역위에 있는 박막소자로서 배치된 부하저항을 포함하고, 상기 부하저항이 게이트전극 및/ 또는 에미터와 베이스단자의 다결정 실리콘층과 동일한 레벨로 배치되고 또 도핑된 다결정실리콘층 구조로되며 그 단자가 고융점의 금속실리사이드로 구성되게 한 것을 특징으로 하는 반도체 집적회로.
  2. 제1항에 있어서, 상기 부하저항의 측벽에 측벽절연층이 제공되는 것을 특징으로 하는 반도체 집적회로.
  3. 제1항 또는 제2항에 있어서, 상기 금속 실리사이드는 탄탈 디실리사이드(TaSi2)인 것을 특징으로 하는 반도체 집적회로.
  4. 제1항 내지 3항중 어느 한 항에서 청구한 바와 같은 반도체 집적회로의 제작방법에 있어서, 집적회로의 활성트랜지스터 영역을 분리하는 피일드산화물 지역위에 있고 산화물마스크를 사용하여 형성되는 박막소자로서 폴리실리콘으로 구성된 부하저항이 게이트 전극 및/ 또는 에미터와 베이스단자 지역의 폴리실리콘층의 성장과 동시에 성장되며, 고융점의 금속실리사이드로 구성된 부하저항단자의 형성은 MOS틀랜지스터의 게이트 전극 및/ 또는 바이폴라트랜지스터의 에미터 및 비이스단자의 형성과 동시에 수행되게 한 것을 특징으로 하는 집적회로의 제작방법.
  5. 제4항에 있어서, 부하저항을 형성하는 폴리실리콘층의 도핑은 층의 성장중이나 차후에 이온주입 또는 확산에 의해 수행되는 것을 특징으로 하는 집적회로의 제작방법.
  6. 제4항에 또는 5항에 있어서, 상기 부하저항과 MOS트랜지스터의 게이트 전극에는 등각적인 산화물층의 성장 및 이 성장된 층의 비이방성 에칭에 의한 측벽절연층이 제공되고, 상기 부하저항의 단자와 MOS트랜지스터의 게이트 전극 및 소오스/ 드레인단자 또는 집적된 바이폴라 트랜지스터의 에미터 및 베이스단자가 산화물층으로 덮여지지 않은 구조의 단결정 및 다결정 실리콘 표면 위로 고융점의 금속실라사이드를 선택적으로 성장시키는 것에 의해 형성되는 것을 특징으로 하는 집적회로이 제작방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019870012957A 1986-11-18 1987-11-18 반도체 집적회로 및 그 제조방법 KR970000426B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE3639357.6 1986-11-18
DE3639357 1986-11-18
DEP3639357.6 1986-11-18

Publications (2)

Publication Number Publication Date
KR880006781A true KR880006781A (ko) 1988-07-25
KR970000426B1 KR970000426B1 (ko) 1997-01-09

Family

ID=6314192

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019870012957A KR970000426B1 (ko) 1986-11-18 1987-11-18 반도체 집적회로 및 그 제조방법

Country Status (7)

Country Link
US (1) US5013678A (ko)
EP (1) EP0272433B1 (ko)
JP (1) JPS63141349A (ko)
KR (1) KR970000426B1 (ko)
AT (1) ATE87766T1 (ko)
CA (1) CA1303250C (ko)
DE (1) DE3785162D1 (ko)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5457062A (en) * 1989-06-30 1995-10-10 Texas Instruments Incorporated Method for forming gigaohm load for BiCMOS process
US5172211A (en) * 1990-01-12 1992-12-15 Paradigm Technology, Inc. High resistance polysilicon load resistor
US5168076A (en) * 1990-01-12 1992-12-01 Paradigm Technology, Inc. Method of fabricating a high resistance polysilicon load resistor
FR2658951B1 (fr) * 1990-02-23 1992-05-07 Bonis Maurice Procede de fabrication d'un circuit integre pour filiere analogique rapide utilisant des lignes d'interconnexions locales en siliciure.
US5134088A (en) * 1990-04-27 1992-07-28 Digital Equipment Corporation Precision resistor in self-aligned silicided mos process
EP0469214A1 (en) * 1990-07-31 1992-02-05 International Business Machines Corporation Method of forming stacked conductive and/or resistive polysilicon lands in multilevel semiconductor chips and structures resulting therefrom
JPH04355912A (ja) * 1990-08-09 1992-12-09 Seiko Epson Corp 半導体装置及びその製造方法
US5462894A (en) * 1991-08-06 1995-10-31 Sgs-Thomson Microelectronics, Inc. Method for fabricating a polycrystalline silicon resistive load element in an integrated circuit
US5236857A (en) * 1991-10-30 1993-08-17 Texas Instruments Incorporated Resistor structure and process
JP2762851B2 (ja) * 1992-07-27 1998-06-04 日本電気株式会社 半導体装置の製造方法
JP2705476B2 (ja) * 1992-08-07 1998-01-28 ヤマハ株式会社 半導体装置の製造方法
US5268330A (en) * 1992-12-11 1993-12-07 International Business Machines Corporation Process for improving sheet resistance of an integrated circuit device gate
CA2093111C (en) * 1993-03-31 1997-03-18 Thomas W. Macelwee High value resistive load for an integrated circuit
GB2290167B (en) * 1994-06-08 1999-01-20 Hyundai Electronics Ind Method for fabricating a semiconductor device
DE69623440T2 (de) 1995-01-19 2003-08-07 Micron Technology Inc Verfahren zur herstellung von transistoren in einem peripheren schaltkreis
US5618749A (en) * 1995-03-31 1997-04-08 Yamaha Corporation Method of forming a semiconductor device having a capacitor and a resistor
JP2792468B2 (ja) * 1995-06-15 1998-09-03 日本電気株式会社 半導体集積回路装置の製造方法
US5585302A (en) * 1995-08-10 1996-12-17 Sony Corporation Formation of polysilicon resistors in the tungsten strapped source/drain/gate process
US5837592A (en) * 1995-12-07 1998-11-17 Taiwan Semiconductor Manufacturing Company, Ltd. Method for stabilizing polysilicon resistors
US6143613A (en) * 1997-06-30 2000-11-07 Vlsi Technology, Inc. Selective exclusion of silicide formation to make polysilicon resistors
US6100170A (en) * 1997-07-07 2000-08-08 Matsushita Electronics Corporation Method of manufacturing semiconductor device
EP0923116A1 (en) 1997-12-12 1999-06-16 STMicroelectronics S.r.l. Process for manufacturing integrated multi-crystal silicon resistors in MOS technology and integrated MOS device comprising multi-crystal silicon resistors
JP3107032B2 (ja) * 1998-03-09 2000-11-06 日本電気株式会社 半導体装置の製造方法
JP3001566B1 (ja) * 1999-02-01 2000-01-24 日本電気アイシーマイコンシステム株式会社 トランジスタ素子、その製造方法、トランジスタ回路、集積回路装置

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4187602A (en) * 1976-12-27 1980-02-12 Texas Instruments Incorporated Static memory cell using field implanted resistance
US4408385A (en) * 1978-06-15 1983-10-11 Texas Instruments Incorporated Semiconductor integrated circuit with implanted resistor element in polycrystalline silicon layer
US4367580A (en) * 1980-03-21 1983-01-11 Texas Instruments Incorporated Process for making polysilicon resistors
US4486944A (en) * 1980-06-30 1984-12-11 Inmos Corporation Method of making single poly memory cell
JPS5775453A (en) * 1980-10-29 1982-05-12 Fujitsu Ltd Semiconductor device and manufacture thereof
FR2515427A1 (fr) * 1981-10-27 1983-04-29 Efcis Procede de fabrication de resistances de forte valeur pour circuits integres
JPS58215063A (ja) * 1982-06-07 1983-12-14 Toshiba Corp 半導体装置
JPS5925244A (ja) * 1982-08-02 1984-02-09 Hitachi Ltd 半導体装置
JPS59112641A (ja) * 1982-12-20 1984-06-29 Hitachi Ltd 半導体装置及びその製造方法
US4569122A (en) * 1983-03-09 1986-02-11 Advanced Micro Devices, Inc. Method of forming a low resistance quasi-buried contact
GB2139420B (en) * 1983-05-05 1987-04-29 Standard Telephones Cables Ltd Semiconductor devices
US4528582A (en) * 1983-09-21 1985-07-09 General Electric Company Interconnection structure for polycrystalline silicon resistor and methods of making same
JPS6143464A (ja) * 1984-08-08 1986-03-03 Hitachi Ltd 半導体装置
JPS61174744A (ja) * 1985-01-30 1986-08-06 Nec Corp 集積回路装置およびその製造方法
DE3662627D1 (en) * 1985-06-03 1989-05-03 Siemens Ag Method of simultaneously producing bipolar and complementary mos transistors as a common silicon substrate
US4619038A (en) * 1985-08-15 1986-10-28 Motorola, Inc. Selective titanium silicide formation
ATE59917T1 (de) * 1985-09-13 1991-01-15 Siemens Ag Integrierte bipolar- und komplementaere mostransistoren auf einem gemeinsamen substrat enthaltende schaltung und verfahren zu ihrer herstellung.
US4737472A (en) * 1985-12-17 1988-04-12 Siemens Aktiengesellschaft Process for the simultaneous production of self-aligned bipolar transistors and complementary MOS transistors on a common silicon substrate
US4902640A (en) * 1987-04-17 1990-02-20 Tektronix, Inc. High speed double polycide bipolar/CMOS integrated circuit process

Also Published As

Publication number Publication date
JPS63141349A (ja) 1988-06-13
EP0272433B1 (de) 1993-03-31
US5013678A (en) 1991-05-07
EP0272433A2 (de) 1988-06-29
DE3785162D1 (de) 1993-05-06
KR970000426B1 (ko) 1997-01-09
ATE87766T1 (de) 1993-04-15
CA1303250C (en) 1992-06-09
EP0272433A3 (en) 1988-07-06

Similar Documents

Publication Publication Date Title
KR880006781A (ko) 반도체 집적회로 및 그 제조방법
US4074300A (en) Insulated gate type field effect transistors
US5465005A (en) Polysilicon resistor structure including polysilicon contacts
KR910001886A (ko) 반도체장치와 그 제조방법
JP2609619B2 (ja) 半導体装置
US4507846A (en) Method for making complementary MOS semiconductor devices
KR910007133A (ko) 고 성능 BiCMOS 회로를 제조하는 방법
JPH0758791B2 (ja) Ｍｏｓ型半導体装置
KR930001460A (ko) 반도체 집적회로장치 및 그 제조방법
JPH0557741B2 (ko)
US6621118B2 (en) MOSFET, semiconductor device using the same and production process therefor
JP3502509B2 (ja) Ｃｍｏｓ構造を備えた集積回路及びその製造方法
JP2729422B2 (ja) 半導体装置
JPH1050721A (ja) バイポーラ・トランジスタおよび製造方法
JPS6344769A (ja) 電界効果型トランジスタ及びその製造方法
JPH067556B2 (ja) Ｍｉｓ型半導体装置
JPS63227059A (ja) 半導体装置およびその製造方法
KR100209744B1 (ko) 반도체소자 제조방법
JPS625344B2 (ko)
JPH0484428A (ja) 半導体装置の製造方法
JPS605068B2 (ja) Ｍｏｓ形半導体装置
JP2697631B2 (ja) 半導体装置の製造方法
KR940008563B1 (ko) Sram 소자 및 그 제조방법
JP2000138347A (ja) 半導体装置の製造方法
JPH0621479A (ja) 半導体装置の製造方法及び半導体装置

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20061228

Year of fee payment: 11

LAPS Lapse due to unpaid annual fee