KR930001456A - 자기 정합된 플레이너 모놀리딕 집적회로의 종적 트랜지스터 프로세스 - Google Patents

자기 정합된 플레이너 모놀리딕 집적회로의 종적 트랜지스터 프로세스 Download PDF

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KR930001456A
KR930001456A KR1019920007856A KR920007856A KR930001456A KR 930001456 A KR930001456 A KR 930001456A KR 1019920007856 A KR1019920007856 A KR 1019920007856A KR 920007856 A KR920007856 A KR 920007856A KR 930001456 A KR930001456 A KR 930001456A
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transistor
base
substrate wafer
polysilicon
emitter
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알. 람드 아모락
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존 지. 웨브
내쇼날 세미컨덕터 코포레이션
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8222—Bipolar technology
    • H01L21/8228—Complementary devices, e.g. complementary transistors
    • H01L21/82285—Complementary vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/761—PN junctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/01—Bipolar transistors-ion implantation

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)

Abstract

내용 없음

Description

자기 정합된 플레이너 모놀리딕 집적회로의 종적 트랜지스터 프로세스
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제16도에 이르는 도면들은 PNP및 NPN트랜지스터를 형성하기위한 웨이퍼 예비에 관한 다양한 단계들을 묘사하는 실리콘 웨이퍼 부분 단면들을 나타낸다. 왼편에는 NPN트랜지스터들이 있으며, 오른편에는 PNP트랜지스터들이 있다. 도면의 치수는 일정 비율로 측정된 것이 아니며, 보다 알기쉽도록 수직 치수를 과장하여 도시하였다.

Claims (1)

  1. 제1도전율형의 반도체 기판 웨이퍼를 가지고 시작하기;상기의 기판 웨이퍼위에 비교적 얇은 패드 산화물을 형성하기;본 발명의 트랜지스터가 제작되어질 위치의 상기 패드 산화물위에 실리콘 질화물층을 형성하기;상기 트랜지스터가 필드 산화물로 둘러싸이도록, 상기 실리콘 질화물로 덮인 곳을 제외한, 상기 웨이퍼상에 비교적 두꺼운 필드 산화물을 생성하기 위하여 상기 웨이퍼를 산화시키기;상기 필드 산화물의 경계내로 상기 패드 산화물이 노출되어지도록 상기 실리콘 질화물을 제거하기;상기 트랜지스터가 제작되어질 위치의 필드 산화물을 경계로 하여 노출된 패드 산화물위에, 상기 트랜지스터 링크베이스 영역을 규정하는 형태로 된 링크베이스 에치 레지스트 패턴을 형성하기;상기 링크 베이스 에치 레지스트 패턴에 의해 노출된 위치의 상기 얇은 패드 산화물을 에칭하여서, 그로인해 링크 베이스 영역들 위에 얇은 패드 산화물을 남기기;상기 기판 웨이퍼 위에 한층의 폴리실리콘을 적립시키기;상기 트랜지스터 외인성 베이스 영역위에 위치하는 폴리실리콘을 노출시키도록 상기 기판웨이퍼 위에 이온 주입 마스크를 형성시키기;다량의 불순물을 주입하여, 상기 폴리실리콘내 기판 웨이퍼를 트랜지스터 베이스 도전율형(type)으로 도핑시켜서 그로인해 상기 트랜지스터 외인성 베이스 영역내의 상기 폴리실리콘을 진하게 도핑시키기;트랜지스터 외인성 베이스 및 에미터 영역들내의 기판 웨이퍼가 덮이도록 상기 기판 웨이퍼에 에치-레지스트를 가하기;상기 외인성 베이스 마스크 및 에미터 마스크로 덮인 외인성 베이스 및 에미터 영역들내를 제외한 폴리실리콘을 제거하기 위하여 기판 웨이퍼를 에칭하기;상기한 다량의 불순물 적립을 상기 폴리실리콘이 상기 기판 웨이퍼와 접촉하는 위치의 기판 웨이퍼내로 확산시키기 위하여 기판 웨이퍼를 가열하여서, 그로인해 상기 트랜지스터 외인성 베이스를 형성하기;상기 트랜지스터의 진성, 외인성 및 링크 베이스영역을 노출시키도록, 트랜지스터 베이스 이온주입을 정확히 제한하도록 하는 상기 필드 산화물에 포개진 개방구를 가진 트랜지스터 베이스 이온-주입 마스크를 가하기;원하는 트랜지스터 진성 베이스 도전율을 제공하도록 선택된 양과 상기 패드 산화물을 침투하여 노출된 모든 폴리실리콘내로 충분히 들어갈 수 있을 정도의 에너지로써, 실리콘 웨이퍼를 상기 트랜지스터 베이스 도전율형으로 도핑시킬 불순물을 이온 주입하기;상기 진성 및 링크베이스 영역을 생성하기 위하여 상기 웨이퍼내로 베이스 이온주입되어진 불순물을 확산시키기;상기 웨이퍼에 상기 트랜지스터 에미터 영역위의 폴리실리콘을 노출시키는 개방구를 가진 이온-주입 에미터 마스크를 가하기;그에 의해 상기 노출된 폴리실리콘이 에미터 불순물 원자들로 진하게 도핑되기 위하여 상기 기판 웨이퍼를 트랜지스터 에미터 도전율 형으로 도핑시킬 비교적 다량의 불순물을 이온주입하기;및 자기 정합 프로세스를 통해 상기 패드 산화물이 에미터를 규정하도록 폴리실리콘이 기판 웨이퍼 표면과 접촉하는 장소인 상기 패드 산화물로 제한된 영역의 기판 웨이퍼내로 상기한 에미터 불순물 원자들을 확산시키기 위하여 기판 웨이퍼를 가열하기의 단계로 구성되는 상기 트랜지스터가 에미터 영역, 켈렉트 영역, 외인성 베이스 영역, 진성 베이스 영역 및 외인성과 진성 베이스 영역들을 연결하는 링크 베이스 영역을 포함하는 자기정합 트랜지스터 제작 프로세스.
    ※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.
KR1019920007856A 1991-06-18 1992-05-09 자기정합된 플레이너 모놀리딕 집적회로의 종적 트랜지스터 프로세스 KR100222116B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US91-716,890 1991-06-18
US07/716,890 US5128272A (en) 1991-06-18 1991-06-18 Self-aligned planar monolithic integrated circuit vertical transistor process

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KR930001456A true KR930001456A (ko) 1993-01-16
KR100222116B1 KR100222116B1 (ko) 1999-10-01

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US (1) US5128272A (ko)
EP (1) EP0519592B1 (ko)
JP (1) JP3098848B2 (ko)
KR (1) KR100222116B1 (ko)
DE (1) DE69216304T2 (ko)

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US9805935B2 (en) 2015-12-31 2017-10-31 International Business Machines Corporation Bottom source/drain silicidation for vertical field-effect transistor (FET)
US10002962B2 (en) 2016-04-27 2018-06-19 International Business Machines Corporation Vertical FET structure
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US9842931B1 (en) 2016-06-09 2017-12-12 International Business Machines Corporation Self-aligned shallow trench isolation and doping for vertical fin transistors
US9853127B1 (en) 2016-06-22 2017-12-26 International Business Machines Corporation Silicidation of bottom source/drain sheet using pinch-off sacrificial spacer process
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Publication number Publication date
US5128272A (en) 1992-07-07
EP0519592A3 (en) 1993-10-13
DE69216304T2 (de) 1997-07-24
EP0519592B1 (en) 1997-01-02
DE69216304D1 (de) 1997-02-13
KR100222116B1 (ko) 1999-10-01
JPH05160353A (ja) 1993-06-25
JP3098848B2 (ja) 2000-10-16
EP0519592A2 (en) 1992-12-23

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