DE69216304D1 - Verfahren zum Herstellen eines selbst-ausrichtenden, planaren, monolithischen integrierten Schaltkreises mit vertikalen Transistoren - Google Patents
Verfahren zum Herstellen eines selbst-ausrichtenden, planaren, monolithischen integrierten Schaltkreises mit vertikalen TransistorenInfo
- Publication number
- DE69216304D1 DE69216304D1 DE69216304T DE69216304T DE69216304D1 DE 69216304 D1 DE69216304 D1 DE 69216304D1 DE 69216304 T DE69216304 T DE 69216304T DE 69216304 T DE69216304 T DE 69216304T DE 69216304 D1 DE69216304 D1 DE 69216304D1
- Authority
- DE
- Germany
- Prior art keywords
- aligning
- planar
- self
- making
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004519 manufacturing process Methods 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8222—Bipolar technology
- H01L21/8228—Complementary devices, e.g. complementary transistors
- H01L21/82285—Complementary vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/761—PN junctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/01—Bipolar transistors-ion implantation
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Bipolar Integrated Circuits (AREA)
- Bipolar Transistors (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/716,890 US5128272A (en) | 1991-06-18 | 1991-06-18 | Self-aligned planar monolithic integrated circuit vertical transistor process |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69216304D1 true DE69216304D1 (de) | 1997-02-13 |
DE69216304T2 DE69216304T2 (de) | 1997-07-24 |
Family
ID=24879878
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69216304T Expired - Fee Related DE69216304T2 (de) | 1991-06-18 | 1992-05-01 | Verfahren zum Herstellen eines selbst-ausrichtenden, planaren, monolithischen integrierten Schaltkreises mit vertikalen Transistoren |
Country Status (5)
Country | Link |
---|---|
US (1) | US5128272A (de) |
EP (1) | EP0519592B1 (de) |
JP (1) | JP3098848B2 (de) |
KR (1) | KR100222116B1 (de) |
DE (1) | DE69216304T2 (de) |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5358883A (en) * | 1992-02-03 | 1994-10-25 | Motorola, Inc. | Lateral bipolar transistor |
US5416687A (en) * | 1992-06-23 | 1995-05-16 | Delta Coventry Corporation | Power factor correction circuit for AC to DC power supply |
US5411900A (en) * | 1993-03-05 | 1995-05-02 | Deutsche Itt Industries, Gmbh | Method of fabricating a monolithic integrated circuit with at least one CMOS field-effect transistor and one NPN bipolar transistor |
KR0138352B1 (ko) * | 1993-12-17 | 1998-04-28 | 김광호 | 반도체 장치 및 그의 제조방법 |
US6437381B1 (en) | 2000-04-27 | 2002-08-20 | International Business Machines Corporation | Semiconductor memory device with reduced orientation-dependent oxidation in trench structures |
US20020118850A1 (en) * | 2000-08-02 | 2002-08-29 | Yeh Jer-Liang (Andrew) | Micromachine directional microphone and associated method |
US9805935B2 (en) | 2015-12-31 | 2017-10-31 | International Business Machines Corporation | Bottom source/drain silicidation for vertical field-effect transistor (FET) |
US10002962B2 (en) | 2016-04-27 | 2018-06-19 | International Business Machines Corporation | Vertical FET structure |
US9812567B1 (en) | 2016-05-05 | 2017-11-07 | International Business Machines Corporation | Precise control of vertical transistor gate length |
US9653575B1 (en) | 2016-05-09 | 2017-05-16 | International Business Machines Corporation | Vertical transistor with a body contact for back-biasing |
US9842931B1 (en) | 2016-06-09 | 2017-12-12 | International Business Machines Corporation | Self-aligned shallow trench isolation and doping for vertical fin transistors |
US9853127B1 (en) | 2016-06-22 | 2017-12-26 | International Business Machines Corporation | Silicidation of bottom source/drain sheet using pinch-off sacrificial spacer process |
US10217863B2 (en) | 2016-06-28 | 2019-02-26 | International Business Machines Corporation | Fabrication of a vertical fin field effect transistor with an asymmetric gate structure |
US10243073B2 (en) | 2016-08-19 | 2019-03-26 | International Business Machines Corporation | Vertical channel field-effect transistor (FET) process compatible long channel transistors |
US9704990B1 (en) | 2016-09-19 | 2017-07-11 | International Business Machines Corporation | Vertical FET with strained channel |
US10312346B2 (en) | 2016-10-19 | 2019-06-04 | International Business Machines Corporation | Vertical transistor with variable gate length |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4110126A (en) * | 1977-08-31 | 1978-08-29 | International Business Machines Corporation | NPN/PNP Fabrication process with improved alignment |
JPS56115525A (en) * | 1980-02-18 | 1981-09-10 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Manufacture of semiconductor device |
US4309812A (en) * | 1980-03-03 | 1982-01-12 | International Business Machines Corporation | Process for fabricating improved bipolar transistor utilizing selective etching |
DE3314450A1 (de) * | 1983-04-21 | 1984-10-25 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zum herstellen von hochintegrierten komplementaeren mos-feldeffekttransistorschaltungen |
US4940671A (en) * | 1986-04-18 | 1990-07-10 | National Semiconductor Corporation | High voltage complementary NPN/PNP process |
US4933295A (en) * | 1987-05-08 | 1990-06-12 | Raytheon Company | Method of forming a bipolar transistor having closely spaced device regions |
IT1231913B (it) * | 1987-10-23 | 1992-01-15 | Sgs Microelettronica Spa | Procedimento di fabbricazione di transistori ad alta frequenza. |
EP0375323A1 (de) * | 1988-12-22 | 1990-06-27 | Texas Instruments Incorporated | Ein vertikaler Hochleistungs-Bipolartransistor, Kompatibel mit einer hochwertigen ECL-Bipolar-Technologie und dessen Herstellungsverfahren |
US4910160A (en) * | 1989-06-06 | 1990-03-20 | National Semiconductor Corporation | High voltage complementary NPN/PNP process |
-
1991
- 1991-06-18 US US07/716,890 patent/US5128272A/en not_active Expired - Lifetime
-
1992
- 1992-05-01 EP EP92303984A patent/EP0519592B1/de not_active Expired - Lifetime
- 1992-05-01 DE DE69216304T patent/DE69216304T2/de not_active Expired - Fee Related
- 1992-05-09 KR KR1019920007856A patent/KR100222116B1/ko not_active IP Right Cessation
- 1992-05-11 JP JP04117071A patent/JP3098848B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US5128272A (en) | 1992-07-07 |
EP0519592A3 (en) | 1993-10-13 |
DE69216304T2 (de) | 1997-07-24 |
EP0519592B1 (de) | 1997-01-02 |
KR100222116B1 (ko) | 1999-10-01 |
JPH05160353A (ja) | 1993-06-25 |
JP3098848B2 (ja) | 2000-10-16 |
KR930001456A (ko) | 1993-01-16 |
EP0519592A2 (de) | 1992-12-23 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |