DE69022710D1 - Verfahren zum Herstellen einer Halbleitervorrichtung. - Google Patents

Verfahren zum Herstellen einer Halbleitervorrichtung.

Info

Publication number
DE69022710D1
DE69022710D1 DE69022710T DE69022710T DE69022710D1 DE 69022710 D1 DE69022710 D1 DE 69022710D1 DE 69022710 T DE69022710 T DE 69022710T DE 69022710 T DE69022710 T DE 69022710T DE 69022710 D1 DE69022710 D1 DE 69022710D1
Authority
DE
Germany
Prior art keywords
manufacturing
semiconductor device
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69022710T
Other languages
English (en)
Other versions
DE69022710T2 (de
Inventor
Yoshiki Yamada
Bunshiro Yamaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of DE69022710D1 publication Critical patent/DE69022710D1/de
Application granted granted Critical
Publication of DE69022710T2 publication Critical patent/DE69022710T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66272—Silicon vertical transistors
    • H01L29/66295—Silicon vertical transistors with main current going through the whole silicon substrate, e.g. power bipolar transistor
    • H01L29/66303—Silicon vertical transistors with main current going through the whole silicon substrate, e.g. power bipolar transistor with multi-emitter, e.g. interdigitated, multi-cellular or distributed emitter
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66272—Silicon vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/011—Bipolar transistors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/124—Polycrystalline emitter

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Bipolar Transistors (AREA)
DE69022710T 1990-01-26 1990-12-11 Verfahren zum Herstellen einer Halbleitervorrichtung. Expired - Fee Related DE69022710T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2017300A JPH07114210B2 (ja) 1990-01-26 1990-01-26 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
DE69022710D1 true DE69022710D1 (de) 1995-11-02
DE69022710T2 DE69022710T2 (de) 1996-03-21

Family

ID=11940153

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69022710T Expired - Fee Related DE69022710T2 (de) 1990-01-26 1990-12-11 Verfahren zum Herstellen einer Halbleitervorrichtung.

Country Status (5)

Country Link
US (1) US5100812A (de)
EP (1) EP0438693B1 (de)
JP (1) JPH07114210B2 (de)
KR (1) KR930006736B1 (de)
DE (1) DE69022710T2 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5386623A (en) * 1990-11-15 1995-02-07 Hitachi, Ltd. Process for manufacturing a multi-chip module
US5665991A (en) * 1992-03-13 1997-09-09 Texas Instruments Incorporated Device having current ballasting and busing over active area using a multi-level conductor process
US5328857A (en) * 1992-09-25 1994-07-12 Sgs-Thomson Microelectronics, Inc. Method of forming a bilevel, self aligned, low base resistance semiconductor structure
US5492844A (en) * 1993-01-29 1996-02-20 Sgs-Thomson Microelectronics, Inc. Method of manufacturing increased conductivity base contact/feeders with self-aligned structures
KR0161378B1 (ko) * 1994-06-13 1998-12-01 김광호 바이폴라 접합 트랜지스터 제조방법
US5597758A (en) * 1994-08-01 1997-01-28 Motorola, Inc. Method for forming an electrostatic discharge protection device
JP2637937B2 (ja) * 1995-01-30 1997-08-06 関西日本電気株式会社 電界効果トランジスタの製造方法
US5670417A (en) * 1996-03-25 1997-09-23 Motorola, Inc. Method for fabricating self-aligned semiconductor component
US6121129A (en) * 1997-01-15 2000-09-19 International Business Machines Corporation Method of contact structure formation
IT1298516B1 (it) * 1998-01-30 2000-01-12 Sgs Thomson Microelectronics Dispositivo elettronico di potenza integrato su un materiale semiconduttore e relativo processo di fabricazione
US6444536B2 (en) * 1999-07-08 2002-09-03 Agere Systems Guardian Corp. Method for fabricating bipolar transistors
JP4468609B2 (ja) * 2001-05-21 2010-05-26 株式会社ルネサステクノロジ 半導体装置

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2168982B1 (de) * 1972-01-28 1976-06-11 Radiotechnique Compelec
US4566176A (en) * 1984-05-23 1986-01-28 U.S. Philips Corporation Method of manufacturing transistors
US4640721A (en) * 1984-06-06 1987-02-03 Hitachi, Ltd. Method of forming bipolar transistors with graft base regions
JPS6146063A (ja) * 1984-08-10 1986-03-06 Hitachi Ltd 半導体装置の製造方法
JPS6267868A (ja) * 1985-09-20 1987-03-27 Fujitsu Ltd 半導体装置の製造方法
JPS63193562A (ja) * 1987-02-06 1988-08-10 Toshiba Corp バイポ−ラトランジスタの製造方法
JPS63237471A (ja) * 1987-03-26 1988-10-03 Toshiba Corp 半導体装置及びその製造方法
JPH0626217B2 (ja) * 1987-11-11 1994-04-06 日本電気株式会社 半導体装置の製造方法
JPH06129172A (ja) * 1992-10-14 1994-05-10 Fujisash Co 組付け網戸装置の組付構造

Also Published As

Publication number Publication date
US5100812A (en) 1992-03-31
EP0438693A3 (en) 1992-03-04
JPH07114210B2 (ja) 1995-12-06
JPH03222336A (ja) 1991-10-01
EP0438693B1 (de) 1995-09-27
EP0438693A2 (de) 1991-07-31
KR930006736B1 (ko) 1993-07-23
DE69022710T2 (de) 1996-03-21

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee