DE3861889D1 - Verfahren zum herstellen von loechern in integrierten halbleiterschaltungen. - Google Patents
Verfahren zum herstellen von loechern in integrierten halbleiterschaltungen.Info
- Publication number
- DE3861889D1 DE3861889D1 DE8888105978T DE3861889T DE3861889D1 DE 3861889 D1 DE3861889 D1 DE 3861889D1 DE 8888105978 T DE8888105978 T DE 8888105978T DE 3861889 T DE3861889 T DE 3861889T DE 3861889 D1 DE3861889 D1 DE 3861889D1
- Authority
- DE
- Germany
- Prior art keywords
- integrated semiconductor
- semiconductor circuits
- producing holes
- holes
- producing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Bipolar Transistors (AREA)
- Drying Of Semiconductors (AREA)
- Weting (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62091876A JPS63258021A (ja) | 1987-04-16 | 1987-04-16 | 接続孔の形成方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
DE3861889D1 true DE3861889D1 (de) | 1991-04-11 |
Family
ID=14038761
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8888105978T Expired - Lifetime DE3861889D1 (de) | 1987-04-16 | 1988-04-14 | Verfahren zum herstellen von loechern in integrierten halbleiterschaltungen. |
Country Status (5)
Country | Link |
---|---|
US (1) | US4857141A (de) |
EP (1) | EP0287096B1 (de) |
JP (1) | JPS63258021A (de) |
KR (1) | KR910006370B1 (de) |
DE (1) | DE3861889D1 (de) |
Families Citing this family (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2611273B2 (ja) * | 1987-11-12 | 1997-05-21 | 株式会社デンソー | 半導体装置の製造方法 |
JPH02237135A (ja) * | 1989-03-10 | 1990-09-19 | Fujitsu Ltd | 半導体装置の製造方法 |
EP0410635A1 (de) * | 1989-07-28 | 1991-01-30 | AT&T Corp. | Verfahren zum Aetzen von Oeffnungen mit abgeschrägten Flanken bei der Herstellung von Integrierten Halbleiterschaltungsbauelementen |
US5254213A (en) * | 1989-10-25 | 1993-10-19 | Matsushita Electric Industrial Co., Ltd. | Method of forming contact windows |
US5043790A (en) * | 1990-04-05 | 1991-08-27 | Ramtron Corporation | Sealed self aligned contacts using two nitrides process |
DE4028776C2 (de) * | 1990-07-03 | 1994-03-10 | Samsung Electronics Co Ltd | Verfahren zur Bildung einer metallischen Verdrahtungsschicht und Füllen einer Kontaktöffnung in einem Halbleiterbauelement |
JP2699644B2 (ja) * | 1990-10-30 | 1998-01-19 | 日本電気株式会社 | 半導体装置の製造方法 |
DE4200809C2 (de) * | 1991-03-20 | 1996-12-12 | Samsung Electronics Co Ltd | Verfahren zur Bildung einer metallischen Verdrahtungsschicht in einem Halbleiterbauelement |
KR940003566B1 (ko) * | 1991-04-15 | 1994-04-23 | 삼성전자 주식회사 | 반도체 장치의 다층배선의 형성방법 |
JP2694395B2 (ja) * | 1991-04-17 | 1997-12-24 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
US5203957A (en) * | 1991-06-12 | 1993-04-20 | Taiwan Semiconductor Manufacturing Company | Contact sidewall tapering with argon sputtering |
US5420078A (en) * | 1991-08-14 | 1995-05-30 | Vlsi Technology, Inc. | Method for producing via holes in integrated circuit layers |
EP0540261B1 (de) * | 1991-10-31 | 1997-05-28 | STMicroelectronics, Inc. | Verfahren zur Entfernung von Polymeren aus Sacklöchern in Halbleitervorrichtungen |
JPH0730095A (ja) * | 1993-06-25 | 1995-01-31 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
KR0126801B1 (ko) * | 1993-12-22 | 1998-04-02 | 김광호 | 반도체 장치의 배선 형성방법 |
US5391513A (en) * | 1993-12-22 | 1995-02-21 | Vlsi Technology, Inc. | Wet/dry anti-fuse via etch |
US5597983A (en) * | 1994-02-03 | 1997-01-28 | Sgs-Thomson Microelectronics, Inc. | Process of removing polymers in semiconductor vias |
US5610099A (en) * | 1994-06-28 | 1997-03-11 | Ramtron International Corporation | Process for fabricating transistors using composite nitride structure |
US5453403A (en) * | 1994-10-24 | 1995-09-26 | Chartered Semiconductor Manufacturing Pte, Ltd. | Method of beveled contact opening formation |
KR0168338B1 (ko) * | 1995-05-31 | 1998-12-15 | 김광호 | 랜딩 패드를 갖는 반도체 메모리 장치의 제조방법 |
US5734192A (en) * | 1995-12-22 | 1998-03-31 | International Business Machines Corporation | Trench isolation for active areas and first level conductors |
KR100227636B1 (ko) * | 1995-12-29 | 1999-11-01 | 김영환 | 반도체 소자의 콘택 홀 형성 방법 |
US5746884A (en) * | 1996-08-13 | 1998-05-05 | Advanced Micro Devices, Inc. | Fluted via formation for superior metal step coverage |
JP3050161B2 (ja) * | 1997-04-18 | 2000-06-12 | 日本電気株式会社 | 半導体装置及びその製造方法 |
US6653686B2 (en) | 1998-07-13 | 2003-11-25 | International Business Machines Corporation | Structure and method of controlling short-channel effect of very short channel MOSFET |
GB2387026A (en) * | 2002-03-28 | 2003-10-01 | Zarlink Semiconductor Ltd | Method of coating contact holes in MEMS and micro-machining applications |
FR3091410B1 (fr) * | 2018-12-26 | 2021-01-15 | St Microelectronics Crolles 2 Sas | Procédé de gravure |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5690525A (en) * | 1979-11-28 | 1981-07-22 | Fujitsu Ltd | Manufacture of semiconductor device |
US4461672A (en) * | 1982-11-18 | 1984-07-24 | Texas Instruments, Inc. | Process for etching tapered vias in silicon dioxide |
US4495220A (en) * | 1983-10-07 | 1985-01-22 | Trw Inc. | Polyimide inter-metal dielectric process |
US4487652A (en) * | 1984-03-30 | 1984-12-11 | Motorola, Inc. | Slope etch of polyimide |
US4484979A (en) * | 1984-04-16 | 1984-11-27 | At&T Bell Laboratories | Two-step anisotropic etching process for patterning a layer without penetrating through an underlying thinner layer |
US4522681A (en) * | 1984-04-23 | 1985-06-11 | General Electric Company | Method for tapered dry etching |
US4560436A (en) * | 1984-07-02 | 1985-12-24 | Motorola, Inc. | Process for etching tapered polyimide vias |
JPS61187332A (ja) * | 1985-02-15 | 1986-08-21 | Sumitomo Electric Ind Ltd | スル−・ホ−ルの形成方法 |
US4705597A (en) * | 1985-04-15 | 1987-11-10 | Harris Corporation | Photoresist tapering process |
US4645562A (en) * | 1985-04-29 | 1987-02-24 | Hughes Aircraft Company | Double layer photoresist technique for side-wall profile control in plasma etching processes |
US4631248A (en) * | 1985-06-21 | 1986-12-23 | Lsi Logic Corporation | Method for forming an electrical contact in an integrated circuit |
EP0237844A1 (de) * | 1986-03-18 | 1987-09-23 | BBC Brown Boveri AG | Verfahren zur Herstellung einer Abdeckschicht für die Halbleitertechnik sowie Verwendung der Abdeckschicht |
-
1987
- 1987-04-16 JP JP62091876A patent/JPS63258021A/ja active Pending
-
1988
- 1988-04-13 US US07/181,108 patent/US4857141A/en not_active Expired - Lifetime
- 1988-04-14 DE DE8888105978T patent/DE3861889D1/de not_active Expired - Lifetime
- 1988-04-14 EP EP88105978A patent/EP0287096B1/de not_active Expired - Lifetime
- 1988-04-16 KR KR1019880004359A patent/KR910006370B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR880013239A (ko) | 1988-11-30 |
EP0287096A1 (de) | 1988-10-19 |
JPS63258021A (ja) | 1988-10-25 |
KR910006370B1 (ko) | 1991-08-21 |
US4857141A (en) | 1989-08-15 |
EP0287096B1 (de) | 1991-03-06 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8320 | Willingness to grant licences declared (paragraph 23) |