DE3850624D1 - Verfahren zum Herstellen von Halbleiterkontakten. - Google Patents

Verfahren zum Herstellen von Halbleiterkontakten.

Info

Publication number
DE3850624D1
DE3850624D1 DE3850624T DE3850624T DE3850624D1 DE 3850624 D1 DE3850624 D1 DE 3850624D1 DE 3850624 T DE3850624 T DE 3850624T DE 3850624 T DE3850624 T DE 3850624T DE 3850624 D1 DE3850624 D1 DE 3850624D1
Authority
DE
Germany
Prior art keywords
making semiconductor
semiconductor contacts
contacts
making
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3850624T
Other languages
English (en)
Other versions
DE3850624T2 (de
Inventor
E Henry Stevens
Paul John Mcclure
Christopher Warren Hill
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thorn EMI North America Inc
Original Assignee
Thorn EMI North America Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thorn EMI North America Inc filed Critical Thorn EMI North America Inc
Publication of DE3850624D1 publication Critical patent/DE3850624D1/de
Application granted granted Critical
Publication of DE3850624T2 publication Critical patent/DE3850624T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/112—Nitridation, direct, of silicon
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/118—Oxide films
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/147—Silicides
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/915—Active solid-state devices, e.g. transistors, solid-state diodes with titanium nitride portion or region

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE3850624T 1987-08-24 1988-08-23 Verfahren zum Herstellen von Halbleiterkontakten. Expired - Fee Related DE3850624T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/088,681 US4784973A (en) 1987-08-24 1987-08-24 Semiconductor contact silicide/nitride process with control for silicide thickness

Publications (2)

Publication Number Publication Date
DE3850624D1 true DE3850624D1 (de) 1994-08-18
DE3850624T2 DE3850624T2 (de) 1994-12-22

Family

ID=22212799

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3850624T Expired - Fee Related DE3850624T2 (de) 1987-08-24 1988-08-23 Verfahren zum Herstellen von Halbleiterkontakten.

Country Status (4)

Country Link
US (1) US4784973A (de)
EP (1) EP0305147B1 (de)
JP (1) JP2598479B2 (de)
DE (1) DE3850624T2 (de)

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US5874766A (en) * 1988-12-20 1999-02-23 Matsushita Electric Industrial Co., Ltd. Semiconductor device having an oxynitride film
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US4977440A (en) * 1989-01-04 1990-12-11 Stevens E Henry Structure and process for contacting and interconnecting semiconductor devices within an integrated circuit
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US5229311A (en) * 1989-03-22 1993-07-20 Intel Corporation Method of reducing hot-electron degradation in semiconductor devices
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JP2586345B2 (ja) * 1994-10-14 1997-02-26 日本電気株式会社 コバルトシリサイド膜より成る半導体装置及び該装置の製造方法
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Also Published As

Publication number Publication date
EP0305147B1 (de) 1994-07-13
JP2598479B2 (ja) 1997-04-09
US4784973A (en) 1988-11-15
JPH01144625A (ja) 1989-06-06
EP0305147A1 (de) 1989-03-01
DE3850624T2 (de) 1994-12-22

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee