DE3684380D1 - Verfahren zum einebnen von halbleiteranordnungen. - Google Patents
Verfahren zum einebnen von halbleiteranordnungen.Info
- Publication number
- DE3684380D1 DE3684380D1 DE8686108755T DE3684380T DE3684380D1 DE 3684380 D1 DE3684380 D1 DE 3684380D1 DE 8686108755 T DE8686108755 T DE 8686108755T DE 3684380 T DE3684380 T DE 3684380T DE 3684380 D1 DE3684380 D1 DE 3684380D1
- Authority
- DE
- Germany
- Prior art keywords
- semiconductor arrangements
- leveling
- leveling semiconductor
- arrangements
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/312—Organic layers, e.g. photoresist
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Formation Of Insulating Films (AREA)
- Local Oxidation Of Silicon (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US06/766,629 US4665007A (en) | 1985-08-19 | 1985-08-19 | Planarization process for organic filling of deep trenches |
Publications (1)
Publication Number | Publication Date |
---|---|
DE3684380D1 true DE3684380D1 (de) | 1992-04-23 |
Family
ID=25077031
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8686108755T Expired - Fee Related DE3684380D1 (de) | 1985-08-19 | 1986-06-27 | Verfahren zum einebnen von halbleiteranordnungen. |
Country Status (5)
Country | Link |
---|---|
US (1) | US4665007A (de) |
EP (1) | EP0212149B1 (de) |
JP (1) | JPS6245043A (de) |
CA (1) | CA1233914A (de) |
DE (1) | DE3684380D1 (de) |
Families Citing this family (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4839311A (en) * | 1987-08-14 | 1989-06-13 | National Semiconductor Corporation | Etch back detection |
US5068959A (en) * | 1988-07-11 | 1991-12-03 | Digital Equipment Corporation | Method of manufacturing a thin film head |
US5091289A (en) * | 1990-04-30 | 1992-02-25 | International Business Machines Corporation | Process for forming multi-level coplanar conductor/insulator films employing photosensitive polyimide polymer compositions |
US5229257A (en) * | 1990-04-30 | 1993-07-20 | International Business Machines Corporation | Process for forming multi-level coplanar conductor/insulator films employing photosensitive polymide polymer compositions |
US5217831A (en) * | 1991-03-22 | 1993-06-08 | At&T Bell Laboratories | Sub-micron device fabrication |
US5276126A (en) * | 1991-11-04 | 1994-01-04 | Ocg Microelectronic Materials, Inc. | Selected novolak resin planarization layer for lithographic applications |
US5320864A (en) * | 1992-06-29 | 1994-06-14 | Lsi Logic Corporation | Sedimentary deposition of photoresist on semiconductor wafers |
US5330883A (en) * | 1992-06-29 | 1994-07-19 | Lsi Logic Corporation | Techniques for uniformizing photoresist thickness and critical dimension of underlying features |
US5618751A (en) * | 1996-05-23 | 1997-04-08 | International Business Machines Corporation | Method of making single-step trenches using resist fill and recess |
US5851899A (en) * | 1996-08-08 | 1998-12-22 | Siemens Aktiengesellschaft | Gapfill and planarization process for shallow trench isolation |
US6020256A (en) * | 1996-12-18 | 2000-02-01 | Lucent Technologies Inc. | Method of integrated circuit fabrication |
JP3373748B2 (ja) * | 1997-02-07 | 2003-02-04 | 株式会社東芝 | 半導体装置の製造方法 |
US6136665A (en) * | 1998-06-03 | 2000-10-24 | United Microelectronics Corp. | Method for forming a recess-free buffer layer |
US6221560B1 (en) | 1999-08-12 | 2001-04-24 | Chartered Semiconductor Manufacturing Ltd. | Method to enhance global planarization of silicon oxide surface for IC device fabrication |
WO2001015211A1 (en) | 1999-08-26 | 2001-03-01 | Brewer Science | Improved fill material for dual damascene processes |
US20040034134A1 (en) * | 1999-08-26 | 2004-02-19 | Lamb James E. | Crosslinkable fill compositions for uniformly protecting via and contact holes |
US6482716B1 (en) * | 2000-01-11 | 2002-11-19 | Infineon Technologies North America Corp. | Uniform recess depth of recessed resist layers in trench structure |
JP3794470B2 (ja) * | 2001-04-18 | 2006-07-05 | Tdk株式会社 | 薄膜磁気ヘッド、磁気ヘッド装置及び磁気記録再生装置 |
US6586313B2 (en) * | 2001-11-29 | 2003-07-01 | Stmicroelectronics S.R.L. | Method of avoiding the effects of lack of uniformity in trench isolated integrated circuits |
US7323417B2 (en) * | 2004-09-21 | 2008-01-29 | Molecular Imprints, Inc. | Method of forming a recessed structure employing a reverse tone process |
US7547504B2 (en) * | 2004-09-21 | 2009-06-16 | Molecular Imprints, Inc. | Pattern reversal employing thick residual layers |
US7205244B2 (en) * | 2004-09-21 | 2007-04-17 | Molecular Imprints | Patterning substrates employing multi-film layers defining etch-differential interfaces |
US7977032B2 (en) * | 2005-02-11 | 2011-07-12 | International Business Machines Corporation | Method to create region specific exposure in a layer |
US20070020876A1 (en) * | 2005-07-19 | 2007-01-25 | Micron Technology, Inc. | Integrated circuitry, dynamic random access memory cells, electronic systems, and semiconductor processing methods |
US20070077763A1 (en) * | 2005-09-30 | 2007-04-05 | Molecular Imprints, Inc. | Deposition technique to planarize a multi-layer structure |
US7524758B2 (en) * | 2006-02-17 | 2009-04-28 | Toshiba America Electronic Components, Inc. | Interconnect structure and method for semiconductor device |
CN100461433C (zh) * | 2007-01-04 | 2009-02-11 | 北京京东方光电科技有限公司 | 一种tft阵列结构及其制造方法 |
US20080318420A1 (en) * | 2007-06-22 | 2008-12-25 | Wong Denny K | Two step chemical mechanical polish |
US11901189B2 (en) * | 2020-02-27 | 2024-02-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Ambient controlled two-step thermal treatment for spin-on coating layer planarization |
CN113517216B (zh) * | 2020-04-09 | 2023-10-17 | 长鑫存储技术有限公司 | 沟槽隔离结构制备方法和半导体器件制备方法 |
CN113380696B (zh) * | 2021-04-26 | 2022-11-15 | 南方科技大学 | 深槽的填充方法及深槽的填充结构 |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US2559389A (en) * | 1942-04-02 | 1951-07-03 | Keuffel & Esser Co | Method of producing precision images |
US3976524A (en) * | 1974-06-17 | 1976-08-24 | Ibm Corporation | Planarization of integrated circuit surfaces through selective photoresist masking |
DE2547792C3 (de) * | 1974-10-25 | 1978-08-31 | Hitachi, Ltd., Tokio | Verfahren zur Herstellung eines Halbleiterbauelementes |
JPS588579B2 (ja) * | 1975-08-20 | 1983-02-16 | 松下電器産業株式会社 | ハンドウタイソウチノセイゾウホウホウ |
US4104086A (en) * | 1977-08-15 | 1978-08-01 | International Business Machines Corporation | Method for forming isolated regions of silicon utilizing reactive ion etching |
US4139442A (en) * | 1977-09-13 | 1979-02-13 | International Business Machines Corporation | Reactive ion etching method for producing deep dielectric isolation in silicon |
US4284659A (en) * | 1980-05-12 | 1981-08-18 | Bell Telephone Laboratories | Insulation layer reflow |
JPS56160050A (en) * | 1980-05-14 | 1981-12-09 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
US4389281A (en) * | 1980-12-16 | 1983-06-21 | International Business Machines Corporation | Method of planarizing silicon dioxide in semiconductor devices |
JPS58210634A (ja) * | 1982-05-31 | 1983-12-07 | Toshiba Corp | 半導体装置の製造方法 |
JPS6025247A (ja) * | 1983-07-21 | 1985-02-08 | Nec Corp | 半導体装置の製造方法 |
JPS6050939A (ja) * | 1983-08-30 | 1985-03-22 | Toshiba Corp | 半導体装置の製造方法 |
US4568601A (en) * | 1984-10-19 | 1986-02-04 | International Business Machines Corporation | Use of radiation sensitive polymerizable oligomers to produce polyimide negative resists and planarized dielectric components for semiconductor structures |
US4541169A (en) * | 1984-10-29 | 1985-09-17 | International Business Machines Corporation | Method for making studs for interconnecting metallization layers at different levels in a semiconductor chip |
-
1985
- 1985-08-19 US US06/766,629 patent/US4665007A/en not_active Expired - Fee Related
-
1986
- 1986-03-04 CA CA000503286A patent/CA1233914A/en not_active Expired
- 1986-06-18 JP JP61140400A patent/JPS6245043A/ja active Granted
- 1986-06-27 DE DE8686108755T patent/DE3684380D1/de not_active Expired - Fee Related
- 1986-06-27 EP EP86108755A patent/EP0212149B1/de not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0212149A3 (en) | 1989-10-18 |
EP0212149A2 (de) | 1987-03-04 |
US4665007A (en) | 1987-05-12 |
CA1233914A (en) | 1988-03-08 |
JPH0344418B2 (de) | 1991-07-05 |
JPS6245043A (ja) | 1987-02-27 |
EP0212149B1 (de) | 1992-03-18 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |