DE68914572D1 - Verfahren zum Herstellen von Halbleitervorrichtungen. - Google Patents

Verfahren zum Herstellen von Halbleitervorrichtungen.

Info

Publication number
DE68914572D1
DE68914572D1 DE68914572T DE68914572T DE68914572D1 DE 68914572 D1 DE68914572 D1 DE 68914572D1 DE 68914572 T DE68914572 T DE 68914572T DE 68914572 T DE68914572 T DE 68914572T DE 68914572 D1 DE68914572 D1 DE 68914572D1
Authority
DE
Germany
Prior art keywords
semiconductor devices
manufacturing semiconductor
manufacturing
devices
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68914572T
Other languages
English (en)
Other versions
DE68914572T2 (de
Inventor
Masahiro Intellectual Prop Abe
Yasukazu Intellectual Pro Mase
Toshihiko Intellectual Katsura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE68914572D1 publication Critical patent/DE68914572D1/de
Publication of DE68914572T2 publication Critical patent/DE68914572T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/137—Resists

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Drying Of Semiconductors (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
DE68914572T 1988-10-06 1989-10-06 Verfahren zum Herstellen von Halbleitervorrichtungen. Expired - Fee Related DE68914572T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63252701A JPH02100341A (ja) 1988-10-06 1988-10-06 半導体装置のパターン形成方法

Publications (2)

Publication Number Publication Date
DE68914572D1 true DE68914572D1 (de) 1994-05-19
DE68914572T2 DE68914572T2 (de) 1994-09-01

Family

ID=17241049

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68914572T Expired - Fee Related DE68914572T2 (de) 1988-10-06 1989-10-06 Verfahren zum Herstellen von Halbleitervorrichtungen.

Country Status (5)

Country Link
US (1) US4952528A (de)
EP (1) EP0362867B1 (de)
JP (1) JPH02100341A (de)
KR (1) KR930007840B1 (de)
DE (1) DE68914572T2 (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2515408B2 (ja) * 1989-10-31 1996-07-10 株式会社東芝 バイポ−ラ型半導体装置
US5849632A (en) * 1991-08-30 1998-12-15 Micron Technology, Inc. Method of passivating semiconductor wafers
JP2727909B2 (ja) * 1993-03-26 1998-03-18 松下電器産業株式会社 金属配線の形成方法
US5286675A (en) * 1993-04-14 1994-02-15 Industrial Technology Research Institute Blanket tungsten etchback process using disposable spin-on-glass
JP2947054B2 (ja) * 1994-03-04 1999-09-13 ヤマハ株式会社 配線形成法
US5464794A (en) * 1994-05-11 1995-11-07 United Microelectronics Corporation Method of forming contact openings having concavo-concave shape
US5646814A (en) 1994-07-15 1997-07-08 Applied Materials, Inc. Multi-electrode electrostatic chuck
US5592358A (en) 1994-07-18 1997-01-07 Applied Materials, Inc. Electrostatic chuck for magnetic flux processing
US5846876A (en) * 1996-06-05 1998-12-08 Advanced Micro Devices, Inc. Integrated circuit which uses a damascene process for producing staggered interconnect lines
US5866481A (en) * 1996-06-07 1999-02-02 Taiwan Semiconductor Manufacturing Company Ltd. Selective partial curing of spin-on-glass by ultraviolet radiation to protect integrated circuit dice near the wafer edge
US6255039B1 (en) * 1997-04-16 2001-07-03 Isola Laminate Systems Corp. Fabrication of high density multilayer interconnect printed circuit boards
JP2001308002A (ja) * 2000-02-15 2001-11-02 Canon Inc フォトマスクを用いたパターン作製方法、及びパターン作製装置
US7136681B2 (en) * 2001-10-31 2006-11-14 Telefonaktiebolaget Lm Ericsson (Publ) Electrically conductive carrier and patterning for controlling current distribution in a wireless communications device
US7404167B2 (en) * 2005-02-23 2008-07-22 Taiwan Semiconductor Manufacturing Company, Ltd. Method for improving design window
JP4665631B2 (ja) * 2005-07-07 2011-04-06 セイコーエプソン株式会社 電子基板とその製造方法及び電気光学装置の製造方法並びに電子機器の製造方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4253888A (en) * 1978-06-16 1981-03-03 Matsushita Electric Industrial Co., Ltd. Pretreatment of photoresist masking layers resulting in higher temperature device processing
NL181611C (nl) * 1978-11-14 1987-09-16 Philips Nv Werkwijze ter vervaardiging van een bedradingssysteem, alsmede een halfgeleiderinrichting voorzien van een dergelijk bedradingssysteem.

Also Published As

Publication number Publication date
EP0362867A2 (de) 1990-04-11
US4952528A (en) 1990-08-28
EP0362867B1 (de) 1994-04-13
DE68914572T2 (de) 1994-09-01
JPH0587179B2 (de) 1993-12-15
KR930007840B1 (ko) 1993-08-20
EP0362867A3 (de) 1992-07-08
JPH02100341A (ja) 1990-04-12
KR900007050A (ko) 1990-05-09

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee