DE3575241D1 - Halbleiteranordnung und verfahren zum herstellen derselben. - Google Patents

Halbleiteranordnung und verfahren zum herstellen derselben.

Info

Publication number
DE3575241D1
DE3575241D1 DE8585306249T DE3575241T DE3575241D1 DE 3575241 D1 DE3575241 D1 DE 3575241D1 DE 8585306249 T DE8585306249 T DE 8585306249T DE 3575241 T DE3575241 T DE 3575241T DE 3575241 D1 DE3575241 D1 DE 3575241D1
Authority
DE
Germany
Prior art keywords
producing
same
semiconductor arrangement
semiconductor
arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8585306249T
Other languages
English (en)
Inventor
Tadashi C O Patent Div Shibata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE3575241D1 publication Critical patent/DE3575241D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
DE8585306249T 1984-09-03 1985-09-03 Halbleiteranordnung und verfahren zum herstellen derselben. Expired - Lifetime DE3575241D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59182810A JPS6161441A (ja) 1984-09-03 1984-09-03 半導体装置の製造方法

Publications (1)

Publication Number Publication Date
DE3575241D1 true DE3575241D1 (de) 1990-02-08

Family

ID=16124832

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8585306249T Expired - Lifetime DE3575241D1 (de) 1984-09-03 1985-09-03 Halbleiteranordnung und verfahren zum herstellen derselben.

Country Status (5)

Country Link
US (2) US4860084A (de)
EP (1) EP0174185B1 (de)
JP (1) JPS6161441A (de)
KR (1) KR900008359B1 (de)
DE (1) DE3575241D1 (de)

Families Citing this family (36)

* Cited by examiner, † Cited by third party
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JPH04368182A (ja) * 1991-06-17 1992-12-21 Mitsubishi Electric Corp 半導体装置およびその製造方法
US4795436A (en) * 1983-11-14 1989-01-03 Bio-Mimetics, Inc. Bioadhesive composition and method of treatment therewith
JPH0226049A (ja) * 1988-07-14 1990-01-29 Matsushita Electron Corp 半導体装置の製造方法
US5084418A (en) * 1988-12-27 1992-01-28 Texas Instruments Incorporated Method of making an array device with buried interconnects
US5216264A (en) * 1989-06-07 1993-06-01 Sharp Kabushiki Kaisha Silicon carbide MOS type field-effect transistor with at least one of the source and drain regions is formed by the use of a schottky contact
US5585288A (en) * 1990-07-16 1996-12-17 Raytheon Company Digital MMIC/analog MMIC structures and process
JPH0496336A (ja) * 1990-08-11 1992-03-27 Nec Corp Ｍｏｓ型半導体装置
US5506421A (en) * 1992-11-24 1996-04-09 Cree Research, Inc. Power MOSFET in silicon carbide
US5447871A (en) * 1993-03-05 1995-09-05 Goldstein; Edward F. Electrically conductive interconnection through a body of semiconductor material
US6310384B1 (en) * 1993-07-02 2001-10-30 Hitachi, Ltd. Low stress semiconductor devices with thermal oxide isolation
US5395777A (en) * 1994-04-06 1995-03-07 United Microelectronics Corp. Method of producing VDMOS transistors
US5466616A (en) * 1994-04-06 1995-11-14 United Microelectronics Corp. Method of producing an LDMOS transistor having reduced dimensions, reduced leakage, and a reduced propensity to latch-up
US5387534A (en) * 1994-05-05 1995-02-07 Micron Semiconductor, Inc. Method of forming an array of non-volatile sonos memory cells and array of non-violatile sonos memory cells
FR2720191B1 (fr) * 1994-05-18 1996-10-18 Michel Haond Transistor à effet de champ à grille isolée, et procédé de fabrication correspondant.
US5895766A (en) 1995-09-20 1999-04-20 Micron Technology, Inc. Method of forming a field effect transistor
JP3012187B2 (ja) * 1996-02-05 2000-02-21 松下電子工業株式会社 半導体装置の製造方法
US5831312A (en) * 1996-04-09 1998-11-03 United Microelectronics Corporation Electrostic discharge protection device comprising a plurality of trenches
US5721146A (en) * 1996-04-29 1998-02-24 Taiwan Semiconductor Manufacturing Company Ltd Method of forming buried contact architecture within a trench
US5719409A (en) * 1996-06-06 1998-02-17 Cree Research, Inc. Silicon carbide metal-insulator semiconductor field effect transistor
US5736418A (en) * 1996-06-07 1998-04-07 Lsi Logic Corporation Method for fabricating a field effect transistor using microtrenches to control hot electron effects
TW313674B (en) * 1996-09-21 1997-08-21 United Microelectronics Corp High pressure metal oxide semiconductor device and manufacturing method thereof
DE19711165A1 (de) * 1997-03-18 1998-09-24 Smi Syst Microelect Innovat Kontaktanordnung einer planaren, integrierbaren Halbleiteranordnung und Verfahren zur Herstellung dieser Kontaktanordnung
US6297533B1 (en) * 1997-12-04 2001-10-02 The Whitaker Corporation LDMOS structure with via grounded source
US6153934A (en) * 1998-07-30 2000-11-28 International Business Machines Corporation Buried butted contact and method for fabricating
JP3996286B2 (ja) * 1998-11-27 2007-10-24 株式会社ルネサステクノロジ 半導体装置およびその製造方法
JP3566885B2 (ja) * 1999-06-02 2004-09-15 シャープ株式会社 トレンチアイソレーションの形成方法及び半導体装置の製造方法
US7217977B2 (en) * 2004-04-19 2007-05-15 Hrl Laboratories, Llc Covert transformation of transistor properties as a circuit protection method
US6815816B1 (en) * 2000-10-25 2004-11-09 Hrl Laboratories, Llc Implanted hidden interconnections in a semiconductor device for preventing reverse engineering
US7049667B2 (en) 2002-09-27 2006-05-23 Hrl Laboratories, Llc Conductive channel pseudo block process and circuit to inhibit reverse engineering
AU2003293540A1 (en) 2002-12-13 2004-07-09 Raytheon Company Integrated circuit modification using well implants
JP2004363302A (ja) * 2003-06-04 2004-12-24 Toshiba Corp Ｍｏｓｆｅｔ
KR100604527B1 (ko) * 2003-12-31 2006-07-24 동부일렉트로닉스 주식회사 바이폴라 트랜지스터 제조방법
US7242063B1 (en) 2004-06-29 2007-07-10 Hrl Laboratories, Llc Symmetric non-intrusive and covert technique to render a transistor permanently non-operable
KR101101192B1 (ko) * 2004-08-26 2012-01-03 동부일렉트로닉스 주식회사 반도체 소자의 금속 배선 형성 방법
US8168487B2 (en) 2006-09-28 2012-05-01 Hrl Laboratories, Llc Programmable connection and isolation of active regions in an integrated circuit using ambiguous features to confuse a reverse engineer
CN113611736B (zh) * 2020-05-29 2022-11-22 联芯集成电路制造(厦门)有限公司 半导体元件及其制作方法

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* Cited by examiner, † Cited by third party
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US3553536A (en) * 1968-11-19 1971-01-05 Rca Corp Semiconductor rectifiers having controlled storage and recovery characteristics
GB1507299A (en) * 1974-03-26 1978-04-12 Signetics Corp Integrated semiconductor devices
US4151546A (en) * 1976-01-14 1979-04-24 Tokyo Shibaura Electric Co., Ltd. Semiconductor device having electrode-lead layer units of differing thicknesses
JPS5363983A (en) * 1976-11-19 1978-06-07 Toshiba Corp Semiconductor device
JPS5379378A (en) * 1976-12-23 1978-07-13 Matsushita Electric Ind Co Ltd Semoconductor davice and its production
US4116720A (en) * 1977-12-27 1978-09-26 Burroughs Corporation Method of making a V-MOS field effect transistor for a dynamic memory cell having improved capacitance
JPS55107260A (en) * 1979-02-08 1980-08-16 Shindengen Electric Mfg Co Ltd Power transistor
DE2929939A1 (de) * 1979-07-24 1981-02-19 Licentia Gmbh Halbleiteranordnung und verfahren zu ihrer herstellung
JPS5633823A (en) * 1979-08-29 1981-04-04 Toshiba Corp Preparation of semiconductor device
JPS56111217A (en) * 1980-02-07 1981-09-02 Chiyou Lsi Gijutsu Kenkyu Kumiai Preparation of semiconductor device
US4397075A (en) * 1980-07-03 1983-08-09 International Business Machines Corporation FET Memory cell structure and process
EP0067566A3 (de) * 1981-06-13 1985-08-07 Plessey Overseas Limited Integrierter Lichtdetektor oder -generator mit Verstärker
US4458259A (en) * 1981-11-12 1984-07-03 Gte Laboratories Incorporated Etched-source static induction transistor
JPS58137245A (ja) * 1982-02-10 1983-08-15 Hitachi Ltd 大規模半導体メモリ
US4625388A (en) * 1982-04-26 1986-12-02 Acrian, Inc. Method of fabricating mesa MOSFET using overhang mask and resulting structure
US4503598A (en) * 1982-05-20 1985-03-12 Fairchild Camera & Instrument Corporation Method of fabricating power MOSFET structure utilizing self-aligned diffusion and etching techniques
JPS5963719A (ja) * 1982-10-04 1984-04-11 Matsushita Electronics Corp 半導体装置
JPS60126861A (ja) * 1983-12-13 1985-07-06 Fujitsu Ltd 半導体記憶装置
US4633281A (en) * 1984-06-08 1986-12-30 Eaton Corporation Dual stack power JFET with buried field shaping depletion regions
US4622569A (en) * 1984-06-08 1986-11-11 Eaton Corporation Lateral bidirectional power FET with notched multi-channel stacking and with dual gate reference terminal means

Also Published As

Publication number Publication date
KR860002862A (ko) 1986-04-30
KR900008359B1 (ko) 1990-11-17
EP0174185A2 (de) 1986-03-12
US4914050A (en) 1990-04-03
JPS6161441A (ja) 1986-03-29
EP0174185A3 (en) 1988-01-07
US4860084A (en) 1989-08-22
EP0174185B1 (de) 1990-01-03

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Legal Events

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8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)