DE3578266D1 - Verfahren zum herstellen von halbleiteranordnungen und dadurch hergestellte anordnungen. - Google Patents

Verfahren zum herstellen von halbleiteranordnungen und dadurch hergestellte anordnungen.

Info

Publication number
DE3578266D1
DE3578266D1 DE8585905369T DE3578266T DE3578266D1 DE 3578266 D1 DE3578266 D1 DE 3578266D1 DE 8585905369 T DE8585905369 T DE 8585905369T DE 3578266 T DE3578266 T DE 3578266T DE 3578266 D1 DE3578266 D1 DE 3578266D1
Authority
DE
Germany
Prior art keywords
arrangements
same
produced
producing semiconductor
semiconductor arrangements
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8585905369T
Other languages
English (en)
Inventor
Thomas Lynch
Carl Parrillo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
American Telephone and Telegraph Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by American Telephone and Telegraph Co Inc filed Critical American Telephone and Telegraph Co Inc
Application granted granted Critical
Publication of DE3578266D1 publication Critical patent/DE3578266D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2252—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
    • H01L21/2253—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase by ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/763—Polycrystalline semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/938—Lattice strain control or utilization

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Inorganic Chemistry (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
DE8585905369T 1984-11-23 1985-10-18 Verfahren zum herstellen von halbleiteranordnungen und dadurch hergestellte anordnungen. Expired - Lifetime DE3578266D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/674,274 US4656730A (en) 1984-11-23 1984-11-23 Method for fabricating CMOS devices
PCT/US1985/002062 WO1986003339A1 (en) 1984-11-23 1985-10-18 Method for fabricating semiconductor devices and devices formed thereby

Publications (1)

Publication Number Publication Date
DE3578266D1 true DE3578266D1 (de) 1990-07-19

Family

ID=24705990

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8585905369T Expired - Lifetime DE3578266D1 (de) 1984-11-23 1985-10-18 Verfahren zum herstellen von halbleiteranordnungen und dadurch hergestellte anordnungen.

Country Status (7)

Country Link
US (1) US4656730A (de)
EP (1) EP0202252B1 (de)
JP (1) JPH0685412B2 (de)
KR (1) KR940001392B1 (de)
CA (1) CA1232979A (de)
DE (1) DE3578266D1 (de)
WO (1) WO1986003339A1 (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5350941A (en) * 1992-09-23 1994-09-27 Texas Instruments Incorporated Trench isolation structure having a trench formed in a LOCOS structure and a channel stop region on the sidewalls of the trench
US5770504A (en) * 1997-03-17 1998-06-23 International Business Machines Corporation Method for increasing latch-up immunity in CMOS devices
CN1199926A (zh) * 1997-05-21 1998-11-25 日本电气株式会社 一种半导体器件的制造方法
KR100464383B1 (ko) * 1997-05-26 2005-02-28 삼성전자주식회사 트렌치소자분리를이용한반도체장치
US5956583A (en) * 1997-06-30 1999-09-21 Fuller; Robert T. Method for forming complementary wells and self-aligned trench with a single mask
US6492684B2 (en) 1998-01-20 2002-12-10 International Business Machines Corporation Silicon-on-insulator chip having an isolation barrier for reliability
US6133610A (en) 1998-01-20 2000-10-17 International Business Machines Corporation Silicon-on-insulator chip having an isolation barrier for reliability and process of manufacture
JPH11274418A (ja) * 1998-03-25 1999-10-08 Nec Corp 半導体装置
US6747294B1 (en) 2002-09-25 2004-06-08 Polarfab Llc Guard ring structure for reducing crosstalk and latch-up in integrated circuits
DE10345345A1 (de) * 2003-09-19 2005-04-14 Atmel Germany Gmbh Verfahren zur Herstellung von Halbleiterbauelementen in einem Halbleitersubstrat
US7122416B2 (en) * 2003-10-31 2006-10-17 Analog Devices, Inc. Method for forming a filled trench in a semiconductor layer of a semiconductor substrate, and a semiconductor substrate with a semiconductor layer having a filled trench therein
US20050215059A1 (en) * 2004-03-24 2005-09-29 Davis Ian M Process for producing semi-conductor coated substrate
US6956266B1 (en) 2004-09-09 2005-10-18 International Business Machines Corporation Structure and method for latchup suppression utilizing trench and masked sub-collector implantation
US20070152279A1 (en) * 2005-12-30 2007-07-05 Dae Kyeun Kim Sram device
US10249529B2 (en) * 2015-12-15 2019-04-02 International Business Machines Corporation Channel silicon germanium formation method

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55148466A (en) * 1979-05-10 1980-11-19 Nec Corp Cmos semiconductor device and its manufacture
US4493740A (en) * 1981-06-01 1985-01-15 Matsushita Electric Industrial Company, Limited Method for formation of isolation oxide regions in semiconductor substrates
DE3133841A1 (de) * 1981-08-27 1983-03-17 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von hochintegrierten komplementaeren mos-feldeffekttransistorschaltungen
CA1186808A (en) * 1981-11-06 1985-05-07 Sidney I. Soclof Method of fabrication of dielectrically isolated cmos device with an isolated slot
US4435896A (en) * 1981-12-07 1984-03-13 Bell Telephone Laboratories, Incorporated Method for fabricating complementary field effect transistor devices
JPS58165341A (ja) * 1982-03-26 1983-09-30 Toshiba Corp 半導体装置の製造方法
JPS5940563A (ja) * 1982-08-31 1984-03-06 Toshiba Corp 半導体装置の製造方法
US4477310A (en) * 1983-08-12 1984-10-16 Tektronix, Inc. Process for manufacturing MOS integrated circuit with improved method of forming refractory metal silicide areas
EP0158670A1 (de) * 1983-10-11 1985-10-23 AT&T Corp. Integrierte halbleiterschaltungen mit komplementären metalloxid-halbleiteranordnungen
US4536945A (en) * 1983-11-02 1985-08-27 National Semiconductor Corporation Process for producing CMOS structures with Schottky bipolar transistors
US4534824A (en) * 1984-04-16 1985-08-13 Advanced Micro Devices, Inc. Process for forming isolation slots having immunity to surface inversion

Also Published As

Publication number Publication date
KR860700372A (ko) 1986-10-06
JPH0685412B2 (ja) 1994-10-26
EP0202252A1 (de) 1986-11-26
KR940001392B1 (ko) 1994-02-21
EP0202252B1 (de) 1990-06-13
WO1986003339A1 (en) 1986-06-05
US4656730A (en) 1987-04-14
JPS62500969A (ja) 1987-04-16
CA1232979A (en) 1988-02-16

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