DE68916165D1 - Verfahren zum Herstellen von selbstjustierenden Metallhalbleiterkontakten in integrierten MISFET-Strukturen. - Google Patents

Verfahren zum Herstellen von selbstjustierenden Metallhalbleiterkontakten in integrierten MISFET-Strukturen.

Info

Publication number
DE68916165D1
DE68916165D1 DE68916165T DE68916165T DE68916165D1 DE 68916165 D1 DE68916165 D1 DE 68916165D1 DE 68916165 T DE68916165 T DE 68916165T DE 68916165 T DE68916165 T DE 68916165T DE 68916165 D1 DE68916165 D1 DE 68916165D1
Authority
DE
Germany
Prior art keywords
metal semiconductor
producing self
semiconductor contacts
aligning metal
misfet structures
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68916165T
Other languages
English (en)
Other versions
DE68916165T2 (de
Inventor
Pier Luigi Crotti
Nadia Iazzi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
SGS Thomson Microelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics SRL filed Critical SGS Thomson Microelectronics SRL
Publication of DE68916165D1 publication Critical patent/DE68916165D1/de
Application granted granted Critical
Publication of DE68916165T2 publication Critical patent/DE68916165T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising semiconducting material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/911—Differential oxidation and etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/978—Semiconductor device manufacturing: process forming tapered edges on substrate or adjacent layers
DE68916165T 1988-10-20 1989-10-16 Verfahren zum Herstellen von selbstjustierenden Metallhalbleiterkontakten in integrierten MISFET-Strukturen. Expired - Fee Related DE68916165T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT8883674A IT1225624B (it) 1988-10-20 1988-10-20 Procedimento per formare contatti metallo-semiconduttore autoallineatiin dispositivi integrati contenenti strutture misfet

Publications (2)

Publication Number Publication Date
DE68916165D1 true DE68916165D1 (de) 1994-07-21
DE68916165T2 DE68916165T2 (de) 1994-09-22

Family

ID=11323765

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68916165T Expired - Fee Related DE68916165T2 (de) 1988-10-20 1989-10-16 Verfahren zum Herstellen von selbstjustierenden Metallhalbleiterkontakten in integrierten MISFET-Strukturen.

Country Status (5)

Country Link
US (1) US4966867A (de)
EP (1) EP0365492B1 (de)
JP (1) JPH02164027A (de)
DE (1) DE68916165T2 (de)
IT (1) IT1225624B (de)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR920010129B1 (ko) * 1989-11-30 1992-11-16 현대전자산업 주식회사 콘택홀의 패턴형성방법
US5240872A (en) * 1990-05-02 1993-08-31 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing semiconductor device having interconnection layer contacting source/drain regions
JP2934325B2 (ja) * 1990-05-02 1999-08-16 三菱電機株式会社 半導体装置およびその製造方法
US5229325A (en) * 1991-01-31 1993-07-20 Samsung Electronics Co., Ltd. Method for forming metal wirings of semiconductor device
KR930006128B1 (ko) * 1991-01-31 1993-07-07 삼성전자 주식회사 반도체장치의 금속 배선 형성방법
WO1992016966A1 (en) * 1991-03-18 1992-10-01 Boston University A method for the preparation and doping of highly insulating monocrystalline gallium nitride thin films
US5633192A (en) * 1991-03-18 1997-05-27 Boston University Method for epitaxially growing gallium nitride layers
US6953703B2 (en) * 1991-03-18 2005-10-11 The Trustees Of Boston University Method of making a semiconductor device with exposure of sapphire substrate to activated nitrogen
US5231043A (en) * 1991-08-21 1993-07-27 Sgs-Thomson Microelectronics, Inc. Contact alignment for integrated circuits
US5200358A (en) * 1991-11-15 1993-04-06 At&T Bell Laboratories Integrated circuit with planar dielectric layer
US5250464A (en) * 1992-03-11 1993-10-05 Texas Instruments Incorporated Method of making a low capacitance, low resistance sidewall antifuse structure
US5302551A (en) * 1992-05-11 1994-04-12 National Semiconductor Corporation Method for planarizing the surface of an integrated circuit over a metal interconnect layer
KR950011986B1 (ko) * 1992-12-16 1995-10-13 현대전자산업주식회사 고집적 반도체 접속장치 제조방법
US5399533A (en) * 1993-12-01 1995-03-21 Vlsi Technology, Inc. Method improving integrated circuit planarization during etchback
US5597764A (en) * 1996-07-15 1997-01-28 Vanguard International Semiconductor Corporation Method of contact formation and planarization for semiconductor processes
US5994228A (en) * 1997-04-11 1999-11-30 Vanguard International Semiconductor Corporation Method of fabricating contact holes in high density integrated circuits using taper contact and self-aligned etching processes
KR100451500B1 (ko) * 1998-12-28 2004-12-08 주식회사 하이닉스반도체 반도체소자의제조방법
US7777321B2 (en) * 2002-04-22 2010-08-17 Gann Keith D Stacked microelectronic layer and module with three-axis channel T-connects
US6806559B2 (en) * 2002-04-22 2004-10-19 Irvine Sensors Corporation Method and apparatus for connecting vertically stacked integrated circuit chips
US8686002B2 (en) 2005-08-21 2014-04-01 AbbVie Deutschland GmbH & Co. KG Heterocyclic compounds and their use as binding partners for 5-HT5 receptors
DE102007052167B4 (de) * 2007-10-31 2010-04-08 Advanced Micro Devices, Inc., Sunnyvale Halbleiterbauelement und Verfahren zum Einstellen der Höhe einer Gateelektrode in dem Halbleiterbauelement
WO2013032906A1 (en) * 2011-08-29 2013-03-07 Efficient Power Conversion Corporation Parallel connection methods for high performance transistors
US8921136B2 (en) * 2013-01-17 2014-12-30 Taiwan Semiconductor Manufacturing Co., Ltd. Self aligned contact formation

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4057895A (en) * 1976-09-20 1977-11-15 General Electric Company Method of forming sloped members of N-type polycrystalline silicon
US4319954A (en) * 1981-02-27 1982-03-16 Rca Corporation Method of forming polycrystalline silicon lines and vias on a silicon substrate
US4464824A (en) * 1982-08-18 1984-08-14 Ncr Corporation Epitaxial contact fabrication process
FR2537779B1 (fr) * 1982-12-10 1986-03-14 Commissariat Energie Atomique Procede de positionnement d'un trou de contact electrique entre deux lignes d'interconnexion d'un circuit integre
JPS59214239A (ja) * 1983-05-16 1984-12-04 Fujitsu Ltd 半導体装置の製造方法
US4508815A (en) * 1983-11-03 1985-04-02 Mostek Corporation Recessed metallization
US4523372A (en) * 1984-05-07 1985-06-18 Motorola, Inc. Process for fabricating semiconductor device
US4545852A (en) * 1984-06-20 1985-10-08 Hewlett-Packard Company Planarization of dielectric films on integrated circuits
JPS61260639A (ja) * 1985-05-14 1986-11-18 Sony Corp 半導体装置の製造方法
JPS63248145A (ja) * 1987-04-03 1988-10-14 Seiko Instr & Electronics Ltd 半導体装置の製造方法

Also Published As

Publication number Publication date
IT1225624B (it) 1990-11-22
US4966867A (en) 1990-10-30
JPH02164027A (ja) 1990-06-25
EP0365492B1 (de) 1994-06-15
IT8883674A0 (it) 1988-10-20
DE68916165T2 (de) 1994-09-22
EP0365492A3 (de) 1992-07-08
EP0365492A2 (de) 1990-04-25

Similar Documents

Publication Publication Date Title
DE68916165T2 (de) Verfahren zum Herstellen von selbstjustierenden Metallhalbleiterkontakten in integrierten MISFET-Strukturen.
DE69020802T2 (de) Verfahren zum Ausheilen von Halbleitern.
DE3582556D1 (de) Verfahren zum herstellen von kontakten fuer integrierte schaltungen.
DE3575241D1 (de) Halbleiteranordnung und verfahren zum herstellen derselben.
DE3850624D1 (de) Verfahren zum Herstellen von Halbleiterkontakten.
DE3861889D1 (de) Verfahren zum herstellen von loechern in integrierten halbleiterschaltungen.
DE3381509D1 (de) Verfahren zum herstellen von halbleiteranordnungen.
DE3881860D1 (de) Verfahren zum herstellen von profilelementen.
DE68907782D1 (de) Verfahren zum herstellen von grossen halbleiterschaltungen.
DE3770318D1 (de) Anisotrope elektrizitaetsleitende klebstoffzusammensetzung, verfahren zum verbinden von stromkreisen und die so erhaltenen stromkreise.
DE68921046T2 (de) Verfahren und Einrichtung zum Herstellen von Werkstücken in mehreren Schritten.
DE69004842D1 (de) Strahlungemittierende Halbleiteranordnung und Verfahren zum Herstellen einer derartigen Halbleiteranordnung.
DE3684676D1 (de) Verfahren zum herstellen von halbleitersubstraten.
DE3684380D1 (de) Verfahren zum einebnen von halbleiteranordnungen.
DE3883792D1 (de) Verfahren zum Herstellen integrierter Halbleiterschaltungen mit polykristallinen Schichten und Kontakten.
DE3578663D1 (de) Vorrichtung zum herstellen von in mehreren richtungen gebogenen gegenstaenden.
DE3669952D1 (de) Verfahren zum herstellen von mos-transistoren mit metallsilicidelektroden.
DE3873105D1 (de) Verfahren zum stanzen von seifenstuecken.
DE3772490D1 (de) Halbleiteranordnung sowie verfahren zum herstellen und testen derselben.
DE3580192D1 (de) Verfahren zum herstellen eines kontaktes fuer eine halbleiteranordnung.
DE58904461D1 (de) Verfahren zum herstellen von schaumstoffpolstern.
DE68914572D1 (de) Verfahren zum Herstellen von Halbleitervorrichtungen.
DE68923481T2 (de) Verfahren zum Behandeln von Sojabohnen.
DE3578266D1 (de) Verfahren zum herstellen von halbleiteranordnungen und dadurch hergestellte anordnungen.
DE69017949D1 (de) Verfahren zum Herstellen von Halbleiteranordnungen.

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee