DE68907782D1 - Verfahren zum herstellen von grossen halbleiterschaltungen. - Google Patents

Verfahren zum herstellen von grossen halbleiterschaltungen.

Info

Publication number
DE68907782D1
DE68907782D1 DE8989304350T DE68907782T DE68907782D1 DE 68907782 D1 DE68907782 D1 DE 68907782D1 DE 8989304350 T DE8989304350 T DE 8989304350T DE 68907782 T DE68907782 T DE 68907782T DE 68907782 D1 DE68907782 D1 DE 68907782D1
Authority
DE
Germany
Prior art keywords
semiconductor circuits
producing large
large semiconductor
producing
circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8989304350T
Other languages
English (en)
Other versions
DE68907782T2 (de
Inventor
Alexander John Yerman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
General Electric Co
Original Assignee
General Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by General Electric Co filed Critical General Electric Co
Application granted granted Critical
Publication of DE68907782D1 publication Critical patent/DE68907782D1/de
Publication of DE68907782T2 publication Critical patent/DE68907782T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H01L22/22—Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
DE89304350T 1988-05-02 1989-04-28 Verfahren zum Herstellen von grossen Halbleiterschaltungen. Expired - Fee Related DE68907782T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/189,254 US4829014A (en) 1988-05-02 1988-05-02 Screenable power chip mosaics, a method for fabricating large power semiconductor chips

Publications (2)

Publication Number Publication Date
DE68907782D1 true DE68907782D1 (de) 1993-09-02
DE68907782T2 DE68907782T2 (de) 1994-03-17

Family

ID=22696590

Family Applications (1)

Application Number Title Priority Date Filing Date
DE89304350T Expired - Fee Related DE68907782T2 (de) 1988-05-02 1989-04-28 Verfahren zum Herstellen von grossen Halbleiterschaltungen.

Country Status (4)

Country Link
US (1) US4829014A (de)
EP (1) EP0341001B1 (de)
JP (1) JPH0230165A (de)
DE (1) DE68907782T2 (de)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5139963A (en) * 1988-07-02 1992-08-18 Hitachi, Ltd. Method and a system for assisting mending of a semiconductor integrated circuit, and a wiring structure and a wiring method suited for mending a semiconductor integrated circuit
US5016080A (en) * 1988-10-07 1991-05-14 Exar Corporation Programmable die size continuous array
US5108785A (en) * 1989-09-15 1992-04-28 Microlithics Corporation Via formation method for multilayer interconnect board
US5126789A (en) * 1990-07-26 1992-06-30 Konica Corporatoin Image forming apparatus
JP3200150B2 (ja) * 1991-05-20 2001-08-20 キヤノン株式会社 画像形成装置
US5166605A (en) * 1991-08-02 1992-11-24 General Electric Company Controlled impedance test fixture for planar electronic device
US5258650A (en) * 1991-08-26 1993-11-02 Motorola, Inc. Semiconductor device having encapsulation comprising of a thixotropic fluorosiloxane material
US5341310A (en) * 1991-12-17 1994-08-23 International Business Machines Corporation Wiring layout design method and system for integrated circuits
US5256578A (en) * 1991-12-23 1993-10-26 Motorola, Inc. Integral semiconductor wafer map recording
US5352634A (en) * 1992-03-23 1994-10-04 Brody Thomas P Process for fabricating an active matrix circuit
US5347465A (en) * 1992-05-12 1994-09-13 International Business Machines Corporation Method of integrated circuit chips design
US5544038A (en) * 1992-09-21 1996-08-06 General Electric Company Synchronous rectifier package for high-efficiency operation
DE69229673T2 (de) * 1992-10-29 1999-12-02 Stmicroelectronics S.R.L., Agrate Brianza Verfahren zur Bewertung des Gatteroxids nicht-flüchtiger EPROM, EEPROM und flash-EEPROM-Speicher
EP0595775B1 (de) * 1992-10-29 1999-07-28 STMicroelectronics S.r.l. Verfahren zur Bewertung der dielektrischen Schicht nicht-flüchtiger EPROM, EEPROM und flash-EEPROM-Speicher
US5594261A (en) * 1994-04-05 1997-01-14 Harris Corporation Device for isolating parallel sub-elements with reverse conducting diode regions
US5757079A (en) * 1995-12-21 1998-05-26 International Business Machines Corporation Method for repairing defective electrical connections on multi-layer thin film (MLTF) electronic packages and the resulting MLTF structure
US5851911A (en) 1996-03-07 1998-12-22 Micron Technology, Inc. Mask repattern process
JP2990113B2 (ja) * 1997-06-26 1999-12-13 山形日本電気株式会社 半導体基板の不良解析装置及び不良解析方法
TW406319B (en) * 1998-12-22 2000-09-21 Gen Semiconductor Of Taiwan Lt Method of manufacturing inactivated semiconductor devices
US6544880B1 (en) * 1999-06-14 2003-04-08 Micron Technology, Inc. Method of improving copper interconnects of semiconductor devices for bonding
JP2001015526A (ja) * 1999-06-28 2001-01-19 Nec Kansai Ltd 電界効果トランジスタ
US6770911B2 (en) 2001-09-12 2004-08-03 Cree, Inc. Large area silicon carbide devices
US6514779B1 (en) † 2001-10-17 2003-02-04 Cree, Inc. Large area silicon carbide devices and manufacturing methods therefor
US6730527B1 (en) 2001-12-31 2004-05-04 Hyperchip Inc. Chip and defect tolerant method of mounting same to a substrate
US8994173B2 (en) 2013-06-26 2015-03-31 International Business Machines Corporation Solder bump connection and method of making
EP4423808A1 (de) * 2021-10-27 2024-09-04 Atieva, Inc. Nichtplanare anordnung von leistungschips zur wärmeverwaltung

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3835530A (en) * 1967-06-05 1974-09-17 Texas Instruments Inc Method of making semiconductor devices
US3641661A (en) * 1968-06-25 1972-02-15 Texas Instruments Inc Method of fabricating integrated circuit arrays
US3634929A (en) * 1968-11-02 1972-01-18 Tokyo Shibaura Electric Co Method of manufacturing semiconductor integrated circuits
US3702025A (en) * 1969-05-12 1972-11-07 Honeywell Inc Discretionary interconnection process
US3771217A (en) * 1971-04-16 1973-11-13 Texas Instruments Inc Integrated circuit arrays utilizing discretionary wiring and method of fabricating same
US3839781A (en) * 1971-04-21 1974-10-08 Signetics Corp Method for discretionary scribing and breaking semiconductor wafers for yield improvement
US3795972A (en) * 1971-12-09 1974-03-12 Hughes Aircraft Co Integrated circuit interconnections by pad relocation
US3795973A (en) * 1971-12-15 1974-03-12 Hughes Aircraft Co Multi-level large scale integrated circuit array having standard test points
US3795974A (en) * 1971-12-16 1974-03-12 Hughes Aircraft Co Repairable multi-level large scale integrated circuit
US3795975A (en) * 1971-12-17 1974-03-12 Hughes Aircraft Co Multi-level large scale complex integrated circuit having functional interconnected circuit routed to master patterns
US3861023A (en) * 1973-04-30 1975-01-21 Hughes Aircraft Co Fully repairable integrated circuit interconnections
US4479088A (en) * 1981-01-16 1984-10-23 Burroughs Corporation Wafer including test lead connected to ground for testing networks thereon
US4778771A (en) * 1985-02-14 1988-10-18 Nec Corporation Process of forming input/output wiring areas for semiconductor integrated circuit
US4701860A (en) * 1985-03-07 1987-10-20 Harris Corporation Integrated circuit architecture formed of parametric macro-cells

Also Published As

Publication number Publication date
DE68907782T2 (de) 1994-03-17
US4829014A (en) 1989-05-09
JPH0230165A (ja) 1990-01-31
EP0341001A1 (de) 1989-11-08
EP0341001B1 (de) 1993-07-28

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee