KR960043050A - 반도체 소자의 트랜지스터 제조방법 - Google Patents

반도체 소자의 트랜지스터 제조방법 Download PDF

Info

Publication number
KR960043050A
KR960043050A KR1019950011225A KR19950011225A KR960043050A KR 960043050 A KR960043050 A KR 960043050A KR 1019950011225 A KR1019950011225 A KR 1019950011225A KR 19950011225 A KR19950011225 A KR 19950011225A KR 960043050 A KR960043050 A KR 960043050A
Authority
KR
South Korea
Prior art keywords
impurity ions
transistor
semiconductor device
forming
source
Prior art date
Application number
KR1019950011225A
Other languages
English (en)
Other versions
KR0146525B1 (ko
Inventor
박영택
오영균
김의식
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950011225A priority Critical patent/KR0146525B1/ko
Priority to JP8113675A priority patent/JPH08306923A/ja
Priority to TW085105472A priority patent/TW371783B/zh
Priority to CN96110002A priority patent/CN1050691C/zh
Publication of KR960043050A publication Critical patent/KR960043050A/ko
Application granted granted Critical
Publication of KR0146525B1 publication Critical patent/KR0146525B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66492—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a pocket or a lightly doped drain selectively formed at the side of the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures

Abstract

본 발명은 반도체 소자의 트랜지스터 제조방법에 관하여 개시된다.
본 발명은 4가의 불순물이온을 주입하여 실리콘기판의 소오스/드레인영역이 형성될 부위에 비정질실리콘층을 형성시키므로써 채널링 현상을 억제하고, 얕은 접합영역(Shallow junction)을 형성하며, 소자의 신뢰성을 향상시킬 수 있도록 한 반도체 소자의 트랜지스터 제조방법에 관한 것이다.

Description

반도체 소자의 트랜지스터 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2a 내지 2e도는 본 발명에 따른 반도체 소자의 트랜지스터 제조방법을 설명하기 위해 도시한 소자의 단면도.

Claims (4)

  1. 반도체 소자의 트랜지스터 제조방법에 있어서, 실리콘기판상에 게이트전극을 형성하는 단계와, 상기 단계로부터 실리콘기판의 소오스/드레인영역이 형성될 부위를 불순물이온을 주입하여 비정질실리콘층으로 형성하는 단계와, 상기 단계로부터 LDD 이온주입 공정을 실시하는 단계와, 상기 단계로부터 게이트전극의 측벽에 산화막스페이서를 형성하고, 상기 게이트전극 및 산화막스페이서를 포함한 전체구조상에 소오스/드레인 불순물 이온주입공정을 실시하는 단계와, 상기 단계로부터 열처리공정을 실시하여 LDD구조를 갖는 접합부를 형성하는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 트랜지스터 제조방법.
  2. 제1항에 있어서, 상기 비정질실리콘층을 형성하기 위해 주입하는 불순물이온은 4가의 불순물이온인 것을 특징으로 하는 반도체 소자의 트랜지스터 제조방법.
  3. 제1항에 있어서, 상기 LDD 이온은 PMOS 트랜지스터를 제조할 경우에 P-타입의 불순물 이온이고, NMOS 트랜지스터를 제조할 경우에 N-타입의 불순물 이온인 것을 특징으로 하는 반도체 소자의 트랜지스터 제조방법.
  4. 제1항에 있어서, 상기 소오스/드레인 불순물 이온은 PMOS 트랜지스터를 제조할 경우에 P+타입의 불순물 이온이고, NMOS 트랜지스터를 제조할 경우에 N+타입의 불순물 이온인 것을 특징으로 하는 반도체 소자의 트랜지스터 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950011225A 1995-05-09 1995-05-09 반도체 소자의 트랜지스터 제조방법 KR0146525B1 (ko)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1019950011225A KR0146525B1 (ko) 1995-05-09 1995-05-09 반도체 소자의 트랜지스터 제조방법
JP8113675A JPH08306923A (ja) 1995-05-09 1996-05-08 半導体素子のトランジスター製造方法
TW085105472A TW371783B (en) 1995-05-09 1996-05-08 Method for making transistors for semiconductor elements
CN96110002A CN1050691C (zh) 1995-05-09 1996-05-09 制造半导体器件的晶体管的方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950011225A KR0146525B1 (ko) 1995-05-09 1995-05-09 반도체 소자의 트랜지스터 제조방법

Publications (2)

Publication Number Publication Date
KR960043050A true KR960043050A (ko) 1996-12-21
KR0146525B1 KR0146525B1 (ko) 1998-11-02

Family

ID=19413930

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950011225A KR0146525B1 (ko) 1995-05-09 1995-05-09 반도체 소자의 트랜지스터 제조방법

Country Status (4)

Country Link
JP (1) JPH08306923A (ko)
KR (1) KR0146525B1 (ko)
CN (1) CN1050691C (ko)
TW (1) TW371783B (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100429873B1 (ko) * 2001-07-19 2004-05-04 삼성전자주식회사 모스 트랜지스터 및 그 형성방법

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6333217B1 (en) 1999-05-14 2001-12-25 Matsushita Electric Industrial Co., Ltd. Method of forming MOSFET with channel, extension and pocket implants
EP1524684B1 (en) * 2003-10-17 2010-01-13 Imec Method for providing a semiconductor substrate with a layer structure of activated dopants
CN102148245B (zh) * 2010-02-10 2016-09-28 上海华虹宏力半导体制造有限公司 本征mos晶体管及其形成方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0795535B2 (ja) * 1986-12-19 1995-10-11 日本電信電話株式会社 半導体装置の製造方法
JPH04158529A (ja) * 1990-10-23 1992-06-01 Oki Electric Ind Co Ltd 半導体素子の製造方法
JP2683979B2 (ja) * 1991-04-22 1997-12-03 三菱電機株式会社 半導体装置およびその製造方法
JPH06302824A (ja) * 1993-02-16 1994-10-28 Sanyo Electric Co Ltd 薄膜トランジスタおよびその製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100429873B1 (ko) * 2001-07-19 2004-05-04 삼성전자주식회사 모스 트랜지스터 및 그 형성방법

Also Published As

Publication number Publication date
KR0146525B1 (ko) 1998-11-02
CN1050691C (zh) 2000-03-22
CN1146627A (zh) 1997-04-02
JPH08306923A (ja) 1996-11-22
TW371783B (en) 1999-10-11

Similar Documents

Publication Publication Date Title
EP0978141A1 (en) Method of making nmos and pmos devices with reduced masking steps
KR950034842A (ko) 저 접합 누설 금속산화물 반도체 전계효과 트랜지스터
US6051459A (en) Method of making N-channel and P-channel IGFETs using selective doping and activation for the N-channel gate
US6051471A (en) Method for making asymmetrical N-channel and symmetrical P-channel devices
KR960043050A (ko) 반도체 소자의 트랜지스터 제조방법
JPH0346238A (ja) 半導体装置の製造方法
JPS62265765A (ja) 半導体装置の製造方法
KR970018259A (ko) 반도체 소자의 트랜지스터 제조방법
JPH0897422A (ja) Ｍｏｓ型半導体装置の製造方法及びｍｏｓ型半導体装置
JPH04196170A (ja) 半導体装置およびその製造方法
KR960035923A (ko) 반도체 소자의 제조방법
KR960039273A (ko) 반도체 소자의 제조방법
JPS61263258A (ja) Ｃｍｏｓ型半導体装置の製造方法
KR940006277A (ko) 반도체 장치
KR960035911A (ko) 반도체 소자의 제조방법
KR970008340B1 (ko) 반도체장치의 제조방법
KR960002895A (ko) 반도체 소자의 트랜지스터 제조방법
KR930005272A (ko) Ldd형 mos 트랜지스터 및 그의 제조방법
JPH06204419A (ja) 半導体装置の製造方法
KR970024156A (ko) 셀영역과 주변회로 영역 사이의 단차 개선방법
KR960009216A (ko) 반도체 소자 및 그 제조방법
KR950015660A (ko) 반도체 장치의 LDD(Lightly Doped Drain) 트랜지스터 제조방법
JP2000232221A (ja) 半導体装置及びその製造方法
JPH05283424A (ja) 半導体装置の製造方法
KR970053040A (ko) Cmos 트랜지스터의 제조 방법

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20080425

Year of fee payment: 11

LAPS Lapse due to unpaid annual fee