KR940006277A - 반도체 장치 - Google Patents

반도체 장치 Download PDF

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Publication number
KR940006277A
KR940006277A KR1019930008887A KR930008887A KR940006277A KR 940006277 A KR940006277 A KR 940006277A KR 1019930008887 A KR1019930008887 A KR 1019930008887A KR 930008887 A KR930008887 A KR 930008887A KR 940006277 A KR940006277 A KR 940006277A
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South Korea
Prior art keywords
mos transistor
channel
semiconductor substrate
pair
doped layer
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KR1019930008887A
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English (en)
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고주 노나카
시게유키 츠노다
겐지 기타무라
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하라 레이노스케
세이코덴시고교 가부시키가이샤
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Publication of KR940006277A publication Critical patent/KR940006277A/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0925—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising an N-well only in the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

본 발명의 반도체 장치는 각각 폴리실리폰 게이트(4)를 가지는 P채널형 MOS 트랜지스터와 N채널형 MOS 트랜지스터로 구성되는 CMOS 트랜지스터 쌍을 가진다. 상기 MOS 트랜지스터는 게이트 전극 바로 아래에 있는 채널 영역의 표면 부근에 국부적으로 형성된 채널 도핑층(5)를 가진다. 이러한 채널 도핑층(5)는 누설전류를 억제하는데 효과적인 매우 얕은 P-N접합 깊이(xj)를 가진다. 이렇게 함으로써, 상기 채널 영역 표면에서의 상당한 양의 불순물 농도를 감소시켜 MOS 트랜지스터의 부임계 특싱을 향상시킬 수 있고 누설전류를 억제하먼서 저 전압과 고속 동작을 가능하게 한다.

Description

반도체 장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명에 따른 CMOS 트랜지스터의 구조를 도식적으로 나타내는 부분 단면도,
제10도는 본 발명에 따른 COMS 트랜지스터 쌍의 제조방법을 단계적으로 나타내는 도면,
제12도는 본 발명의 따른 CMOS 트랜지스터 쌍의 완성된 상태를 나타내는 도면.

Claims (11)

  1. 폴리실리콘 게이트를 가지는 P채널형 MOS 트랜지스터 쌍으로 구성되는 반도체 장치에 있어서, 상기 MOS 트랜지스터는 반도체 기판에서 서로 이격되게 형성된 한 쌍의 소스 및 드레인 영역과, 상기 한쌍의 소스 및 드레인 영역들 사이에서 반도체 기판의 표면 부근에 국부적으로 형성된 채널 도핑층과 상기 채널 도핑 층위의 반도체 기판 상에 형성된 게이트 절연막을 포함하는 것을 특징으로 하는 반도체 장치.
  2. 제1항에 있어서, 상기 채널 도핑 층은 0.2㎛의 P-N 접합 깊이를 가지는 것을 특징으로 하는 반도테 장치.
  3. 제1항에 있어서, 상기 MOS 트랜지스터의 게이트 절연막은 200Å 미만의 두께를 가지는 것을 특징으로 하는 반도체 장치.
  4. 제1항에 있어서, 1.2 내지 3.6V 범위의 동작전압에서 구동되는 RAM 또는 ROM을 구성하는 다수의 MOS트랜지스터 쌍들을 포함하는 것을 특징으로 하는 반도체 장치.
  5. 제1항에 있어서, 1. 2 내지 3.6V 범위의 동작전압에서 구동되는 CPU를 구성하는 다수의 CMOS 트랜지스터 쌍들을 포함하는 것을 특징으로 하는 반도체 장치.
  6. 각각 폴리실리콘 게이트를 가지는 P 채널형 MOS 트랜지스터 및 N 채널형 MOS트랜지스터으로 구성되는 CMOS 트랜지스터 쌍을 포함하는 단일 칩 형태의 마이프로 컴퓨터에 있어서, 상기 MOS 트랜지스터는 반도체 기판에서 서로 이격되게 형성된 한쌍의 소스 및 드레인 영역과, 상기 한쌍의 소스 및 드레인 영역들 사이에서 반도체 기판의 표면 부근에 국부적으로 형성된 채널 도핑층과, 상기 채널 도핑 층 위의 반도체 기판 상에 형성된 게이트 절연막을 포함하는 것을 특징으로 하는 반도체 장치.
  7. 제6항에 있어서, 상기 CMOS 트랜지스터 쌍은 1.2 내지 3.6V 범위의 동작전압을 가지는 것을 특징으로 하는 마이크로컴퓨터.
  8. N+폴리실리콘 게이트를 가지는 P 채널형 MOS 트랜지스터 및 또다른 N+폴리실리콘 게이트를 가지는 N 채널형 MOS 트랜지스터로 구성되는 CMOS 트랜지스터 쌍을 포함하는 반도체 장치의 제조방법에 있어서, 반도체 기판에 소스 영역과 드레인 영역을 분리하여 형성하는 단계 및 30 KeV 하의 가속 에너지로 BF+를 상기 소스 영역과 드레인 영역 사이의 반도체 기판부분에 이온 주입하여 반도체 기판의 표면 부근에 국부적으로 P형 채널 도핑층을 형성하는 단계를 포함하는 것을 특징으로 하는 방법.
  9. 제8항에 있어서, 상기 채널 도핑층을 형성하는 단계전에, 채널 도핑층이 헝성된 기판의 표면 상에 200Å 미만의 두께로 게이트 절연막을 형성하는 단계를 포함하는 것을 특징으로 하는 방법.
  10. 제8항에 있어서, 상기 채널 도핑층을 형성하는 단계 후에, 반도체 기판의 P형 영역으로 인 이온을 이온 주입하여 N 채널형 MOS 트탠지스터의 소스/드레인 영역 쌍을 형성하는 단계를 포함하는 것을 특징으로 하는 방법.
  11. 제8항에 있어서, 인 이온을 1×1012내지 3×1012/㎠ 분량으로 반도체 기판에 기온 주입하여 상기 P채널형 MOS 트랜지스터의 N형 영역을 한정하는 N형 우물을 형성하는 단계를 포함하는 것을 특징으로 하는 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019930008887A 1992-05-22 1993-05-22 반도체 장치 KR940006277A (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP13107692 1992-05-22
JP92-131076 1992-05-22
JP93-57555 1993-03-17
JP5755593 1993-03-17

Publications (1)

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KR940006277A true KR940006277A (ko) 1994-03-23

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US (1) US5489794A (ko)
EP (1) EP0571224A1 (ko)
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3400891B2 (ja) * 1995-05-29 2003-04-28 三菱電機株式会社 半導体記憶装置およびその製造方法
US6204517B1 (en) * 1998-04-09 2001-03-20 Texas Instruments-Acer Incorporated Single electron transistor memory array
US6881634B2 (en) * 2002-08-30 2005-04-19 Cypress Semiconductor Corporation Buried-channel transistor with reduced leakage current

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Publication number Priority date Publication date Assignee Title
NL8303441A (nl) * 1983-10-07 1985-05-01 Philips Nv Geintegreerde schakeling met komplementaire veldeffekttransistors.

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EP0571224A1 (en) 1993-11-24
US5489794A (en) 1996-02-06

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