EP0571224A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
EP0571224A1
EP0571224A1 EP93303957A EP93303957A EP0571224A1 EP 0571224 A1 EP0571224 A1 EP 0571224A1 EP 93303957 A EP93303957 A EP 93303957A EP 93303957 A EP93303957 A EP 93303957A EP 0571224 A1 EP0571224 A1 EP 0571224A1
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EP
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Prior art keywords
channel
mos transistor
type
channel mos
doped layer
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EP93303957A
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German (de)
English (en)
French (fr)
Inventor
Koju c/o Seiko Instruments Inc. Nonaka
Shigeyuki c/o Seiko Instruments Inc. Tsunoda
Kenji c/o Seiko Instruments Inc. Kitamura
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Seiko Instruments Inc
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Seiko Instruments Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0925—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising an N-well only in the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials

Definitions

  • the present invention relates to a semiconductor device and a method of producing the same.
  • Particular embodiments of the present invention relate to a semiconductor device and production method of the same having a CMOS transistor pair composed of P channel MOS transistor having a polysilicon gate and N channel MOS transistor having a polysilicon gate. More specifically, embodiments of the present invention relate to a semiconductor device and production method of the same, operable at a low voltage of about 1.5 V and at a high speed.
  • an N type polysilicon gate heavily doped with phosphorus and a P type polysilicon gate doped heavily with boron, are formed on a silicon substrate or on an ion implanted well layer in a silicon substrate.
  • this gate electrode material is utilised as a gate electrode of a MOS transistor, such as an N type polysilicon gate for an N channel MOS transistor, a work function difference is relatively great between the semiconductor substrate and the polysilicon so that a threshold voltage is lowered. Therefore, normally a channel region is ion-implanted with an impurity such as boron having the same electroconductivity type as that of the substrate so as to regulatively raise the threshold voltage.
  • the gate electrode material is utilised as a different type of gate electrode material from a channel type of a MOS transistor, such an N type polysilicon gate for a P channel MOS transistor, a work function difference is relatively small between the semiconductor substrate and the polysilicon gate electrode, so that the threshold voltage is negatively shifted. Therefore, in order to regulate the absolute value of the threshold voltage to a smaller level, an impurity, such as boron, having an opposite electroconductivity type to the semiconductor substrate, is ion-implanted into the channel region of that substrate. Consequently, a P-N junction is formed.
  • the former case is called a device of the surface channel type, and the latter case is called a device of the buried channel type.
  • the P channel MOS transistor and the N channel MOS transistor are coupled to one another to constitute a complementary pair, ie. a CMOS transistor pair.
  • CMOS technology As the amount of boron doped into the channel region is increased, a threshold voltage of an N channel MOS transistor of the surface channel type is raised and a threshold voltage of a P channel MOS transistor of the buried channel type is lowered.
  • the semiconductor integrated circuit device containing a CMOS transistor pair as a basic element constitutes a CMOS IC which is suitable, for example, as a one chip microcomputer.
  • CMOS IC which is suitable, for example, as a one chip microcomputer.
  • Such a one chip microcomputer may be assembled into various portable and desk-top instruments, as a controller. These portable and desk-top instruments normally utilise a battery as a power source. In view of compact design and power saving, the instruments are adopted to operate at a power source voltage of about 1.5 V supplied by a single dry battery. Consequently, it is one of the important objectives to lower an operation voltage of the CMOS IC.
  • MOS transistors can be operated with currents flowing in an inverted channel region between a source region and a drain region by applying a voltage over the threshold voltage to a gate electrode and a constant voltage between the source region and the drain region. Although, the threshold voltage is lowered, the channel region is inverted weakly, so that the currents flow between the source region and the drain region (leakage current). This mechanism will be explained by using Figure 8 for better understanding.
  • the horizontal axis represents gate voltage V G and the vertical axis represents drain current I D in a logarithmic scale.
  • an inversion value V G /log(I D ) of an inclination of curve is named as a subthreshold coefficient S, which is an important value for determining a switching characteristic of the MOS transistor.
  • a depletion layer capacity is formed just below the gate electrode in the surface of the MOS transistor.
  • the subthreshold coefficient S becomes greater: on the other hand, as the depletion layer capacity becomes smaller, the subthreshold coefficient S becomes smaller. Further, the depletion layer capacity becomes large when the concentration of the substrate surface just below the gate electrode is high, while the depletion layer capacity becomes small when the concentration is low. Therefore, as the concentration of the substrate surface just below the gate electrode is reduced, the depletion layer capacity becomes smaller, and the subthreshold coefficient S can be decreased. As a result, the MOS transistor can be operated with a narrow range of voltage, and thereby it is possible to perform a switching operation at high speed with a small power consumption.
  • the P channel MOS transistor which is a buried channel type device
  • comparatively large amount of boron is ion-implanted in order to keep the threshold voltage below 0.5 V, so that the concentration of the substrate surface is high.
  • a P-N junction is formed in a channel region of an N type well of the P channel MOS transistor having the N type polysilicon gate electrode and the buried channel.
  • a level of the minimum potential does not exist at a boundary between a silicon substrate and a gate oxide film, but exists in an internal portion of the substrate to form a buried channel.
  • the level of the minimum potential shifts into the internal portion of the substrate to enhance a degree of the buried channel.
  • the buried channel type device is advantageous, as compared to the surface channel type device, in that the mobility is much greater.
  • the buried channel type device suffers from a most serious drawback that a short channel effect is easily induced. This short channel effect particularly causes secondary drawbacks such as increase in any leak current, degradation of a subthreshold characteristic and reduction in a punch-through breakdown voltage.
  • the P-N junction depth In order to suppress such short channel effects in the P channel MOS transistor of the buried channel type, the P-N junction depth must be set as shallow as possible, so that the P channel MOS transistor becomes closer to the surface channel type device. However, it is practically difficult to establish a quite shallow P-N junction depth.
  • boron element is ion-implanted to carry out the channel doping.
  • a shallow diffusion layer cannot be formed because of the relatively great diffusion coefficient of boron.
  • boron is ion-implanted by a great amount so as to suppress the threshold voltage at about 0.5 V, thereby rending the P-N junction depth deep.
  • N type/P type bipolar gate structure is adopted instead of the N type unipolar gate structure.
  • a P type polysilicon gate material is used as a gate electrode of the P channel MOS transistor.
  • the N type/P type bipolar gate structure disadvantageously complicates not only the fabrication process but also IC design.
  • a junction structure of lead lines is complicated to obtain an ohomic contact to opposite polarities of the gate electrodes, thereby disadvantageously enlarging the IC chip size.
  • the N type unipolar gate structure has the advantages of simple process and design and small chip size.
  • an object of the present invention is to achieve low voltage and high speed operation while suppressing a leak current and lowering a sub-threshold coefficient in the MOS transistor of the CMOS transistor pair.
  • the present invention thus provides a semiconductor device including a CMOS transistor pair composed of a P channel MOS transistor having a polysilicon gate, wherein the MOS transistor comprises a pair of source and drain regions formed in spaced relation from each other in a semiconductor substrate, a channel doped layer formed locally in a vicinity of a surface of the semiconductor substrate between the pair of source and drain regions, and a gate insulating film formed on the semiconductor substrate over the channel doped layer.
  • the present invention also provides a method of producing a semiconductor device containing a CMOS transistor pair composed of a P channel MOS transistor having an N+ polysilicon gate and an N channel MOS transistor having another N+ polysilicon gate, the method comprising forming separately source and drain regions in a semiconductor substrate, and a channel doping by ion-implanting BF2+ with an acceleration energy under 30 keV into the semiconductor substrate between the source and drain regions to form a P type channel doped layer localised in a vicinity of a surface of the semiconductor substrate.
  • a gate insulating film of the MOS transistor is formed prior to the channel doping.
  • phosphorus is ion-implanted into a P type region of the N channel MOS transistor to form source/drain regions thereof without effecting drive-in thermal process of N+ source/drain.
  • phosphorus may be ion-implanted into a semiconductor substrate of a P ⁇ type at a dose of 1 x 1012 to 3 x 1012/cm2, more preferably 2 x 1012/cm2, to form an N type well which defines the N type region of P channel MOS transistor.
  • the gate insulating film of the MOS transistor may be formed at a thickness of about 10nm to 20nm (100 ⁇ to 200 ⁇ ), more preferably about 15 nm (150 ⁇ ).
  • BF2+ is ion-implanted to form the P type channel doped layer confined in the vicinity of the channel surface. Since the boron compound BF2+ has a molecular weight greater than that of the boron element B, its range is smaller in the ion-implantation on an acceleration energy under 30 keV. Consequently, the P type impurity layer can be formed quite shallow and a distribution of the impurity in depth direction can be suppressed, thereby the impurity concentration just below the gate electrode in a surface of the substrate can be reduced.
  • the gate insulating film of the MOS transistor is formed by a thermal oxidation process. Thereafter, the P type channel layer is formed so that it is not subjected to hysteresis of the thermal oxidation, thereby suppressing thermal impurity diffusion to maintain the quite shallow P-N junction depth. Further, as there occurs a decrease in concentration of the impurity included in the substrate surface which is necessary for adjusting the threshold voltage when the impurity is thermally diffused, it is necessary to increase the channel doping amount of the impurity in advance in order to prevent the decrease in concentration. However, in the present invention it is unnecessary to take such measures.
  • phosphorus is ion-implanted in place of the conventionally used arsenic into the P type region of the N channel MOS transistor to form the source/drain regions.
  • Phosphorus has a diffusion coefficient greater than arsenic: hence a sufficient impurity region can be obtained without thermal process or annealing.
  • the channel doped layer subsequently formed can be free from thermal hysteresis which would cause ill affect.
  • the dose of phosphorus is reduced by half as compared to the prior art. Therefore, a threshold voltage the same as the conventional threshold voltage, can be achieved with less channel doped impurity.
  • the impurity concentration of the substrate surface just below the gate electrode becomes lower, and it is possible to diminish the subthreshold coefficient of the P channel MOS transistor sufficiently. Furthermore, the leak current can be suppressed even if the threshold voltage is low.
  • the gate insulating film of each MOS transistor is made thin in the order of 15nm (150 ⁇ ) thickness. Accordingly device micronisation is realised to meet "0.8 ⁇ m rule", and concurrently higher operation speed and low leakage current can be achieved.
  • FIG. 1 is a schematic partial section showing a structure of the inventive CMOS transistor pair.
  • This transistor is formed of a P ⁇ type Si substrate 1.
  • An N type well 2 is formed in a surface portion of the substrate 1.
  • This N type well 2 is optimised to a low impurity density such that, for example, phosphorus of the N type impurity is doped at a dose of 2 x 1012/cm2 by ion-implantation.
  • a gate oxide film (Gate Ox) 3 is formed on the surface of the substrate 1.
  • This gate oxide film 3 is made optionally thin such that, for example, its thickness is set 15nm (150 ⁇ ).
  • An N type polysilicon gate electrode (N type poly Si Gate) 4 is patterned over the gate oxide film 3.
  • a channel doped layer 5 is formed under the gate oxide film 3 just below the gate electrode 4.
  • This channel doped layer 5 has a quite shallow P-N junction depth (xj) in the order of, for example, 0.15 ⁇ m.
  • P channel MOS transistor is formed in an N well 2 and N channel MOS transistor is formed in a P type silicon substrate 1. Those two type MOS transistors are separated by a field oxide layer.
  • An impurity is densely doped into opposite sides of the channel doped layer 5 to form a pair of P type/N type source region S and P type/N type drain region D.
  • a P channel MOS transistor of a CMOS pair is formed in a P ⁇ type Si substrate 101.
  • An N type well 102 is provided in the surface of the substrate 101.
  • This N type well 102 contains a high density of an n type impurity as compared to the N type well 2 shown in Figure 1.
  • the impurity phosphorus is doped at a dose of about 4 x 1012/cm2 by ion-implantation.
  • a gate oxide film 103 has a thickness of, for example, about 25nm (250 ⁇ ) which is thicker than the gate oxide film 3 shown in Figure 1.
  • An N type polysilicon gate electrode 104 is formed on the gate oxide film in a manner similar to the gate electrode 4 shown in Figure 1.
  • the P channel transistor and N channel transistor are separated by the field oxide film 106.
  • a channel doped layer 105 formed just under the gate electrode 104 has a relatively deep P-N junction depth xj in the order of, for example, about 0.34 ⁇ m.
  • Figure 3 is a graph showing a density depth profile of the impurity boron in the N type well.
  • the vertical axis denotes depth and the horizontal axis denotes an impurity density in the graph.
  • the conditions of acceleration energy in ion-implantation process are the same in both the present and conventional cases.
  • the dashed lines and solid lines show the cases of boron (P type) impurity and phosphorous (N type) impurity respectively.
  • the curves 31 and 32 are the cases of the inventive sample, and curves 33 and 34 are the cases of the conventional sample.
  • the density profile curve falls sharply in the vicinity of the N type well surface, such that the P type channel doped layer is localised and confined in the vicinity of the surface. Consequently, the P-N junction depth xj1 is quite shallow.
  • the profile curve gradually falls so that the P type channel dope layer has a broad distribution within the N type well. Consequently, the P-N junction depth xj2 is positioned in a relatively deep level. Accordingly, an impurity density of the present invention is thinner than the normal one.
  • Figure 4 is a graph showing the relationship between leak current of the P channel MOS transistor (Pch Tr) and a P-N junction depth xj.
  • the vertical axis denotes the leak current (A) in a logarithmic scale
  • the horizontal axis denotes the junction depth xj in ⁇ m.
  • the Figure 1 inventive construction has the junction depth xj1 of about 0.15 ⁇ m
  • the Figure 2 conventional construction has the junction depth xj2 of about 0.34 ⁇ m.
  • the leak current of an inventive sample 41 is reduced to the order of 10 ⁇ 10 A, while the leak current of a conventional sample 42 is in the order of 10 ⁇ 8 A.
  • a threshold voltage V TP of the P channel MOS transistor is set to 0.4 V.
  • the short channel effects can be effectively suppressed thereby significantly reducing the leak current. It is preferred to limit the junction depth xj within 0.2 ⁇ m in order to suppress the leak current by one order as compared to the prior art.
  • the second feature of the inventive device is such that the thickness of the gate oxide film is optimised relatively thin as compared to the prior art. While the prior art device has a gate oxide film thickness of about 25 nm (250 ⁇ ), the inventive device has a thinner gate oxide film thickness of about 15 nm (150 ⁇ ). The gate oxide film thickness of 15 nm (150 ⁇ ) can meet the "0.8 ⁇ rule" to facilitate device micronisation. Reduction in the gate oxide film thickness can improve the transistor operating characteristics.
  • Figure 5 is a graph showing the capacity characteristics of the MOS transistor structure which is formed by doping P type impurity in the channel of the P ⁇ type Si substrate. Conditions of the above doping is to use an acceleration energy of 25 keV.
  • the normal axis represents a capacity (C/Cox) and the horizontal axis represents a voltage (BIAS).
  • a region where the BIAS is negative shows an oxide film capacity and a region where the BIAS is positive indicates a substrate capacity.
  • the substrate capacity of the present invention sample 43 is smaller than that of the conventional sample 44, for a width of the inventive depletion layer on the substrate surface that is larger than that of the conventional sample. As the impurity concentration is lower, the width of the depletion layer becomes larger. In other words, the impurity concentration on the substrate surface is lower in the present invention compared with the conventional type.
  • Figure 6 is a graph showing the relationship between a threshold voltage V TH of the MOS transistor and a subthreshold coefficient S.
  • the vertical axis represents the subthreshold coefficient S (mV/decade) and the horizontal axis represents the threshold voltage V TH (V).
  • the dashed lines and the solid lines show the cases of P channel MOS transistor and N channel MOS transistor respectively.
  • the curves 61 and 62 are the cases of the inventive sample and the conventional sample respectively.
  • the depth of a buried channel is quite shallow, 0.15 ⁇ m from a semiconductor surface of the channel region, and a total impurity concentration just below the gate electrode is low: while in the prior art shown in Figure 2, the depth is deeper, 0.34 ⁇ m, and the total impurity concentration just below the gate electrode is high.
  • the threshold voltage can be adjusted with a small amount of channel doping in the P channel MOS transistor. For this reason also, the total impurity concentration just below the gate electrode is low.
  • the gate oxide film is thinner, approximately 15nm (150 ⁇ ) while it is conventionally around 25nm (250 ⁇ ).
  • the subthreshold coefficient S of the present invention is 77.2mV/decade and decreasing, while that of the prior art is 97.2mV/decade.
  • the threshold voltage V TH of the N channel MOS transistor is also 0.5 V, for example, the subthreshold coefficient S of the present invention is 78.2mV/decade and decreasing, while that of the prior art is 84.7mV/decade.
  • this graph indicates that when the threshold voltage V TH becomes lower, the subthreshold coefficient S becomes larger in the case of the P channel MOS transistor and becomes smaller in the case of the N channel MOS transistor. This relationship will be further explained in detail below.
  • the channel-doping amount is changed to 1 x 1012/cm2 in order to get the threshold voltage V TH of 0.6 V, and to 2 x 1012/cm2 in order to get the threshold voltage of 0.4 V, for example, and then the threshold voltage is adjusted. Further, as the concentration of the N well is low, the channel doping amount is changed to 1.5 x 1012/cm2 in order to get 0.4 V. As to the N channel MOS transistor, for example, the channel-doping amount is changed to 2 x 1012/cm2 for getting the threshold voltage of 0.6V, and to 5 x 1011/cm2 for 0.4 V.
  • the vertical axis represents the threshold voltage V TH of the MOS transistor and the horizontal axis represents the channel-doping amount.
  • the dashed line and the solid line show the cases of P channel MOS transistor and N channel MOS transistor respectively.
  • the curves 71 and 72 are the cases of the present invention (N well 2 x 1012/cm2) and the convention type (N well 4 x 1012/cm2) respectively.
  • the threshold voltage of the P channel MOS transistor is low and that of the N channel MOS transistor is high, the doping amount is large and the concentration of the substrate surface just below the gate electrode is high, so that the subthreshold coefficient S is large.
  • the threshold voltage of the P channel MOS transistor is high and that of the N channel MOS transistor is low, the doping amount is small and the concentration is low, as a result the subthreshold coefficient S is small.
  • the horizontal axis represents a gate voltage V G and the vertical axis represents a drain current I D in logarithmic memory.
  • An inclination showing the characteristics of the prior art is small which means that the subthreshold coefficient S is large.
  • that of the present invention is large which means that the subthreshold coefficient S is small.
  • the drain current I D of the present invention becomes smaller than that of the prior art, for instance, when the gate voltage V G is 0 V. The above means that a leak current is smaller in the present invention than in the prior art.
  • the vertical axis represents the leak current (A) in logarithmic memory and the horizontal axis represents the threshold voltage V TH (V).
  • the dashed lines and solid lines show the cases of P channel MOS transistor and N channel MOS transistor respectively.
  • the curves 91 and 92 are the present inventive sample and the conventional sample respectively.
  • the leak current of the P channel MOS transistor is 9 x 10 ⁇ 11 A and that of the N channel MOS transistor is 7.5 x 10 ⁇ 12 A in the prior art.
  • that of the P channel MOS transistor is 1.9 x 10 ⁇ 12 A and that of the N channel MOS transistor is 1.2 x 10 ⁇ 12 A in the present invention and the two leak currents of the present invention are smaller.
  • the CMOS IC having the inventive channel structure can respond to a fast drive frequency up to one MHz.
  • the CMOS IC having such a significant characteristic is suitable for one chip CPU, memory and microcomputer, those of which are mounted for control of various portable and desk-top instruments. These instruments may include portable tape recorder, portable CD, pager and portable radio receiver.
  • Step A an N type well 13 is formed in a surface of a P type Si substrate 12.
  • an oxide film 11 is formed on the substrate surface, and is patterned in a desired shape as a mask.
  • an N type impurity of phosphorus is ion-implanted at the dose of 2 x 1012/cm2. As described before, this dose is reduced by half as compared to the prior art.
  • thermal treatment is carried out at 1150 °C for 6 hours to effect diffusion and activation of the doped impurity phosphorus to form the N type well 13 as shown in the figure.
  • a P channel MOS transistor is to be formed in the n type well 13, while an N channel MOS transistor is to be formed in an adjacent region.
  • Step B is undertaken to carry out field doping.
  • a silicon nitride film 14 is formed and patterned to selectively cover an active region in which is to be formed a transistor element.
  • a photoresist 15 is superposed on the silicon nitride film 14 over the N type well 13.
  • an impurity of boron is ion implanted by an acceleration energy of 30 keV at a dose of 2 x 1013/cm2 to effect field doping.
  • a field dope region is formed to surround each device region.
  • Step C a so-called LOCOS process is carried out to form a field oxide film 16 which surrounds the device region. Thereafter, sacrificial oxidation and associated removal treatment are carried out to eliminate remaining contaminants to thereby clean the surface of the substrate 12.
  • Step D a thermal oxidation process is applied to the surface of the substrate 12 to form a gate oxide film 17 which covers the device region.
  • This thermal oxidation process is conducted in an H2O gas at a substrate temperature of 860 °C to grow an oxide film at a thickness of about 15nm (150 ⁇ ).
  • the conventional gate oxide film has a thickness of about 25nm (250 ⁇ ).
  • Step E is undertaken to effect channel doping.
  • This channel doping is directed to adjustment of the threshold voltage of the CMOS transistor pair by doping a P type impurity.
  • the boron compound BF2 is utilised as an ion species of the p type impurity instead of the boron element B for the ion-implantation.
  • the acceleration energy is set to, for example, 25 keV.
  • the boron compound BF2 has a greater molecular weight than the boron element B so that it's range is relatively short in the ion-implantation, thereby forming a channel doped layer in a quite shallow level as shown in the figure.
  • the channel doping is carried out through the gate oxide film 17. Consequently, the channel doped layer is free of hysteresis of the thermal process which has been conducted in forming of the gate oxide film 17, thereby maintaining a P-N junction depth as it is.
  • the gate oxide film is formed after the channel doping so that the impurity boron is disadvantageously subjected to diffusion in the channel doped layer.
  • Step F an N+ polysilicon gate electrode 18 is formed and patterned over the gate oxide film 17 according to the regular method including CVD.
  • Step G source/drain regions are formed to provide an N channel MOS transistor.
  • a photoresist 15 is provided to mask the N type well 13 which is assigned to a P channel MOS transistor.
  • an N type impurity of phosphorus is ion-implanted by self-alignment utilising the gate electrode 18 as a mask to form the source/drain regions.
  • This ion-implantation is conditioned such that the acceleration energy is set to 40 keV, and the dose is set to 3.5 x 1015/cm2.
  • phosphorus is utilised as an N type impurity to thereby achieve a desired electroconductivity in the source/drain regions even without thermal treatment.
  • the channel doped layer formed in the N type well 13 is not subjected to a thermal hysteresis, thereby maintaining the quite shallow P-N junction depth as it is.
  • the prior art utilises arsenic as the N type impurity, which has a smaller diffusion coefficient than phosphorus, thereby necessitating high temperature thermal diffusion process at about 950 °C for about 30 minutes.
  • Step H the remaining source/drain regions are formed for the P channel MOS transistor.
  • the previously formed part of the N channel MOS transistor is masked by a photoresist 15.
  • a P type impurity such as BF2 is ion-implanted at a high density to form the source/drain regions.
  • This ion implantation is conditioned such that the acceleration energy is set to 80 keV and the dose is set to 5 x 1015/cm2.
  • Figure 12 shows a completed state of the N+ unipolar gate structure of the CMOS transistor pair.
  • a boron phosphorous silicon glass (BPSG) inter-layer film 19 is deposited entirely.
  • This inter-layer film 19 is formed by, for example, chemical vapour deposition (CVD), and is then levelled by thermal treatment.
  • CVD chemical vapour deposition
  • the inter-layer film 19 is selectively etched to form contact holes which communicate with the source/drain regions.
  • contact reflow treatment is conducted at 900 °C for about 30 minutes within O2/N2 gas.
  • the P channel MOS transistor thus formed has a channel doped layer 22 which is located in a quite shallow level in the vicinity of the surface of the N type well 13, and its P-N junction depth is adjusted at about 0.15 ⁇ m.
  • a microcomputer 51 receives a power source voltage through a pair of power source terminals V ss and V cc .
  • This microcomputer 51 can be operated at a relatively low voltage by using an external 1.5 V power source 52 such as a dry battery.
  • a smoothing capacitor 53 is externally connected between the pair of power source terminals.
  • An oscillating source 54 is externally connected across a pair of clock input terminals CL1 and CL2 to input a system clock.
  • This oscillating source 54 is composed of, for example, ceramics having an oscillating frequency of 1 MHz.
  • the microcomputer 51 has a low operation voltage and a just operation speed such that the microcomputer can perform fast operation in response to the system clock.
  • an RMO terminal is connected to an infrared light emitting diode 56 through an external driver circuit 55. This infrared light emitting diode 56 transmits a signal for remote control.
  • a reset terminal RESET is connected to an external reset circuit 57.
  • External switches 58 are connected to a set of switch input terminals P00 - P03.
  • an external key matrix 59 or a keyboard is connected to a set of interface terminals P10 - P43.
  • Figure 14 is a block diagram showing a detailed construction of the one chip type microcomputer 51 shown in figure 13.
  • the microcomputer 51 contains logical blocks such as ALU, decoder, timer and counter, all of which are comprised of CMOS transistor pairs according to the present invention.
  • the microcomputer contains memory blocks such as ROM, RAM, table and register, all of which are composed of the inventive CMOS transistor pairs. The same is true for the remaining blocks such as input/output ports and buffers.
  • the present invention has the following effects in a CMOS transistor which is composed of a pair of a P channel MOS transistor having a polysilicon gate and a N channel MOS transistor having also a polysilicon gate.
  • the channel regions of the MOS transistors are formed so as to have as shallow a P-N junction depth as possible, especially the P channel MOS transistor is formed so that it's structure is similar to that of a surface channel type device. Therefore, the leak current can be substantially decreased. Further, the thickness of a gate oxide film is decreased and additionally the impurity concentration of the substrate surface just below the gate electrode is lowered as much as possible.
  • the present invention has an effect that high speed operation can be realised. Accordingly, as the leak current can be restrained even when the threshold voltage is lowered, low voltage drive can be also realised as well as the high speed operation.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
EP93303957A 1992-05-22 1993-05-21 Semiconductor device Withdrawn EP0571224A1 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP13107692 1992-05-22
JP131076/92 1992-05-22
JP57555/93 1993-03-17
JP5755593 1993-03-17

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EP0571224A1 true EP0571224A1 (en) 1993-11-24

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EP (1) EP0571224A1 (ko)
KR (1) KR940006277A (ko)

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Publication number Priority date Publication date Assignee Title
JP3400891B2 (ja) * 1995-05-29 2003-04-28 三菱電機株式会社 半導体記憶装置およびその製造方法
US6204517B1 (en) * 1998-04-09 2001-03-20 Texas Instruments-Acer Incorporated Single electron transistor memory array
US6881634B2 (en) * 2002-08-30 2005-04-19 Cypress Semiconductor Corporation Buried-channel transistor with reduced leakage current

Family Cites Families (1)

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Publication number Priority date Publication date Assignee Title
NL8303441A (nl) * 1983-10-07 1985-05-01 Philips Nv Geintegreerde schakeling met komplementaire veldeffekttransistors.

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
1989 SYMPOSIUM ON VLSI TECHNOLOGY DIGEST OF TECHNICAL PAPERS 22 May 1989, KYOTO, JAPAN pages 13 - 14 Y. OKAZAKI ET AL. 'A high performance 0.22 micron gate CMOS technology' *
EXTENDED ABSTRACTS vol. 87, no. 1, 1987, PRINCETON, NEW JERSEY US page 211 YOSHIO NISHI 'CMOS Technology Status and Challenges' *
INTERNATIONAL ELECTRON DEVICES MEETING 5 December 1983, WASHINGTON, DC pages 534 - 537 SHANG-YI CHIANG ET AL. 'Optimization of sub-micron P-channel FET structure' *
PATENT ABSTRACTS OF JAPAN vol. 011, no. 254 (E-533)18 August 1987 & JP-A-62 065 374 ( TOSHIBA CORP. ) 24 March 1987 *

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KR940006277A (ko) 1994-03-23

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