KR960026938A - 피(p)형 금속 산화물 반도체 전계효과 트랜지스터(PMOSFET) 반도체장치와 그의 제조방법 및 상보형 금속 산화물 반도체(CMOS) 장치 - Google Patents

피(p)형 금속 산화물 반도체 전계효과 트랜지스터(PMOSFET) 반도체장치와 그의 제조방법 및 상보형 금속 산화물 반도체(CMOS) 장치 Download PDF

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KR960026938A
KR960026938A KR1019950045754A KR19950045754A KR960026938A KR 960026938 A KR960026938 A KR 960026938A KR 1019950045754 A KR1019950045754 A KR 1019950045754A KR 19950045754 A KR19950045754 A KR 19950045754A KR 960026938 A KR960026938 A KR 960026938A
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pmosfet
channel region
semiconductor device
substrate
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씨.키지랄리 이식
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엘리 웨이스
에이티앤드티 코포레이션
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Abstract

인듐이나 갈륨을 포함하는 불순물 농도를 가진 매입 채널과 n+폴리실리콘 게이트를 구비한 서브-미크론의 PMOSFET가 제공된다. 매입채널형 PMOSFET는 숏 채널 특성이 개선되어, 특히 CMOS 기술에서 사용하기에 적합하다.

Description

피(P)형 금속 산화물 반도체 전계효과 트랜지스터(PMOSFET) 반도체장치와 그의 제조방법 및 상보형 금속 산화물 반도체(CMOS) 장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명에 따른 매입채널 PMOSFET장치의 단면도.

Claims (29)

  1. PMOSFET 반도체 장치에 있어서, (a)주표면을 갖는 제1의 도전형의 반도체 기판,(b) 서로 분리될 상기 반도체 기판의 주표면내에 형성되는 제2의 도전형의 소오스 및 드레인 영역으로서, 상기 소오스와 드레인 영역 사이의 상기 기판의 주표면내에 채널 영역이 규정되고, 상기 채널영역이 인듐, 갈륨 및 그 혼합물로 이루어지는 군에서 선택된 불순물 이온을 포함하는, 상기 소오스 및 드레인 영역,(c) 상기 채널영역의 주표면상에 현성된 절연막과 (d) 상기 채널영역과 마주하여 상기 채널영역을 거쳐서 상기 절연막의 표면에 형성되고, 고 불순물 농도의 상기 제1의 도전형 이온을 갖는 폴리실리콘을 포함하는 제1의 도전형의 게이트 전극을 포함하는 PMOSFET 반도체장치
  2. 제1항에 있어서, 상기 반도체 기판은 실리콘 기판을 포함하는 PMOSFET 반도체장치
  3. 제2항에 있어서, 상기 반도체 기판은 n형 기판을 포함하고, 상기 채널영역은 p형 영역을 포함하며, 상기 소오스 및 드레인 영역은 p형 영역을 포함하고, 상기 게이트 전극은 n형 폴리실리콘을 포함하는 PMOSFET 반도체장치
  4. 제2항에 있어서, 상기 기판은 인, 비소 및 안티몬으로 이루어지는 군에서 선택된 불순물 이온을 포함하는 n웰 영역을 포함하는 PMOSFET 반도체장치
  5. 제1항에 있어서, 상기 채널영역은 인듐을 포함하는 불순물 이온을 포함하는 PMOSFET 반도체장치
  6. 제1항에 있어서, 상기 채널영역은 갈륨을 포함하는 불순물 이온을 포함하는 PMOSFET 반도체장치
  7. 제1항에 있어서, 상기 채널영역은 인듐을 포함하는 불순물 이온과 갈륨, 붕소 및 그 혼합물로 이루어지는 군에서 선택된 적어도 하나의 p형 불순물 이온을 포함하는 PMOSFET 반도체장치
  8. 제3항에 있어서, 상기 채널영역은 입방 센티미터당 약 1×1016~1×1019캐리어의 인듐을 포함하는 불순물 농도를 포함하는 PMOSFET 반도체장치
  9. 제3항에 있어서, 상기 채널영역은 입방 센티미터당 약 1×1016~1×1019캐리어의 갈륨을 포함하는 불순물 농도를 포함하는 PMOSFET 반도체장치
  10. 제1항에 있어서, 상기 폴리실리콘 게이트 전극은 약 1㎛보다 작은 길이를 갖는 PMOSFET 반도체장치
  11. 제1항에 있어서, 상기 폴리실리콘 게이트 전극은 약 0.5㎛보다 작은 길이를 갖는 PMOSFET 반도체장치
  12. 제1항에 있어서, 상기 n형 폴리실리콘 게이트 전극은 입방 센티미터당 약 1019~1021캐리어의 이온농도를 갖는 PMOSFET 반도체장치
  13. 제1항에 있어서, 상기 채널영역은 약 0.5㎛보다 작은 유효채널 길이를 갖는 PMOSFET 반도체장치
  14. 제1항에 있어서, 상기 채널영역은 약 0.1㎛의 깊이를 갖는 PMOSFET 반도체장치
  15. 제1항에 있어서, 상기 채널영역은 약 0.005~0.05㎛의 깊이를 갖는 PMOSFET 반도체장치
  16. 제1항에 있어서, 상기 절연막은 게이트 절연층을 포함하는 PMOSFET 반도체장치
  17. 제16항에 있어서, 상기 게이트 절연층은 약 150Å보다 작은 두께를 갖는 PMOSFET 반도체장치
  18. 제3항에 있어서, 상기 소오스 및 드레인 영역은 붕소, 인듐 및 갈륨으로 이루어지는 군에서 선택된 불순물 이온을 포함하는 PMOSFET 반도체장치
  19. (a)주표면을 갖는 기판을 마련하는 단계, (b)인듐, 갈륨 및 그 혼합물로 이루어지는 군에서 선택된 불순물 이온을 상기 기판의 상기 주표면으로 주입하는 것에 의해 제1의 단부 및 제2의 단부를 갖는 채널 영역을 형성하는 단계, (c)상기 기판의 주표면상에 게이트 산화물층을 형성하는 단계,(d)상기 기판의 주표면 및 상기 게이트 산화물층상에 많이 도핑된 (heavily doped) n형 폴리실리콘 층을 형성하는 단계, (e)상기 게이트 산화물 층상에 적어도 하나의 많이 도핑된 n형 폴리실리콘 게이트 전극을 형성하기 위해 상기 폴리실리콘층을 패터닝하고 에칭하는 단계와 (f) 상기 기판의 주표면으로 불순물 이온을 주입하는 것에 의해, 상기 매입 채널 영역의 제1단부의 인접한 소오스 영역과 상기 매입 채널 영역의 제2단부에 인접한 드레인 영역을 형성하는 단계를 포함하는 PMOSFET장치의 제조방법.
  20. 제19항에 있어서, 상기 폴리실리콘 게이트 전극상에 적어도 하나의 절연체층을 형성하는 단계를 더 포함하는 PMOSFET장치의 제조방법.
  21. 제19항에 있어서, 상기 소오스영역, 드레인영역 및 게이트 전극상에 접촉층을 형성하는 단계를 더 포함하는 PMOSFET장치의 제조방법.
  22. 제 19항에 있어서,상기 기판을 마련하는 단계는 필드 산화물층을 갖는 기판을 마련하는 것을 포함하는 PMOSFET장치의 제조방법.
  23. 제19항에 있어서, 상기 기판을 마련하는 단계는 약 200Å보다 작은 두께를 가진 스크린층을 상기 기판에 도포하는 것을 포함하는 PMOSFET장치의 제조방법.
  24. 제19항에 있어서, 상기 채널영역을 형성하는 단계는 약 1×1011~1×1014㎝-2도즈량의 불순물 이온을 약 100KeV 보다 작은 주입에너지로 주입하는 것을 포함하는 PMOSFET장치의 제조방법.
  25. 제19항에 있어서, 상기 채널영역을 형성하는 단계는 약 1.4×1013㎝-2도즈량의 불순물 이온을 약 30KeV의 주입에너지로 주입하는 것을 포함하는 PMOSFET장치의 제조방법.
  26. 청구범위 제19항의 제조공정에 의해 형성된 PMOSFET장치.
  27. 적어도 하나의 NMOSFET와 적어도 하나의 PMOSFET를 포함하는 CMOS장치에 있어서, 상기 PMOSFET장치는, (a) 주표면을 갖는 n형 반도체 기판, (b) 서로 분리될 상기 반도체 기판의 주표면내에 형성되는 p형 소오스 드레인 영역으로서, 상기 소오스와 드레인 영역 사이의 상기 기판의 주표면내에 채널 영역이 규정되고, 상기 채널영역이 인듐,갈륨 및 그 혼합물로 이루어지는 군에서 선택된 불순물 이온을 포함하는, 상기 p형 소오스 및 드레인 영역, (c)상기 채널영역의 주표면상에 형성된 절연막과 (d)상기 채널영역과 마주하여 상기 채널영역을 거쳐서 상기 절연막의 표면에 형성된 n+형 폴리실리콘 게이트 전극을 포함하는 CMOS장치.
  28. 제27항에 있어서, 상기 PMOSFET의 채널영역은 입방 센티미터당 약 1×1016~1×1019캐리어의 인듐 이온농도를 갖는 CMOS장치.
  29. 제27항에 있어서, 상기 CMOS장치의 게이트 길리는 약 1㎛보다 작은 CMOS장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950045754A 1994-12-01 1995-11-30 피(p)형 금속 산화물 반도체 전계효과 트랜지스터(PMOSFET) 반도체장치와 그의 제조방법 및 상보형 금속 산화물 반도체(CMOS) 장치 KR960026938A (ko)

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