JP5114829B2 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
- Publication number
- JP5114829B2 JP5114829B2 JP2005141248A JP2005141248A JP5114829B2 JP 5114829 B2 JP5114829 B2 JP 5114829B2 JP 2005141248 A JP2005141248 A JP 2005141248A JP 2005141248 A JP2005141248 A JP 2005141248A JP 5114829 B2 JP5114829 B2 JP 5114829B2
- Authority
- JP
- Japan
- Prior art keywords
- conductivity type
- gate electrode
- source
- semiconductor device
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 78
- 238000004519 manufacturing process Methods 0.000 title claims description 21
- 239000012535 impurity Substances 0.000 claims description 52
- 239000000758 substrate Substances 0.000 claims description 36
- 238000005468 ion implantation Methods 0.000 claims description 34
- 238000000034 method Methods 0.000 claims description 23
- 230000008569 process Effects 0.000 claims description 20
- 238000002513 implantation Methods 0.000 claims description 13
- 230000003321 amplification Effects 0.000 description 27
- 238000003199 nucleic acid amplification method Methods 0.000 description 27
- 230000000694 effects Effects 0.000 description 17
- 239000010410 layer Substances 0.000 description 16
- 230000009977 dual effect Effects 0.000 description 10
- 238000006243 chemical reaction Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 230000005684 electric field Effects 0.000 description 6
- 238000002955 isolation Methods 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical class N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 238000004335 scaling law Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000003384 imaging method Methods 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 230000035945 sensitivity Effects 0.000 description 2
- 230000004913 activation Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000002596 correlated effect Effects 0.000 description 1
- 230000000875 corresponding effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010893 electron trap Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7838—Field effect transistors with field effect produced by an insulated gate without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/766—Addressed sensors, e.g. MOS or CMOS sensors comprising control or output lines used for a plurality of functions, e.g. for pixel output, driving, reset or power
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/942—Masking
- Y10S438/945—Special, e.g. metal
Description
本発明の半導体装置では、従来のようなソース・ドレイン領域と逆極性のポケット領域がないことから、基板不純物濃度が低減され、基板バイアス効果が減少する。この結果、当該半導体装置をソースフォロア回路に適用した場合に、ソースフォロア回路のリニアリティ特性が向上する。
また、低濃度の第2ソース・ドレイン領域により電界が緩和されることから、短チャネル効果が抑制される。また、高濃度の第1ソース・ドレイン領域の距離が確保されており、この第1ソース・ドレイン領域間に実質的なチャネルが形成されるため、チャネル長が確保される。このため、短チャネル効果が抑制される。
さらに、埋め込みチャネル構造を採用するため、ゲート絶縁膜/半導体基板界面でキャリアとなる電子あるいは正孔のトラップ準位が形成されても、当該トラップ準位によるチャネルへ流れる電流への影響が抑えられる。すなわち、1/fノイズの発生原因となるトラップ準位による電流のゆらぎが抑制される。
また、従来のように、ゲート電極をマスクとしたイオン注入によりポケット領域やエクステンション領域を形成することはないため、表面チャネル型の半導体装置の製造工程に比べて、製造工程を削減することができる。
成の一例を示すブロック図である。
図2は、単位画素11の回路構成の一例を示す回路図である。
例えば本実施形態では、nMOSトランジスタを例に挙げたが、pMOSトランジスタであってもよい。この場合には、p型が第1導電型、n型が第2導電型となる。すなわち、図4の各種の領域の導電型が逆の導電型となる。
その他、本発明の要旨を逸脱しない範囲で、種々の変更が可能である。
Claims (7)
- 半導体基板に形成され、ソースフォロア回路に用いられ、ゲート電極に印加される信号を増幅して2つの第1ソース・ドレイン領域の一方からソースフォロアで出力するトランジスタを有し、
前記トランジスタは、
前記半導体基板の第2導電型ウェル上にゲート絶縁膜を介して形成されたゲート電極と、
前記ゲート電極下のチャネル領域となる、前記第2導電型ウェルの部分に形成され、第1導電型不純物を含有する第1導電型層と、
前記ゲート電極の両側における前記第2導電型ウェルの部分に形成された第1導電型の前記2つの第1ソース・ドレイン領域と、
前記第1ソース・ドレイン領域よりも第1導電型不純物濃度が低く、前記ゲート電極の一部とオーバーラップするように、それぞれが対応する前記第1ソース・ドレイン領域の、ゲート電極側の側面から底面の周囲に位置する、前記第2導電型ウェルの部分に、互いに分離して形成された第1導電型の2つの第2ソース・ドレイン領域と、
を有する、
半導体装置。 - 前記トランジスタは、
前記ゲート電極の両側に形成されたサイドウォール絶縁膜をさらに有し、
前記第1ソース・ドレイン領域は、前記サイドウォール絶縁膜の両側の前記第2導電型ウェルの部分に形成される、
請求項1記載の半導体装置。 - 前記ゲート電極は、第2導電型不純物を含有する
請求項1または2記載の半導体装置。 - 半導体基板に、ソースフォロア回路に用いられ、ゲート電極に印加される信号を増幅して2つの第1ソース・ドレイン領域の一方からソースフォロアで出力するトランジスタを形成するために、
前記半導体基板のチャネル領域となる第2導電型ウェルに第1導電型不純物を導入して第1導電型層を形成する工程と、
前記第1導電型層が形成された前記第2導電型ウェル上にゲート絶縁膜を形成する工程と、
前記ゲート絶縁膜上にゲート電極を形成する工程と、
前記ゲート電極の両側にサイドウォール絶縁膜を形成する工程と、
前記ゲート電極および前記サイドウォール絶縁膜をマスクとした第1導電型不純物の第1イオン注入処理により、前記2つの第1ソース・ドレイン領域を形成する工程と、
前記第1イオン注入処理よりも前記第1導電型不純物のドーズ量が小さくかつ前記第1導電型不純物の注入深さが深い第2イオン注入処理により、前記ゲート電極の一部とオーバーラップし、かつ前記第1ソース・ドレイン領域の、ゲート電極側の側面から底面の周囲に位置する、前記第2導電型ウェルの部分に、互いに分離して2つの第2ソース・ドレイン領域を形成する工程と、
を有する半導体装置の製造方法。 - 前記ゲート電極を形成する工程において、第2導電型不純物を含有する前記ゲート電極を形成する
請求項4記載の半導体装置の製造方法。 - 前記第1イオン注入処理および前記第2イオン注入処理の合計での前記第1導電型不純物のドーズ量が、前記ゲート電極に導入された第2導電型不純物の量よりも小さく設定された
請求項5記載の半導体装置の製造方法。 - 前記第2イオン注入処理において、前記半導体基板の主面に対して斜め方向からイオン注入を行う
請求項4から6のいずれか一項記載の半導体装置の製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005141248A JP5114829B2 (ja) | 2005-05-13 | 2005-05-13 | 半導体装置およびその製造方法 |
US11/432,264 US7718498B2 (en) | 2005-05-13 | 2006-05-11 | Semiconductor device and method of producing same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005141248A JP5114829B2 (ja) | 2005-05-13 | 2005-05-13 | 半導体装置およびその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006319185A JP2006319185A (ja) | 2006-11-24 |
JP5114829B2 true JP5114829B2 (ja) | 2013-01-09 |
Family
ID=37494686
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005141248A Expired - Fee Related JP5114829B2 (ja) | 2005-05-13 | 2005-05-13 | 半導体装置およびその製造方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US7718498B2 (ja) |
JP (1) | JP5114829B2 (ja) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100817093B1 (ko) * | 2007-03-16 | 2008-03-26 | 삼성전자주식회사 | 아일랜드 영역을 포함하는 반도체 소자 |
KR100851757B1 (ko) * | 2007-05-03 | 2008-08-11 | 동부일렉트로닉스 주식회사 | 이미지센서 및 그 제조방법 |
KR101344441B1 (ko) * | 2007-07-16 | 2013-12-23 | 삼성전자 주식회사 | 이미지 센서 및 그 제조 방법 |
JP5335271B2 (ja) * | 2008-04-09 | 2013-11-06 | キヤノン株式会社 | 光電変換装置及びそれを用いた撮像システム |
JP2009283649A (ja) * | 2008-05-22 | 2009-12-03 | Panasonic Corp | 固体撮像装置及びその製造方法 |
CN101299439B (zh) * | 2008-06-24 | 2011-06-22 | 广州南科集成电子有限公司 | 耐高压恒流源器件及制造方法 |
JP4911158B2 (ja) * | 2008-10-30 | 2012-04-04 | ソニー株式会社 | 半導体装置および固体撮像装置 |
JP5493430B2 (ja) | 2009-03-31 | 2014-05-14 | ソニー株式会社 | 固体撮像装置とその製造方法、及び電子機器 |
JP5434489B2 (ja) * | 2009-11-06 | 2014-03-05 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
JP2013045879A (ja) * | 2011-08-24 | 2013-03-04 | Sony Corp | 半導体装置、半導体装置の製造方法、固体撮像装置、固体撮像装置の製造方法、電子機器 |
US9363451B2 (en) | 2011-12-19 | 2016-06-07 | Sony Corporation | Solid-state imaging device, method of manufacturing solid-state imaging device, and electronic apparatus |
JP2013247347A (ja) * | 2012-05-29 | 2013-12-09 | Canon Inc | 半導体装置及びその製造方法 |
KR102131327B1 (ko) | 2013-08-16 | 2020-07-07 | 삼성전자 주식회사 | 소스 팔로워를 포함하는 이미지 센서 |
US10490438B2 (en) * | 2014-03-07 | 2019-11-26 | Toshiba Memory Corporation | Non-volatile semiconductor memory device and manufacturing method of p-channel MOS transistor |
KR102509203B1 (ko) * | 2014-08-29 | 2023-03-14 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 촬상 장치 및 전자 기기 |
CN107195645B (zh) * | 2016-03-14 | 2023-10-03 | 松下知识产权经营株式会社 | 摄像装置 |
CN108695161B (zh) * | 2017-04-07 | 2021-06-08 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件及其形成方法 |
TWI621273B (zh) * | 2017-04-27 | 2018-04-11 | 立錡科技股份有限公司 | 具有可調整臨界電壓之高壓空乏型mos元件及其製造方法 |
Family Cites Families (45)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4062699A (en) * | 1976-02-20 | 1977-12-13 | Western Digital Corporation | Method for fabricating diffusion self-aligned short channel MOS device |
JPS61189712A (ja) * | 1985-02-18 | 1986-08-23 | Sharp Corp | モス型電界効果トランジスタの低ノイズ駆動方法 |
US5266510A (en) * | 1990-08-09 | 1993-11-30 | Micron Technology, Inc. | High performance sub-micron p-channel transistor with germanium implant |
US5401994A (en) * | 1991-05-21 | 1995-03-28 | Sharp Kabushiki Kaisha | Semiconductor device with a non-uniformly doped channel |
JP3253179B2 (ja) | 1992-06-30 | 2002-02-04 | 株式会社リコー | 光電変換装置 |
US5352914A (en) * | 1992-08-03 | 1994-10-04 | Hughes Aircraft Company | Field-effect transistor with structure for suppressing hot-electron effects, and method of fabricating the transistor |
US5396096A (en) * | 1992-10-07 | 1995-03-07 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and manufacturing method thereof |
US5583067A (en) * | 1993-01-22 | 1996-12-10 | Intel Corporation | Inverse T-gate semiconductor device with self-aligned punchthrough stops and method of fabrication |
JPH07122733A (ja) * | 1993-10-21 | 1995-05-12 | Nec Corp | 電荷転送装置およびその製造方法 |
US5622880A (en) * | 1994-08-18 | 1997-04-22 | Sun Microsystems, Inc. | Method of making a low power, high performance junction transistor |
JP3601612B2 (ja) * | 1994-09-22 | 2004-12-15 | 富士通株式会社 | 半導体装置及びその製造方法 |
TW304301B (ja) * | 1994-12-01 | 1997-05-01 | At & T Corp | |
US5650350A (en) * | 1995-08-11 | 1997-07-22 | Micron Technology, Inc. | Semiconductor processing method of forming a static random access memory cell and static random access memory cell |
JP3305197B2 (ja) * | 1995-09-14 | 2002-07-22 | 株式会社東芝 | 半導体装置 |
JP3472655B2 (ja) * | 1995-10-16 | 2003-12-02 | ユー・エム・シー・ジャパン株式会社 | 半導体装置 |
US5923987A (en) * | 1997-06-30 | 1999-07-13 | Sun Microsystems, Inc. | Method for forming MOS devices with retrograde pocket regions and counter dopant regions at the substrate surface |
US5985727A (en) * | 1997-06-30 | 1999-11-16 | Sun Microsystems, Inc. | Method for forming MOS devices with retrograde pocket regions and counter dopant regions buried in the substrate surface |
TW388087B (en) * | 1997-11-20 | 2000-04-21 | Winbond Electronics Corp | Method of forming buried-channel P-type metal oxide semiconductor |
US6960499B2 (en) * | 1998-02-24 | 2005-11-01 | Texas Instruments Incorporated | Dual-counterdoped channel field effect transistor and method |
JPH11274472A (ja) * | 1998-03-26 | 1999-10-08 | Sanyo Electric Co Ltd | 電荷転送素子 |
US5985705A (en) * | 1998-06-30 | 1999-11-16 | Lsi Logic Corporation | Low threshold voltage MOS transistor and method of manufacture |
US6218251B1 (en) * | 1998-11-06 | 2001-04-17 | Advanced Micro Devices, Inc. | Asymmetrical IGFET devices with spacers formed by HDP techniques |
US20020036328A1 (en) * | 1998-11-16 | 2002-03-28 | William R. Richards, Jr. | Offset drain fermi-threshold field effect transistors |
KR100357644B1 (ko) * | 1999-02-19 | 2002-10-25 | 미쓰비시덴키 가부시키가이샤 | 비휘발성 반도체 기억장치 및 그 구동방법, 동작방법 및제조방법 |
JP3621844B2 (ja) * | 1999-02-24 | 2005-02-16 | シャープ株式会社 | 増幅型固体撮像装置 |
US6333217B1 (en) * | 1999-05-14 | 2001-12-25 | Matsushita Electric Industrial Co., Ltd. | Method of forming MOSFET with channel, extension and pocket implants |
JP3695996B2 (ja) * | 1999-07-07 | 2005-09-14 | 日本電信電話株式会社 | 相補型ソースフォロワ回路 |
US7091093B1 (en) * | 1999-09-17 | 2006-08-15 | Matsushita Electric Industrial Co., Ltd. | Method for fabricating a semiconductor device having a pocket dopant diffused layer |
US6432802B1 (en) * | 1999-09-17 | 2002-08-13 | Matsushita Electronics Corporation | Method for fabricating semiconductor device |
JP4671459B2 (ja) * | 1999-10-20 | 2011-04-20 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
US6548842B1 (en) * | 2000-03-31 | 2003-04-15 | National Semiconductor Corporation | Field-effect transistor for alleviating short-channel effects |
US7145191B1 (en) * | 2000-03-31 | 2006-12-05 | National Semiconductor Corporation | P-channel field-effect transistor with reduced junction capacitance |
US6720632B2 (en) * | 2000-06-20 | 2004-04-13 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device having diffusion layer formed using dopant of large mass number |
JP3750502B2 (ja) | 2000-08-03 | 2006-03-01 | ソニー株式会社 | 固体撮像装置およびカメラシステム |
JP2002198529A (ja) * | 2000-10-18 | 2002-07-12 | Hitachi Ltd | 半導体装置およびその製造方法 |
US20020058385A1 (en) * | 2000-10-26 | 2002-05-16 | Taiji Noda | Semiconductor device and method for manufacturing the same |
US6555872B1 (en) * | 2000-11-22 | 2003-04-29 | Thunderbird Technologies, Inc. | Trench gate fermi-threshold field effect transistors |
KR100495914B1 (ko) * | 2002-05-24 | 2005-06-20 | 주식회사 하이닉스반도체 | 씨모스트랜지스터 및 그 제조 방법 |
US6756276B1 (en) * | 2002-09-30 | 2004-06-29 | Advanced Micro Devices, Inc. | Strained silicon MOSFET having improved source/drain extension dopant diffusion resistance and method for its fabrication |
JP4188637B2 (ja) * | 2002-08-05 | 2008-11-26 | 独立行政法人産業技術総合研究所 | 半導体装置 |
CN1286157C (zh) * | 2002-10-10 | 2006-11-22 | 松下电器产业株式会社 | 半导体装置及其制造方法 |
JP2004241638A (ja) * | 2003-02-06 | 2004-08-26 | Sanyo Electric Co Ltd | 電荷転送素子 |
JP4247163B2 (ja) * | 2003-12-25 | 2009-04-02 | 株式会社東芝 | 半導体装置およびその製造方法 |
CN1694263A (zh) * | 2004-05-07 | 2005-11-09 | 松下电器产业株式会社 | 半导体装置及其制造方法 |
KR101455404B1 (ko) * | 2005-12-09 | 2014-10-27 | 세미이큅, 인코포레이티드 | 탄소 클러스터의 주입에 의한 반도체 디바이스의 제조를위한 시스템 및 방법 |
-
2005
- 2005-05-13 JP JP2005141248A patent/JP5114829B2/ja not_active Expired - Fee Related
-
2006
- 2006-05-11 US US11/432,264 patent/US7718498B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US20060275990A1 (en) | 2006-12-07 |
JP2006319185A (ja) | 2006-11-24 |
US7718498B2 (en) | 2010-05-18 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5114829B2 (ja) | 半導体装置およびその製造方法 | |
US7795655B2 (en) | Solid-state imaging device and electronic device | |
JP5426114B2 (ja) | 半導体装置及びその製造方法 | |
JP5110820B2 (ja) | 光電変換装置、光電変換装置の製造方法及び撮像システム | |
JP4513497B2 (ja) | 固体撮像装置 | |
WO2014002361A1 (ja) | 固体撮像装置及びその製造方法 | |
KR100746222B1 (ko) | 이미지 센서의 제조방법들 | |
WO2013027524A1 (ja) | 固体撮像素子 | |
JP2008166607A (ja) | 固体撮像装置とその製造方法、並びに半導体装置とその製造方法 | |
JP2009283649A (ja) | 固体撮像装置及びその製造方法 | |
TW201310628A (zh) | 固態成像裝置,製造固態成像裝置之方法,及電子裝置 | |
WO2010122621A1 (ja) | 固体撮像装置 | |
JP2007088305A (ja) | 固体撮像装置およびその製造方法、並びにカメラ | |
JP4923596B2 (ja) | 固体撮像装置 | |
JP2007305925A (ja) | 固体撮像装置 | |
JP5050512B2 (ja) | 固体撮像装置の製造方法および半導体装置の製造方法 | |
KR20050038034A (ko) | 이미지 센서, 이미지 센서를 포함하는 카메라 시스템 및 이미지 센서 제조 방법 | |
JP5267497B2 (ja) | 固体撮像装置 | |
JP5274118B2 (ja) | 固体撮像装置 | |
JP2008108916A (ja) | 固体撮像装置及び電子機器 | |
JP4810831B2 (ja) | 半導体装置及びその製造方法 | |
JP2005302836A (ja) | 固体撮像装置の製造方法 | |
JP2007250956A (ja) | 固体撮像素子及びその製造方法 | |
JP2004022624A (ja) | 固体撮像装置の製造方法 | |
JP2007123680A (ja) | 固体撮像装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20080501 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20101108 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20101116 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20110117 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20111227 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120227 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20120918 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20121001 |
|
R151 | Written notification of patent or utility model registration |
Ref document number: 5114829 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R151 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20151026 Year of fee payment: 3 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313111 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |