CN1132941A - Pmosfet及由此制造的cmos器件 - Google Patents

Pmosfet及由此制造的cmos器件 Download PDF

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CN1132941A
CN1132941A CN95120272A CN95120272A CN1132941A CN 1132941 A CN1132941 A CN 1132941A CN 95120272 A CN95120272 A CN 95120272A CN 95120272 A CN95120272 A CN 95120272A CN 1132941 A CN1132941 A CN 1132941A
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伊西克·C·基兹尔亚利
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Abstract

提出了一种亚微米PMOSFET，它包含n+多晶硅栅和具有In或Ga杂质浓度的掩埋沟道。此掩埋沟道PMOSFET具有改进了的短沟道特性且特别适合于CMOS工艺。

Description

PMOSFET及由此制造的CMOS器件
本发明一般涉及到半导体器件，具体地说，本发明涉及到一种带有n+多晶硅栅的新颖的掺In或掺Ga掩埋P沟道的金属氧化物半导体场效应晶体管(PMOSFET)。此处所述的PMOSFET具有改善了的短沟道特性，特别适用于互补金属氧化物半导体(CMOS)工艺。
制作MOSFET的各种方法在本领域中是众所周知的。在甚大规模集成电路(VLSI)或超大规模集成电路(ULSI)的应用中，具有1μm或更小有效短沟道长度的MOSFET是特别合乎需要的。FET集成电路集成密度的改善借助于缩小器件尺寸来达到。有效沟道长度1.0μm或更小的常规MOSFET表现出诸如较大的Vth偏移、亚阀值漏电和沟道穿通之类的有害于小尺寸器件性能的短沟道效应。
半导体材料的特性可用杂质离子对半导体材料进行掺杂的方法来修正。诸如硼、磷、砷和锑之类的常规杂质可用来控制MOS-FET各层的电阻率。PMOSFET的沟道常用硼或BF2之类的硼的化合物来掺杂。例如见T.ohguro等人“带有超高真空CVD生长的超薄外延沟道层的0.1μmPMOSFET”，IEDM文集，PP433—436(1993)。但用硼或硼化物掺杂的P沟道呈现向PMOS器件衬底的不希望有的扩散和渗透。
比之用硼离子获得的注入掺杂分布，In离子呈现更陡的注入掺杂分布。铟杂质离子已被注入到亚微米NMOSFET中以获得非均匀的沟道掺杂。见G.G.shahidi等人，“用于改善亚微米NMOS-FET短沟道行为的铟沟道注入剂”，IEEE Electron Device Letters，Vol.14，No.8，PP.409-411(1993)。
P+多晶硅栅已用于亚半微米PMOS掩埋沟道晶体管以减小某些短沟道效应。例如见S.J.Hillenius等人“对称亚微米CMOS工艺”，IEDM文集，PP.252—255(1986)。但当带有P+多晶硅栅的PMOSFET应用于CMOS工艺时，需要二个多晶硅栅工艺，即CMOS器件NMOSFET的n+多晶硅栅和PMOSFET的P+多晶硅栅。在CMOS工艺中同时出现n+和P+多晶硅栅工艺使工艺流程复杂化并使成本升高。而且，P+多晶硅栅一般用硼掺杂，它具有渗透晶体管的栅极氧化物和衬底的不希望有的倾向。此外，P+多晶硅可获得的最低薄层电阻比n+多晶硅大2—3倍。
为获得带有窄沟和改善的短沟道特性的半导体器件，带有n+多晶硅栅和用注入杂质分布更陡而掺杂离子更少扩散到衬底去的杂质进行掺杂的掩埋沟道的PMOSFET是人们所希望的。
本发明提供了带有n+多晶硅栅的掺铟或掺镓掩埋沟道PMOS场效应晶体管。提供了一种制作具有窄的掩埋沟道和有效沟道长度约为0.5μm或更短的PMOSFET的方法。此处所述的较窄掩埋沟道PMOSFET呈现改善的短沟道特性，包括小的Vth偏移、降低了的沟道穿通以及降低了的亚阈值漏电。还提供了包括此处所述的掩埋沟道PMOSFET的CMOS器件。
图1是根据本发明的掩埋沟道PMOSFET器件剖面的侧视图；
图2—7剖面侧视图示出了各制造阶段中提供的根据本发明的掩埋沟道PMOSFET中间结构。图8示出了掩埋沟道中硼离子的离子注入分布以及常规PMOSFET n阱中磷和砷的离子注入分布。
图9示出了掩埋沟道中铟离子的离子注入分布以及根据本发明的PMOSFET的n阱中磷和砷离子的离子注入分布。
图10示出了三个掩埋沟道深度不同的掩埋沟道PMOSFET的亚阈值漏电流(Ioff)，在恒定阈值电压下，Ioff示为有效沟道长度的函数。
此处所述的PMOSFET具有n+多晶硅栅和含有铟或镓杂质离子的掩埋沟道。由于In和Ga的原子序数比B大，故比之掺B的掩埋沟道，根据本发明得到的掩埋沟道具有更陡的注入掺杂分布。而且，比之硼和硼化物(为BF2)，In和Ga在硅中的扩散常数更小。更陡的注入掺杂分布以及In或Ga在此处所述的PMOSFET掩埋沟道中较低的扩散率导致形成窄的掩埋沟道，亦即得到掩埋沟道深度减小了的掩埋沟道(其中沟道深度从衬底同栅氧化层交界面算起)。本发明可提供比掺硼的沟道窄约500的掩埋沟道PMOSFET。
当掩埋沟道深度降低时，沟道的最小长度(Lmin)可获得明显改善。为避免不利的短沟道效应，栅长应大于Lmin。本发明的掺In或掺Ga的掩埋沟道PMOSFET特别适用于制作具有改善的短沟道特性的亚半微米PMOS晶体管。
图1是根据本发明的掩埋沟道PMOSFET最佳实施例的剖面侧视图。PMOSFET包括一个衬底10、场氧化层12、掩埋沟道区15、栅氧化物16a、n+多晶硅栅电极18a、源区22、漏区24以及空间隔离层26。
图2-6剖面侧视图示出了根据本发明一个实施例的掩埋沟道PMOSFET其不同制造阶段得到的中间结构。参照图2，衬底10用作制造掩埋沟道PMOSFET的起始材料。衬底10包含诸如硅、锗或砷的半导体材料。衬底10最好是用磷或砷离子注入成杂质浓度约为1×1016—约1×1019载流子/cm3的n型硅片或n型硅片。衬底10的取向最好为<100>，电阻率最好为大约10-3—大约10Ωcm。在一个实施例中，n阱可包括一个抑制穿通的注入剂，例如1.5×1013cm-2剂量的砷离子。此外，衬底10最好包括一个衬底主表面附近的场氧化层12以便将MOSFET同其附近的其它结构隔离开来。含SiO2的场氧化层是较好的。
用常规氧化工艺可在硅衬底10的主表面上制作一个屏蔽层14以保护衬底表面免受离子注入过程中的沾污，如图3所示。屏蔽层14最好包含厚度为约50A—约200A的SiO2。参照图3，将In或Ga离子通过屏蔽层14引入衬底10。在掺杂步骤过程中，屏蔽层的存在是有利的；但离子也可注入到没有屏蔽层的衬底中。In或Ga掺杂剂注入衬底10中由图3虚线所示的深度以形成掩埋沟道区15。作为变通，也可在衬底10中注入In和Ga离子的混合物以获得此处所述的掩埋沟道PMOSFET。在本发明的另一种情况下，可获得带有含In离子和至少另一种掺杂剂的或含Ga离子和至少另一种掺杂剂的掩埋沟道的PMOSFET。为了获得根据本发明的窄的掩埋沟道，In离子是最佳的掺杂剂。
任何掺杂方法都可用来将In或Ga注入到掩埋沟道区。常规的掺杂方法在本领域中是众所周知的。例如，可用扩散或离子注入方法来将In或Ga杂质离子注入到沟道区中。在S.M.Sze的《VL-SI工艺》，MCGraw Hill BOOK Company，第7和8章PP272-374(1988)以及S.Wolf和R.N.Tauber的《Silicon Processing for theVLSI Era Volume 1：Process Technology》，Lattice Press，pp.308-311(1986)中描述了掺杂方法，列此二书为参考。离子注子是一种将掺杂剂引入PMOS器件掩埋沟道的较好方法。注入剂的剂量最好为约1×1011cm-2-1×1014cm-2，而注入剂的能量最好小于约100keV。降低注入剂的能量可得到更窄的掩埋沟道，即掩埋沟道的深度较小，为了得到根据本发明的窄的掩埋沟道，约30keV—约50keV的注入能量是最佳的。注入剂的浓度最好为约1×1016—约1×1019载流子/cm3。杂质离子注入之后可在惰性气氛中执行快速热退火以清除离子注入对衬底10的损伤。
用例如腐蚀的方法将屏蔽层14清除，然后如图4所示在衬底10的主表面上生长一个诸如栅隔离层16的隔离膜。可用热氧化方法在约800℃—约1200℃的温度下来生长衬底10上的栅隔离层16，使栅氧化物的厚度达到约35—约200。约50—约150的栅隔离膜厚度较好，而65的栅隔离层厚度最好。注入在本发明的掩埋沟道PMOSFET中的In或Ga掺杂剂在此热氧化步骤中呈现出比诸如硼离子之类的常规掺杂剂更小的扩散率。
降低了的掺杂剂扩散率特别有利于获得带有改善的短沟道特性的亚半微米晶体管。
如图5所示，在栅氧化层16上沉积了一个重掺杂的n型(n+)多晶硅层18。例如可用在多晶硅层上扩散或注入磷或砷使这一多层硅层成为n+多晶硅的方法来制作此n+多晶硅层。n+多晶硅栅最好包括诸如浓度为约1019—约1021载流子/cm3的磷、砷或锑的杂质离子。
参照图6，借助于用标准的光刻技术使n+多晶硅栅层图形化并腐蚀的方法来确定掩埋沟道PMOS晶体管的多晶硅栅电极18a，以达到约小于1μm的栅极长度。用多晶硅栅的长度来确定PMOS-FET的有效掩埋沟道长度(leff)。于是，小于0.5μm的栅极长度最佳。栅氧化层16a最好在栅电极18a从多晶硅层18被图形和腐蚀的时候加以确定。作为变通，栅氧化层16a也可以在图形化和腐蚀栅电极18a之前确定。
在向衬底10注入离子以形成源区22和漏区24之前，最好在栅电极上沉积一个掩模20。源区22和漏区24可用硼离子或BF2掺杂。作为变通，源区和漏区也可用In或Ga离子掺杂。
然后可在栅电极18a的侧面上制作空间隔离层26。而且，可用任何已知的金属化方法来制作PMOSFET的源、漏和栅接触。
图8示出了带有n+多晶硅栅和掺硼的掩埋沟道的0.5μmPMOSFET的计算机模拟离子注入分布。图9示出了根据本发明的带有n+多晶硅栅和掺In的掩埋沟道的0.5μm PMOSFET的计算机模拟离子注入分布。在60keV下通过200屏蔽氧化物的In离子沟道注入剂的剂量为1.4×10113cm-2。比之硼注入分布In离子，具有更陡的注入分布和在衬底中更小的扩散率。此外，在带有掺In掩埋沟道的PMOSFET的衬底n阱中，得到了更高浓度的n型离子。n阱中提高了的n型离子浓度对降低沟道穿通是有利的。掺In离子的PMOSFET的掩埋沟道深度约为0.03而用硼沟道掺杂得到约为0.05μm的掩埋沟道深度。于是，用In沟道掺杂就得到了更窄的掩埋沟道。
图10示出了三个根据本发明得到的具有不同掩埋沟道深度(XB)的掩埋沟道PMOSFET的亚阈值漏电在0.78V恒定阈值电压下对有效沟道长度的函数关系。三个PMOSFET的沟道深度为0.055μm、0.088μm和0.108μm。当掩埋沟道深度减小时，最小有效沟道长度得到了明显的改善。此处所述的掺In掩埋沟道PMOSFET的窄的掩埋沟道提供了具有诸如最小Vth偏移、降低的沟道穿通以及降低的亚阈值漏电之类的改善了的短沟道特性。
包括本发明的PMOSFET在内的CMOS器件可以用本领域熟知的各种方法来制造。例如见D.Roddy的《Introduction to Micro-electronics》，Pergamon Press，PP.100-102(1978)和《The Electri-cal Engineering Handbook》，Richard C.编，CRC Press，PP.581-584和1631-1635(1993)，这些书此处都引作参考。此处所述的PMOSFET特别适用于低压0.1μm-0.035μmCMOS工艺。
图1-10所述的PMOSFET不是有意要将此处所述的器件限定为任何特定的实施例。根据上面所作的阐述，完全可以对本发明进行修改和改变。例如，本领域熟练人员可采用各种不同的技术来进行离子注入、半导体器件各层的沉积(例如用物理气相淀积或化学气相淀积)、光刻和图形转换以制作此处所述的PMOSFET。而且，根据本发明人们可以在PMOSFET的掩埋沟道中注入In或Ga离子，也可以注入In和Ga离子的组合物。此外，此处所述的PMOSFET的掩埋沟道可用In和至少一种其它掺杂剂或Ga和至少一种其它掺杂剂来掺杂。例如，根据本发明的PMOSFET的掩埋沟道所包含In离子和硼离子。因此应该了解，在所述的本发明特定实施例中可以作出改变而不超出权利要求所规定的本发明的范围。

Claims (29)

1.一种PMOSFET半导体器件，它包含：
a.一个带有一主表面的第一导电类型的半导体衬底；
b.形成在上述半导体衬底主表面内的第二导电类型的相互隔开的源区和漏区，在源区和漏区之间的上述衬底的主表面内确定一个沟道区，上述沟道区包含一个选自In、Ga及其混合物的杂质离子；
c.一个形成在上述沟道区主表面上的隔离膜；以及
d.一个形成在上述隔离膜表面上对着上述沟道区的第一导电类型的栅电极，其中所述的栅电极包含具有上述第一导电类型的离子的高杂质浓度的多晶硅。
2.根据权利要求1的器件，其中所述的半导体衬底包含硅衬底。
3.根据权利要求2的器件，其中所述的半导体衬底包含n型衬底，所述的沟道区包含P型区，所述的源和漏区包含P型区，而所述的栅电极包含n型多晶硅。
4.根据权利要求2的器件，其中所述的衬底包含一个含有选自磷、砷和锑的杂质离子的n阱区。
5.根据权利要求1的PMOSFET器件，其中所述的沟道区包括含In的杂质离子。
6.根据权利要求1的PMOSFET器件，其中所述的沟道区包括含Ga的杂质离子。
7.根据权利要求1的PMOSFET器件，其中所述的沟道区包括含In和至少一种其它选自Ga、B及其混合物的P型杂质离子。
8.根据权利要求3的PMOSFET器件，其中所述的沟道区包括大约1×1016-大约1×1019载流子/cm3的含In的杂质浓度。
9.根据权利要求3的PMOSFET器件，其中所述的沟道区包括～1×1016-～1×1019载流子/cm3的含Ga的杂质浓度。
10.根据权利要求1的PMOSFET器件，其中所述的多晶硅栅电极的长度约小于1μm。
11.根据权利要求1的PMOSFET器件，其中所述的多晶硅栅电极的长度约小于0.5μm。
12.根据权利要求1的PMOSFET器件，其中所述的n型多晶硅栅电极的离子浓度为约1019-1021载流子/cm3。
13.根据权利要求1的PMOSFET器件，其中所述的沟道区的有效沟道长度约小于0.5μm。
14.根据权利要求1的PMOSFET器件，其中所述的沟道区的深度约小于0.1μm。
15.根据权利要求1的PMOSFET器件，其中所述的沟道区的深度为约0.005μm-约0.05μm。
16.根据权利要求1的PMOSFET器件，其中所述的隔离膜包含栅隔离层。
17.根据权利要求16的PMOSFET器件，其中所述的栅隔离层的厚度约小于150A。
18.根据权利要求3的PMOSFET器件，其中所述的源区和漏区包括选自B、In和Ga的杂质离子。
19.一种制作PMOSFET器件的工艺，它包含下列步骤：
a)提供一种带有一主表面的衬底；
b)用将杂质离子注入到上述衬底和上述主表面内的方法，形成一个带有第一和第二端的沟道区，其中所述的杂质离子选自In、Ga或其混合物；
c)在上述衬底的主表面上制作一个栅氧化层；
d)在上述栅氧化层和上述衬底的主表面上制作一个重掺杂的n型多晶硅层；
e)对上述多晶硅层进行图形化和腐蚀，以便在上述栅氧化层上形成至少一个重掺杂的n型多晶硅栅电极；以及
f)用将杂质离子注入到上述衬底的上述主表面内的方法，制作一个靠近上述掩埋沟道区第一端的源区和一个靠近上述掩埋沟道区第二端的漏区。
20.根据权利要求19的制作PMOSFET器件的工艺，还包含在上述多晶硅栅电极上制作至少一个隔离层。
21.根据权利要求19的制作PMOSFET器件的工艺，还包含在上述源区、上述漏区和上述栅电极上制作接触层。
22.根据权利要求19的工艺，其中提供衬底的步骤包含提供一个带有场氧化层的衬底。
23.根据权利要求19的工艺，其中所述的提供衬底的步骤包括将厚度为约小于200A的屏蔽层加于上述衬底。
24.根据权利要求19的工艺，其中所述的形成上述沟道区的步骤包含以大约1×1011cm-2-大约1×1014cm2的剂量，在约小于100keV的注入能量下注入杂质离子。
25.根据权利要求19的工艺，其中所述的形成上述沟道区的步骤包含以～1.4×1013cm-2的剂量，在约30keV的注入能量下注入杂质离子。
26.一种根据权利要求19的工艺生产的PMOSFET器件。
27.一种包含至少一个NMOSFET和至少一个PMOSFET的CMOS器件，其中所述的PMOSFET器件包括：
a)一个带有一个主表面的n型半导体衬底；
b)形成在上述半导体衬底主表面内、彼此分隔开的P型源区和漏区，在源区和漏区之间的上述衬底的主表面内确定了一个沟道区，上述沟道区包括选自In、Ga或其混合物的杂质离子；
c)一个形成在上述沟道区主表面上的隔离膜；以及
d)一个形成在上述隔离膜表面上对着上述沟道区的n+型多晶硅栅电极。
28.根据权利要求27的CMOS器件，其中所述的上述PMOS-FET的沟道区的In离子浓度为～1×1016-～1×1019载流子/cm3。
29.根据权利要求27的CMOS，其中所述的上述CMOS器件的栅长度为约小于1μm。
CN95120272A 1994-12-01 1995-11-27 Pmosfet及由此制造的cmos器件 Pending CN1132941A (zh)

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CN100530696C (zh) * 2004-03-12 2009-08-19 惠普开发有限公司 具有多组分氧化物制备的沟道的半导体器件
CN100364055C (zh) * 2004-09-02 2008-01-23 海力士半导体有限公司 半导体器件的单元沟道离子的注入方法
US20100117074A1 (en) * 2008-11-07 2010-05-13 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
CN101740633A (zh) * 2008-11-07 2010-06-16 株式会社半导体能源研究所 半导体器件及其制造方法
US8395148B2 (en) * 2008-11-07 2013-03-12 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
CN101740633B (zh) * 2008-11-07 2014-10-15 株式会社半导体能源研究所 半导体器件及其制造方法
CN107039506A (zh) * 2010-12-03 2017-08-11 三重富士通半导体股份有限公司 对改进型晶体管的源/漏延伸控制
CN107039506B (zh) * 2010-12-03 2020-09-11 联华电子日本株式会社 对改进型晶体管的源/漏延伸控制
CN105679712A (zh) * 2015-12-31 2016-06-15 上海华虹宏力半导体制造有限公司 Sonos器件的工艺方法

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US5767557A (en) 1998-06-16
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KR960026938A (ko) 1996-07-22
DE19544945A1 (de) 1996-06-13
TW304301B (zh) 1997-05-01

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