JPH01147829A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法

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Publication number
JPH01147829A
JPH01147829A JP62307010A JP30701087A JPH01147829A JP H01147829 A JPH01147829 A JP H01147829A JP 62307010 A JP62307010 A JP 62307010A JP 30701087 A JP30701087 A JP 30701087A JP H01147829 A JPH01147829 A JP H01147829A
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JP
Japan
Prior art keywords
layer
diffusion
impurity
gate insulating
upper wiring
Prior art date
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Pending
Application number
JP62307010A
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English (en)
Inventor
Hideki Shibata
英毅 柴田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
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Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=17963929&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=JPH01147829(A) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP62307010A priority Critical patent/JPH01147829A/ja
Priority to KR1019880015348A priority patent/KR930000607B1/ko
Priority to EP00100837A priority patent/EP1011129A3/en
Priority to EP88311511A priority patent/EP0328819A3/en
Publication of JPH01147829A publication Critical patent/JPH01147829A/ja
Priority to US08/425,234 priority patent/US5814541A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H01L21/2652—Through-implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2252—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
    • H01L21/2253—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase by ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 ［発明の目的］ （産業上の利用分野） 本発明は、半導体基体と上層配線層との直接接触（Ｂｕ
ｒｉｅｄ　ＣｏｎｔａｃｔまたはＤｉｒｅｃｔ　Ｃｏｎ
ｔａｃｔ）を用いる半導体装置の製造方法に関する。
〈従来の技術） 従来のベリドコンタクト技術の一例を第３図に示す。即
ちこのコンタクトの形成方法としては、第３図（ａ）の
如く半導体基板１上に素子間分離領域２．ゲート絶縁ｒ
ＩＡ３を形成後、第３図（ｂ）の如くコンタクト部分の
み化学薬品を用いてエツチング除去してコンタクト孔５
を形成し、その後多結晶シリコン層４を堆積し、不純物
拡散層６を形成するための拡散法として、第３図（ｃ）
の如＜ＰＯＣＪＩ　３による液体源拡散法を用いていた
。
（発明が解決しようとする問題点） 従来技術の問題点としては、第４図に符号ａで示される
ように拡散層６どうじが近づき、フィールドパンチスル
ー特性の劣化があった。即ち、高濃度のＰＯＣＪ１３拡
散により、多結晶シリコン層４からシリコン基板内１ヘ
リンが拡散するために、例えば９００℃、４０分の拡散
でも、拡散深さが０．６μｍにもおよび（第５図参照）
、フィールドパンチスルー特性を著しく劣化させるばか
りか、素子のＭ細化の妨げになっていた。
本発明は、上記実情に鑑みてなされたもので、半導体基
板中への不純物拡散長を極力抑制し、素子の微細化を実
現できる半導体装置の製造方法を提供するものである。
［発明の構成］ （問題点を解決するための手段） 本発明は、第１導電型半導体基体上に素子間分離領域で
隔離された素子領域を形成する工程、及び前記素子領域
にゲート絶縁膜を形成する工程と、前記ゲート絶縁膜に
対してレジストにより前記半導体基体と上層配線層との
直接接触を得るための領域にコレクト孔を開口する工程
と、１ｉｉＪ記コンタクト孔から第２導電型の第１の不
純物をイオン注入し、その後に前記コンタクト孔及びゲ
ート絶縁膜上に形成される前記上層配線層へ導入される
第２導電型の第２の不純物の前記半導体基板内への拡ｌ
ｉｋを抑制するための工程と、前記上層配線層を前記コ
ンタクト孔及びゲート絶縁膜上に堆積し前記上層配線層
に前記第２導電型の第２の不純物を導入する工程とを具
備したことを特徴とする。
即ち本発明は、半導体基体と逆タイプの不純物、例えば
Ａｓイオン注入を行ない、これにより得られる層が、そ
の後形成される上層配線層例えば多結晶シリコン膜堆積
後のＰＯＣＪ！　３拡散による不純物の拡散を抑制し、
浅い拡散深さを実現するものである。
（実施例） 以下図面を参照して本発明の詳細な説明する。第１図は
同実施例の工程フローを示すもので、Ｎタイプコンタク
トの場合である。まず第１図（ａ＞に示す如くＰタイプ
の半導体基板１上に（ウェル構造の場合はＰウェル上に
）素子間分離領域２を形成する６次にこの領域２で隔離
された素子領域上にゲート酸化膜３を１００〜１５０人
形成した後、堆積前処理を行なわないか、或いは弗化水
素酸を含まない化学薬品で処理後、低圧化学的気相成長
法（以下ＬＰＣＶＤ法）によりゲート酸化膜保護用の第
１の多結晶シリコン層７を約１０００人堆積する。その
後フォトレジスト８を用いてベリドコンタクト領域５を
開孔し、即ちフォトマスクを用いて選択的にフォトレジ
スト８を除去した後、反応性イオンエツチング及びＮｌ
ｌ、　Ｆ液を用いて半導体基板１が露出するまでエツチ
ングする。それからＡｓイオン注入を加速電圧４０ｋｅ
Ｖ　、ドーズ量Ｉ　Ｘ　１０１５ａｎ−２の条件で行な
い、コンタクト孔５内にドーピング９を行なう。その後
第１図（ｃ）の如く第２の多結晶シリコン膜１０を、０
濃度をｐｐｎ＋オーダーにコントロールしたＬＰＧＶＤ
炉を用いて約３０００人堆積し、ＰＯＣｊ３液体源を用
いて多結晶シリコン層１ｏ、Ｓｉ基板】中へドーピング
する。この時、Ａｓ拡散層９がＰの拡散を抑制する様に
働くため、拡散層９′でのＰの分布はＡｓ分布の内側に
くる（第２図参照）。
尚、上記Ａｓイオン注入は、第２の多結晶シリコンＷＡ
１０の堆積（この時は５００人程反り薄膜にするとよい
）後に行なってもかまわない。この場合は、上記Ａｓイ
オン注入は、第２の多結晶シリコンｖ１０とシリコン基
板１との間の自然酸化膜の破壊の役割りもあわせもつ、
また第１図ではゲート酸化膜保護用の多結晶シリコン層
７を用いたが、これは必ずしも必要なものではない。
以上説明した実施例によれば、多結晶シリコン屑１０か
ら基板１中への不純物拡散長をＡｓとＰとの相互作用に
より極めて浅くすることができ（第２図参照）、従って
フィールドバンチスルー特性を大幅に向上でき、また素
子の微細化には適した構造が実現できる。
［発明の効果］ 以上説明した如く本発明によれば、Ｌ層配線！ｒ！Ｊ（
実施例の多結晶シリコン１０）から半導体基体中への不
純物拡散長を極めて浅くできるから、バンチスルー特性
を大幅に向上でき、また素子のｍ細化に適した構造が実
現できるものである。
【図面の簡単な説明】
第１図は本発明の一実施例の工程図、第２図は同工程で
得られる拡散層の特性図、第３図は従来のベリドコンタ
クトの工程図、第４図は同ｉｔ来法の問題点を示す断面
図、第５図は上記従来法で得られる拡散層の特性図であ
る。 １・・・半導体基板、２・・・素子量分ＭｆＰＡ、３・
・・ゲート絶縁膜、５・・・コンタクト孔、７・・・第
１の導電膜（多結晶シリコン）、８・・・フォトレジス
ト膜、９・・・イオン注入により形成された浅い不純物
（Ａｓ）拡散層、９′・・・不純物Ａｓ、Ｐによる拡散
層、１０・・・第２の導電Ｍ（多結晶シリコン）。 出願人代理人　弁理士　鈴　江　武　彦−１゜ 第３図 ｇ４図 差玖表″ｆｇ号秒刀で（μｍ） 第５ｒＡ

Claims (5)

    【特許請求の範囲】
  1. （１）第１導電型半導体基体上に素子間分離領域で隔離
    された素子領域を形成する工程、及び前記素子領域にゲ
    ート絶縁膜を形成する工程と、前記ゲート絶縁膜に対し
    てレジストにより前記半導体基体と上層配線層との直接
    接触を得るための領域にコンタクト孔を開口する工程と
    、前記コンタクト孔から第２導電型の第１の不純物をイ
    オン注入し、その後に前記コンタクト孔及びゲート絶縁
    膜上に形成される前記上層配線層へ導入される第２導電
    型の第２の不純物の前記半導体基板内への拡散を抑制す
    るための工程と、前記上層配線層を前記コンタクト孔及
    びゲート絶縁膜上に堆積し前記上層配線層に前記第２導
    電型の第２の不純物を導入する工程とを具備したことを
    特徴とする半導体装置の製造方法。
  2. （２）前記第１、第２の不純物が各々Ａｓ、Ｐであるこ
    とを特徴とする特許請求の範囲第１項に記載の半導体装
    置の製造方法。
  3. （３）前記ゲート絶縁層と前記上層配線層との間に前記
    ゲート絶縁膜の保護用導電層を設ける工程を具備するこ
    とを特徴とする特許請求の範囲第１項に記載の半導体装
    置の製造方法。
  4. （４）前記上層配線層及びゲート絶縁膜保護用導電層が
    低圧化学的気相成長法により堆積された多結晶シリコン
    であることを特徴とする特許請求の範囲第３項に記載の
    半導体装置の製造方法。
  5. （５）前記Ａｓのイオン注入を前記上層配線層堆積後に
    前記コンタクト孔内の前記半導体基体付近に行なうこと
    を特徴とする特許請求の範囲第２項に記載の半導体装置
    の製造方法。
JP62307010A 1987-12-04 1987-12-04 半導体装置の製造方法 Pending JPH01147829A (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP62307010A JPH01147829A (ja) 1987-12-04 1987-12-04 半導体装置の製造方法
KR1019880015348A KR930000607B1 (ko) 1987-12-04 1988-11-22 반도체장치의 제조방법
EP00100837A EP1011129A3 (en) 1987-12-04 1988-12-05 Method for manufacturing semiconductor device
EP88311511A EP0328819A3 (en) 1987-12-04 1988-12-05 Making of doped regions using phosphorus and arsenic
US08/425,234 US5814541A (en) 1987-12-04 1995-04-18 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62307010A JPH01147829A (ja) 1987-12-04 1987-12-04 半導体装置の製造方法

Publications (1)

Publication Number Publication Date
JPH01147829A true JPH01147829A (ja) 1989-06-09

Family

ID=17963929

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62307010A Pending JPH01147829A (ja) 1987-12-04 1987-12-04 半導体装置の製造方法

Country Status (4)

Country Link
US (1) US5814541A (ja)
EP (2) EP0328819A3 (ja)
JP (1) JPH01147829A (ja)
KR (1) KR930000607B1 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006339655A (ja) * 2005-06-03 2006-12-14 Magnachip Semiconductor Ltd イメージセンサのピクセル縮小のためのコンタクト構造及びその製造方法

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5047357A (en) * 1989-02-03 1991-09-10 Texas Instruments Incorporated Method for forming emitters in a BiCMOS process
US5096840A (en) * 1990-08-15 1992-03-17 At&T Bell Laboratories Method of making a polysilicon emitter bipolar transistor
JP3144000B2 (ja) * 1990-11-28 2001-03-07 セイコーエプソン株式会社 半導体装置およびその製造方法
US6180494B1 (en) * 1999-03-11 2001-01-30 Micron Technology, Inc. Integrated circuitry, methods of fabricating integrated circuitry, methods of forming local interconnects, and methods of forming conductive lines
KR100440078B1 (ko) * 1999-12-28 2004-07-15 주식회사 하이닉스반도체 반도체소자의 제조방법
JP2003031797A (ja) * 2001-07-12 2003-01-31 Mitsubishi Electric Corp 半導体装置およびその製造方法
US6750482B2 (en) 2002-04-30 2004-06-15 Rf Micro Devices, Inc. Highly conductive semiconductor layer having two or more impurities
US20040121524A1 (en) * 2002-12-20 2004-06-24 Micron Technology, Inc. Apparatus and method for controlling diffusion
US7297617B2 (en) * 2003-04-22 2007-11-20 Micron Technology, Inc. Method for controlling diffusion in semiconductor regions
US8110469B2 (en) 2005-08-30 2012-02-07 Micron Technology, Inc. Graded dielectric layers
US9976437B2 (en) 2006-08-15 2018-05-22 United Technologies Corporation Epicyclic gear train
US8753243B2 (en) 2006-08-15 2014-06-17 United Technologies Corporation Ring gear mounting arrangement with oil scavenge scheme
CN102315121A (zh) * 2010-07-02 2012-01-11 上海镭芯微电子有限公司 高频晶体管的制造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51135362A (en) * 1975-05-19 1976-11-24 Matsushita Electronics Corp Method of manufacturing silicon semiconductor element
JPS61137369A (ja) * 1984-12-10 1986-06-25 Hitachi Ltd 半導体装置の製造方法
JPS62193118A (ja) * 1986-02-19 1987-08-25 Sanyo Electric Co Ltd 半導体装置の製造方法

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5327372A (en) * 1976-08-27 1978-03-14 Hitachi Ltd Production of s emiconductor device
JPS53147473A (en) * 1977-05-27 1978-12-22 Mitsubishi Electric Corp Production of mis type semiconductor device
US4333099A (en) * 1978-02-27 1982-06-01 Rca Corporation Use of silicide to bridge unwanted polycrystalline silicon P-N junction
JPS5519857A (en) * 1978-07-28 1980-02-12 Nec Corp Semiconductor
GB2056168A (en) * 1979-08-01 1981-03-11 Gen Instrument Corp Method of fabricating P-N junction with high breakdown voltage
US4276688A (en) * 1980-01-21 1981-07-07 Rca Corporation Method for forming buried contact complementary MOS devices
JPS5736844A (en) * 1980-08-15 1982-02-27 Hitachi Ltd Semiconductor device
JPS5787174A (en) * 1980-11-20 1982-05-31 Seiko Epson Corp Semiconductor integrated circuit device
US4374700A (en) * 1981-05-29 1983-02-22 Texas Instruments Incorporated Method of manufacturing silicide contacts for CMOS devices
JPS592191A (ja) * 1982-06-29 1984-01-07 Fujitsu Ltd 手書き日本語文の認識処理方式
JPS59135767A (ja) * 1983-01-24 1984-08-04 Hitachi Ltd 半導体装置とその製造方法
JPS6063961A (ja) * 1983-08-30 1985-04-12 Fujitsu Ltd 半導体装置の製造方法
JPS60132373A (ja) * 1983-12-20 1985-07-15 Toshiba Corp 半導体装置の製造方法
US4666557A (en) * 1984-12-10 1987-05-19 Ncr Corporation Method for forming channel stops in vertical semiconductor surfaces
JPS6212125A (ja) * 1985-07-10 1987-01-21 Fujitsu Ltd 半導体装置の製造方法
JPS6237967A (ja) * 1985-08-12 1987-02-18 Sony Corp 半導体装置の製造方法
JPH0732192B2 (ja) * 1987-05-26 1995-04-10 日本電気株式会社 半導体装置の製造方法
JPH03109736A (ja) * 1989-09-25 1991-05-09 Sony Corp 半導体装置の製造方法
EP0430166A3 (en) * 1989-12-01 1993-05-12 Seiko Instruments Inc. Method of doping impurity into semiconductor films and patterned semiconductor strip
US5376577A (en) * 1994-06-30 1994-12-27 Micron Semiconductor, Inc. Method of forming a low resistive current path between a buried contact and a diffusion region
US5525552A (en) * 1995-06-08 1996-06-11 Taiwan Semiconductor Manufacturing Company Method for fabricating a MOSFET device with a buried contact
US5536683A (en) * 1995-06-15 1996-07-16 United Microelectronics Corporation Method for interconnecting semiconductor devices
US5554549A (en) * 1995-07-03 1996-09-10 Taiwan Semiconductor Manufacturing Company Ltd. Salicide process for FETs

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51135362A (en) * 1975-05-19 1976-11-24 Matsushita Electronics Corp Method of manufacturing silicon semiconductor element
JPS61137369A (ja) * 1984-12-10 1986-06-25 Hitachi Ltd 半導体装置の製造方法
JPS62193118A (ja) * 1986-02-19 1987-08-25 Sanyo Electric Co Ltd 半導体装置の製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006339655A (ja) * 2005-06-03 2006-12-14 Magnachip Semiconductor Ltd イメージセンサのピクセル縮小のためのコンタクト構造及びその製造方法

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