GB2056168A - Method of fabricating P-N junction with high breakdown voltage - Google Patents

Method of fabricating P-N junction with high breakdown voltage Download PDF

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GB2056168A
GB2056168A GB8012509A GB8012509A GB2056168A GB 2056168 A GB2056168 A GB 2056168A GB 8012509 A GB8012509 A GB 8012509A GB 8012509 A GB8012509 A GB 8012509A GB 2056168 A GB2056168 A GB 2056168A
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substrate
layer
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concentration
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General Instrument Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H01L21/2652Through-implantation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/36Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material

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Abstract

A layer with a gradual impurity concentration profile but with its extent largely determined by a slow differing impurity (which produces an abrupt profile) is produced by introducing the slow differing impurity into a first zone and a second faster A diffusing impurity of the same conductivity type into a second zone and merging the two zones. Ions of the first impurity (arsenic) are implanted in the substrate, to form zone 10 at a first depth 12 using a given acceleration energy, followed by heating to partially diffuse the implanted ions to form zone 10'. Ions of the second impurity (phosphorous) are implanted in the substrate, using the same acceleration energy to form zone 14 at a greater depth 16 in the substrate than the first zone 10. The first zone 10 has a substantially greater impurity concentration than the second zone 14. The first and second impurities are diffused by heating the substrate to cause the layers 10, 14 to merge to form a single impurity layer composed of both the first and second impurities. The resultant impurity layer is substantially immune to subsequent heating fabrication steps and has a relatively gradual distribution profile such that the formed P-N junction has a relatively high breakdown voltage. <IMAGE>

Description

SPECIFICATION Method of fabricating P-N junction with high breakdown voltage The present invention relates to a method for fabricating a semiconductor device and, more particularly, to a method for fabricating a P-N junction in a substrate which is substantially immune to heat applied in subsequent fabrication steps and which has a relatively high breakdown voltage.
One of the basic techniques used in the fabrication of semiconductor devices is the formation of a P-N junction. Various methods of creating a P-N junction in a substrate are known.
For example, starting with a P-type silicon substrate, it is known to distribute, either by ion implantation or other doping techniques, an Ntype impurity into the substrate to change the conductivity of the substrate within the boundaries of the distribution area. By appropriate selection of the impurity and by regulating the concentration and configuration of the distributed impurity layer, the electrical characteristics of the resulting P-N junction can be adjusted, within limits.
A semiconductor device will normally undergo fabrication process steps after the creation of the P-N junction which will affect the concentration and configuration of the impurity layer and, thus, the electrical characteristics of the P-N junction.
For instance, subsequent heating steps taking place above the diffusion temperature of the distributed impurity tend to cause diffusion of the distribute##d impurity, spreading and reducing the concentration of the impurity layer and causing a migration of the P-N junction. The degree of alteration of the distributed impurity layer depends upon the concentration of the distributed impurity, the diffusion coefficient thereof, and the parameters of the subsequent heating steps. It is, therefore, necessary to take this alteration of the distributed impurity layer, caused by the subsequent heating processing steps, into account when determining the nature of the original distribution.
Certain impurities, such as arsenic or antimony, have relatively low diffusion coefficients and thus substantial diffusion thereof will take place only at relatively high temperatures (1 1000C).
Subsequent heating fabrication steps, which normally take place at a temperature (9500C) lower than the diffusion temperature of these impurities, will therefore have little effect on a distributed impurity layer thereof. For this reason, impurities with relatively low diffusion coefficients are desirable for use in forming P-N junctions because once same are distributed into a layer of the desired concentration and configuration, same are relatively immune to alteration by subsequent fabrication steps.
However, impurities with low diffusion coefficients tend to form a layer with a distribution profile having a relatively abrupt periphery or boundary. A layer with a relatively abrupt periphery or boundary results in a P-N junction having a relatively low breakdown voltage. Thus, there is a trade-off between the electrical characteristics of the junction formed and the resistance thereof to subsequent heating fabrication steps. If one wishes to accurately control the characteristics of the P-N junction, then one does so at the cost of a high breakdown voltage.
On the other hand, there are certain impurities, such as phosphorous, which have a higher diffusion coefficient and thus require lower temperatures to obtain substantial diffusion. Such impurities will distribute into a layer with a diffusion profile having a relatively gradual periphery or boundary, but the layer will be affected to a much greater extent by subsequent heating fabrication steps. Thus, while it is desirable to have a layer with a distribution profile having a relatively gradual periphery or boundary because same results in a relatively high breakdown voltage, when such impurities are utilized, it is extremely difficult to accurately control the characteristics of the P-N junction because of the relatively high effect which the subsequent heating fabrication steps have on the concentration and configuration of the impurity layer.Therefore, with impurities such as phosphorous, one must give up a substantial degree of control over the concentration and configuration of the impurity layer in order to achieve a relatively high breakdown voltage.
The most desirable situation would be to utilize an impurity which can be distributed into a layer having a relatively gradual periphery or boundary, thereby resulting in a P-N junction with a relatively high breakdown voltage and, at the same time, has a low diffusion coefficient, such that subsequent heating fabrication steps have relatively little effect on the concentration and configuration of the impurity layer. However, the lower the diffusion coefficient, the more abrupt the periphery of the distributed layer. There is, therefore, always a trade-off between the electrical characteristics of the junction and the ability to control the concentration and configuration of the impurity layer. In fabricating the semiconductor, one must choose one characteristic to the detriment of the other.
It is, therefore, a prime object of the present invention to provide a method for fabricating a P-N junction in a semiconductor device, wherein a high breakdown voltage can be obtained without sacrificing the ability to control the impurity concentration and the junction depth.
In accordance with the present invention, ions of a first impurity of a given conductivity determining type and having a relatively low diffusion coefficient are distributed in an area in the substrate to form a first impurity layer. Ions of a second impurity of the same conductivity determining type and having a relatively high diffusion coefficient are distributed in the same area in the substrate to form a second impurity layer. The second impurity layer is distributed more deeply into the substrate than the first impurity layer. The first and second impurities are diffused to merge the first and second layers to form a single impurity layer composed of both the first and second impurities.
The first impurity is chosen to have a relatively low diffusion coefficient because subsequent heating fabrication steps will have little effect on the distribution profile thereof. The second impurity is chosen to have a higher diffusion coefficient, such that the distribution profile of the layer thereof will be relatively gradual. The merged layer, because it is formed of a combination of the two impurities, will therefore be relatively immune to subsequent heating steps, but will result in a junction with a high breakdown voltage.
The impurity concentration of the first impurity layer is controlled to be significantly higher than the impurity concentration of the second impurity layer to reduce the tendency of the merged layer to spread during subsequent heating steps. For instance, the concentration of the first impurity layer may be two orders of magnitude higher than the concentration of the second impurity layer.
The second impurity layer is formed at a greater depth than the first impurity layer. By forming the second impurity layer at a greater depth than the first impurity layer, when the first and second layers are merged, the portion of the merged layer near the periphery or boundary thereof will be composed of a relatively high percentage of the second impurity. Thus, the single impurity layer will have a relatively gradual distribution at the boundary thereof and, at the same time, because of the higher concentration of the first impurity in the body of the layer, the configuration thereof will be substantially immune to alteration by subsequent heating fabrication steps.
Preferably, the first impurity is distributed by implantation and, thereafter, partial diffusion of the implanted ions to form the first impurity layer.
However, the first impurity layer may be formed by other doping methods, such as diffusion, if desired. The second impurity layer is formed by implanting ions of-the second impurity. Once the two impurity layers are formed, the substrate is heated to redistribute and merge the first and second impurities by means of diffusion, such that a single impurity layer composed of both of the impurities results.
When ion implantation techniques are utilized, both impurities are preferably implanted at approximately the same acceleration energy.
However, because the second impurity is selected to have a lower atomic number than the first impurity, the second impurity layer will have a peak concentration at a depth which is greater than the depth of the peak concentration of the first impurity layer. For this reason, implanting at substantially the same acceleration voltage results in the desired intermediate layered configuration.
It is desirable, although not necessary, to penorm the ion implantation steps through a relatively thin oxide layer formed on the surface of the substrate. The relatively thin oxide layer is virtually transparent to the ions being implanted, but prevents damage to the surface of the substrate which may be caused by implantation at high acceleration energies.
To the accomplishment of the above and to such other objects as may hereinafter appear, the present invention relates to a method for fabricating a P-N junction having a relatively high breakdown voltage, as described in the following specification and recited in the annexed claims, taken together with the accompanying drawings, wherein like numerals refer to like parts, and in which:: Fig. 1 is a graphical representation illustrating the difference between a relatively abrupt concentration profile and a relatively gradual concentration profile; Fig. 2 is a graphical representation illustrating the breakdown voltages resulting from the concentration profiles shown in Fig. 1; Fig. 3 is a graphical representation of the distribution curves of the first and second impurities within the substrate prior to the diffusion step; Fig. 4 is a graphical representation of the impurity concentration curve after the diffusion step; Fig. 5 is a cross-sectional view of a substrate with an ion implantation mask thereon; Fig. 6 is a cross-sectional view of a substrate after implantation of the first impurity; Fig. 7 is a cross-sectional view of a substrate after partial diffusion of the first impurity.
Fig. 8 is a cross-sectional view of a substrate after implantation of the second impurity; and Fig. 9 is a cross-sectional view of a substrate after diffusion of the first and second impurities to form a single impurity layer.
Figure 1 illustrates the difference between an impurity layer which has a gradual or non-abrupt periphery or boundary and, thus, has a gradual distribution profile curve and an impurity layer which has an abrupt periphery or boundary and, thus, a steep distribution profile curve. The abscissa in Fig. 1 represents the depth from the surface of a P-type substrate and the ordinate represents the concentration of an impurity (P or N) which is distributed below the surface of the substrate. The solid line curve illustrates an impurity layer with a relatively gradual periphery or boundary. The dashed line curve illustrates an impurity layer with a relatively abrupt periphery or boundary.
Fig. 2 graphically illustrates the breakdown voltages which result from P-N junctions formed from impurity layers having the characteristics of the curves illustrated in Fig. 1. In this figure, the abscissa represents the breakdown voltage and the ordinate represents the magnitude of current flow across the P-N junction. The solid line curve in Fig. 2 corresponds to the electrical characteristics of a P-N junction formed with an impurity layer having a relatively gradual periphery or boundary, such as is illustrated in solid in Fig. 1.
The dashed-line curve in Fig. 2 represents the electrical characteristics of a P-N junction formed from an impurity layer having a relatively abrupt border or periphery, as is illustrated in the dashed-line curve in Fig. 1. It is clear from Fig. 2 that a junction with a higher breakdown voltage results from the use of an impurity layer with a relatively gradual distribution profile curve.
Fig. 3 graphically illustrates the distribution profile curves of the first and second impurity layers at an intermediate point in the process of the present invention, prior to merging of the impurity layers. In Fig. 3, the abscissa represents the depth from the surface of a P-type substrate and the ordinate represents the concentration of the N-type impurities distributed therein. The curve 10 represents the distribution profile of the first impurity, after same is implanted into the substrate, but before same is partially diffused.
The vertical line 12 which bisects curve 10 represents the depth from the surface of the substrate of the peak of profile curve 10. Dashed line curve 10' represents the distribution profile of the first impurity after the distribution thereof is complete, that is, after the implanted ions have been partially diffused in an intermediate diffusion step. It should be noted that the intermediate diffusion step causes the distribution profile curve 10 to spread out to a degree determined by the parameters of the intermediate diffusion step.
Curve 14 represents the distribution profile of the second impurity after the same is implanted into the substrate. Vertical line 16, which bisects curve 14, represents the peak of the distribution curve of the second impurity. Line 16 is further away from the surface of the substrate than is line 12, indicating that the peak of the distribution curve of the second impurity is deeper into the substrate than the peak of the distribution curve of the first impurity. In other words, the second impurity layer is situated at a location deeper within the substrate than the first impurity layer. In addition, Fig. 3 illustrates the fact that the second impurity layer has an impurity concentration which is substantially less than the concentration of the first impurity layer.
After the first and second impurity layers are formed within the substrate, the substrate is heated to diffuse the first and second impurities, causing the first and second impurity layers to merge into a single impurity layer, the distribution profile curve of which is illustrated by curve 1 8 in Fig. 4. The abscissa in Fig. 4 represents the depth from the surface of the P-type substrate, whereas the ordinate represents the concentration of the combined N-type impurities. As illustrated in Fig.
4, after the diffusion step merging the first and second layers, the layers completely lose their individual identities and form a single impurity layer of N-type impurities having a relatively gradual concentration profile curve.
The configuration of the distribution profile curve 18 of the merged impurity layer, and particularly of the gradual boundary thereof, is due in large part to the molecular characteristics of the second impurity, that is, the relatively high diffusion coefficient of the second impurity and the fact that the second impurity can be implanted more deeply into the substrate than the first. On the other hand, the relative insensitivity of the configuration of the merged layer to subsequent heating steps is due in large part to the molecular characteristics of the first impurity, that is, the relatively low diffusion coefficient thereof and the fact that the first impurity is distributed in a substantially greater concentration than the second impurity.
Figs. 5 through to 9 illustrate the process steps by which the method of the present invention is implemented. As shown in Fig. 5, the P-type silicon substrate 20 has a surface 22 upon which an ion implantation mask 24 is formed. Ion implantation mask 24 may comprise silicon dioxide or other similar material. Mask 24 is formed in a conventional manner.
A layer of silicon dioxide is grown or deposited on surface 22 of substrate 20 with a thickness of approximately 5000 Angstroms. A layer of photresist (not shown) is then formed on the surface of the silicon dioxide layer 24.
A mask is placed on top of the layer of photoresist. The mask is transparent at all portions thereof, except for the portion thereof above the area in the substrate where the P-N junction is to be formed. The assembly is then exposed to light and developed. The non-exposed portions of the photo-resist layer and underlying silicon dioxide layer 24, are etched to expose the substrate surface 22 above the areas where the P-N junction is to be formed. Thereafter, a relatively thin oxide layer 26, approximately 200 Angstroms thick, is grown on the exposed surface 22 of substrate 20 such that the assembly appears as illustrated in Fig. 5.
It should be noted that silicon dioxide, when in a layer approximately 5000 Angstroms thick, is opaque to the implantation of ions at low energies. However, when in a relatively thin layer of approximately 200 Angstroms thick, the silicon dioxide is relatively transparent to the implantation of ions. Thus, when the assembly is exposed to the ions during the implantation process, the thick oxide portions of layer 24 will prevent the ions from being implanted into the substrate, whereas the relatively thin oxide layer 26 will permit implantation of the ions in the substrate beneath same. The relatively thin oxide layer 26 is used in the implantation areas to prevent damage to the substrate surface 22 which often occurs when ions are implanted at relatively high acceleration energies.
Fig. 6 illustrates the substrate as it appears after implantation of the first impurity. The first impurity is selected to have a relatively high atomic number and a relatively low diffusion coefficient, thus requiring a relatively high temperature to obtain substantial diffusion thereof. Preferably, arsenic or antimony ions are selected for the first impurity. Arsenic, for instance, has an atomic number of 33 and requires a temperature of approximately 11 000C in order to obtain substantial diffusion. Since the subsequent processing steps will take place at a somewhat lower temperature, approximately 9500C, same will have little effect on the location of the implanted arsenic ions.
It is preferable to implant the arsenic ions as deeply as possible and, thus, the ion implanter is set near its maximum acceleration energy, approximately 100 Kev. However, lower energies may also be used. The typical implant dose is approximately 5.0 x 1 0'5/Cm2, which will result in an arsenic ion concentration of approximately 5 x 1 O'9/Cm3. The result of the arsenic implant is a layer of implanted arsenic ions 28 formed below the thin oxide layer 26.
If the arsenic ions have been introduced by implantation, as is preferable, the arsenic layer 28 is then partially diffused into the silicon substrate 20 under either N2 or 02/N2 ambient or O2 ambient, at temperatures typically in the neighborhood of 1 000C. The time for this partial diffusion step is relatively short. When the partial diffusion step is completed, the diffused arsenic layer 28' appears as illustrated in Fig. 7.
It is also possible to dope the substrate with ions of the first impurity by conventional diffusion methods. If this option is chosen, the diffusion of the arsenic ions takes place during doping and no separate partial diffusion step is required.
Phosphorous ions are now implanted through the same thin oxide layer 26 at the maximum energy of the ion implanter, approximately 100 Kev., but at a substantially lower dose than the arsenic implant. Preferably, the resulting phosphorous concentration is approximately two orders of magnitude lower than the implanted arsenic concentration. A typical phosphorous implant dose of 5.0 x 1 0'3/Cm2 is preferable which will result in a phosphorous concentration of approximately 5 x 1 0'7/Cm3 in the substrate.
At the same acceleration energy as was used for the arsenic implant, the phosphorous will be implanted into a greater depth below the surface 22 of the silicon substrate because phosphorous has a lower atomic number (15) than arsenic.
Thus, the implanted phosphorous layer 30 will be deeper into the substrate than the implanted arsenic layer 28. After the phosphorous implant, the assembly appears as illustrated in Fig. 8.
Following the phosphorous implant, the assembly is subjected to diffusion conditions at temperatures approximately equal to the diffusion temperature of the first impurity, that is, approximately 1 1000C, in an oxidizing ambient for a predetermined time. It is also possible to carry out a part of this diffusion step in a nitrogen ambient or ambient formed of a combination of oxygen and nitrogen. The result of this heating step is that the arsenic layer 28' and the phosphorous layer 30 merger into a single N-type layer 32 of both arsenic and phosphorous ions. the diffusion time is determined by the final junction depth desired, taking into consideration the concentration doses of the implanted ions. Many suitable combinations of times and temperatures for diffusion can be utilized. After diffusion, the assembly appears as illustrated in Fig. 9.
Subsequent to the formation of the P-N junction, the assembly will be subjected to a variety of additional processing steps. Some of these subsequent processing steps will involve heating the assembly, but these heating steps usually take place around 9500C and, thus, will have little effect on the concentration or configuration of merged layer 32 because of the low diffusion coefficient and high concentration of the arsenic ions. Merged layer 32, however, has a relatively gradual concentration profile curve, that is, relatively gradual periphery or border, due to the more deeply implanted phosphorous ions.
It will now be appreciated that the present invention relates to a method of fabricating a P-N junction in a substrate which has a relatively high breakdown voltage, but which enables the manufacturer to accurately control the characteristics of the P-N junction. This result is achieved by implanting a relatively high concentration of a first impurity with a high atomic number and low diffusion coefficient to form a first impurity layer, implanting a lower concentration of a second impurity having a lower atomic number and a higher diffusion coefficient to form a second layer deeper than the first and heating the substrate to diffuse the distributed impurities to cause the layers to merge into a single layer of both the first and second impurities. In this manner, the merged layer has the attribute of the first impurity, that is, gives the manufacturer the ability to accurately control the concentration and configuration of the layer, as well as the attribute of the second impurity, that is, a relatively gradual distribution profile.

Claims (43)

1. A method for forming an impurity layer having a relatively gradual impurity distribution profile in a substrate, the method being characterized by the steps of: distributing ions of a first impurity (As) of a given conductivity determining type and having a relatively low diffusion coefficient in the substrate (20) to form a first impurity layer (28) therein having a peak impurity concentration at a first depth (12); distributing ions of a second impurity (Ph) of said given conductivity determining type and having a relatively high diffusion coefficient in the substrate (20) to form a second impurity layer (30) therein having a peak impurity concentration at a second depth (16); and diffusing the first and second impurities (As, Ph) to cause said first and second layers (28,30) to merge to form a single impurity layer (32) composed of both of said first and second impurities (As, Ph).
2. The method of Claim 1, characterized in that said second depth (1 6) is greater than said first depth (12).
3. The method of Claim 1, characterized in that the step of distributing the first impurity (As) comprises the step of distributing the first impurity (As) at a first concentration (10) and wherein the step of distributing the second impurity (Ph) comprises the step, of distributing the second impurity at a second concentration (14) and wherein said first concentration (10) is higher than said second concentration (14).
4. The method of Claim 3, characterized in that said first concentration (10) is approximately two orders of magnitude higher than said second concentration (14).
5. The method of any of Claims 1-4, characterized in that said first impurity (As) has a first atomic number and said second impurity (Ph) has a second atomic number and wherein said first (12) and second (16) depths are a functionn, at least in part, of said first and second atomic numbers.
6. The method of Claim 5, characterized in that said first atomic number is greater than said second atomic number.
7. The method of any of Claims 1-6, characterized in that the step of diffusing comprises the step of heating the substrate (20) to a temperature sufficient to cause substantial diffusion of said first impurity (As).
8. The method of Claim 7, characterized in that said temperature is equal to or higher than the temperature sufficient to cause substantial diffusion of said second impurity (Ph).
9. The method of Claim 8, characterized in that said temperature is higher than the temperature sufficient to cause substantial diffusion of said second impurity (Ph).
10. The method of any of Claims 1-9, characterized in that the step of diffusing further comprises the step of regulating the heating time to control the configuration of said single impurity layer (32).
1 The method of any of Claims 1-10, characterized in that the step of distributing said first impurity (As) comprises the step of implanting ions of said first impurity (As) comprises the step of implanting ions of said first impurity (As) into said substrate (20).
12. The method of Claim 1 1, characterized in that the step of implanting comprises the steps of forming an oxide layer (24) on the surface of the substrate and implanting said ions through said oxide layer (24).
13. The method of Claim 12, characterised in that the step of distributing said first impurity (As) further comprises the step of heating the substrate (20) to partially diffuse said ions of said first impurity (As) after said implantation.
14. The method of any of Claims 1-13, characterized in that the step of distributing said first impurity (As) comprises the step of diffusing ions of the first impurity (As) into the substrate (20).
15. The method of any of Claims 1-14, characterized in that the step of distributing said second impurity (Ph) comprises the step of implanting ions of said second impurity (Ph) into said substrate (20).
16. The method of any of Claims 1-15, characterized in that said first impurity (As) is arsenic.
17. The method of any of Claims 1-15, characterized in that said first impurity is antimony.
18. The method of any of Claims 1-17, characterized in that said second impurity (Ph) is phosphorous.
19. The method of any of Claims 118, characterized in that the step of distributing said first impurity (As) comprises the step of distributing said first impurity (As) with a dose of approximately 5 x 1 015/Cm2.
20. The method of any of Claims 1-19, characterized in that the step of distributing said second impurity (Ph) comprises the step of distributing said second impurity with a dose of approximately 5 x 10'3/Cm2.
21. The method of any of Claims 1-20, characterized in that the step of distributing said second impurity comprises the step of distributing said second impurity with a concentration of approximately 5 x 10'7/Cm3.
22. The method of any of Claims 1-21, characterized in that said steps of implanting said first and second impurities (As,Ph) are performed at approximately the same acceleration energy.
23. The method of Claim 22, characterized in that said acceleration energy is approximately 100 Kev.
24. The method of any of Claims 1-23, characterized in that the step of heating comprises the step of heating the substrate (20) to approximately 1 1000C in an oxidizing atmosphere.
25. The method of any of Claims 1-23, characterized in that the step of heating comprises the step of heating the substrate (20) to approximately 1 000C in a nitrogen atmosphere.
26. The method of any of Claims 1-23, characterized in that the step of heating comprises the step of heating the substrate (20) to approximately 11000C in an oxygen and nitrogen atmosphere.
27. A method of forming a P-N junction having a relatively high breakdown voltage in a substrate, said method being characterized by the steps of: implanting ions of a first impurity (As) of a given conductivity determining type and having a given atomic number and a given diffusion coefficient, at a given acceleration energy, into the substrate (20) of opposite conductivity type to form a first layer (28) having a distribution peak at a first depth (12); implanting ions of a second impurity (Ph) of said given conductivity determining type and having a higher atomic number and diffusion coefficient than said first impurity (As), at approximately said given acceleration energy, into the substrate (20) to form a second layer (30) having a distribution peak at a second depth (16); and heating the substrate (20) to cause substantial diffusion of the ions so as to merge the first and second layers (28,30) to form a single conductivity type impurity layer (32) formed of both impurities (As, Ph), having a relatively gradual diffusion profile.
28. The method of Claim 27, characterized in that the step of implanting ions of a first impurity (As) comprises the step of regulating the concentration of the implanted ions of the first impurity (As).
29. The method of Claims 27 or 28, characterized in that the step of implanting ions of a second impurity (Ph) comprises the step of regulating the concentration of the implanted ions of the second impurity (Ph).
30. The method of any of Claims 27-29, characterized in that the concentration of implanted ions of the first impurity (As) is higher than the concentration of implanted ions of the second impurity (Ph).
31. The method of any of Claims 27-30, characterized in that the dose of implanted ions of the first type (As) is approximately 5 x 1015/Cm2.
32. The method of any of Claims 27-31, characterized in that the dose of implanted ions of the second impurity (Ph) is approximately -5 x 1013/Cm2.
33. The method of any of Claims 27-32, characterized in that said first impurity (As) is arsenic.
34. The method of any of Claims 27-33, characterized in that said first impurity is antimony.
35. The method of any of Claims 27-34, characterized in that said second impurity is phosphorous.
36. The method of any of Claims 27-35, characterized in that said given conductivity determining type is N-type.
37. The method of any of Claims 27-36, characterized in that the step of implanting said first impurity (As) further comprises the step of heating the substrate (20) to partially diffuse said first impurity (As).
38. A method of fabricating a P-N junction having a relatively high breakdown voltage; the method being characterized by the steps of: masking the surface (22) of the substrate (20) except at locations on the substrate surface above the areas where the P-N junction is to be formed; growing a relatively thin oxide layer (26) on the surface at the unmasked locations; implanting ions of a first impurity (As) at a given acceleration energy having a relatively low diffusion coefficient and a relatively high atomic number, through said oxide layer (26), into the substrate (20) to create a first impurity layer (28);; implanting ions of a second impurity (Ph) at said given acceleration energy having relatively high diffusion coefficient and relatively low atomic number, through the oxide layer (26), into the substrate (20) to create a second impurity layer (30); and heating the substrate (20) to diffuse the first (As) and second (Ph) impurities to merge the first (28) and second (30) impurity layers to form a single impurity layer (32) of both of said first (As) and second (Ph) impurities having a relatively gradual impurity profile.
39. The method of Claim 38, characterized in that said oxide layer (26) is approximately 200 Angstroms thick.
40. The method of Claims 38 or 39, characterized in that the step of masking comprises the steps of forming a thick oxide layer (24) approximately 5000 Angstroms thick and removing the part of said thick oxide layer (26) at locations above which the P-N junction will be formed.
41. The method of any of Claims 38-40, characterized in that the concentration of said first impurity (As) in said first impurity layer (28) is greater than the concentration of said second impurity (Ph) in said second impurity layer (30).
42. The method of any of Claims 38-41, characterized in that said first layer (28) is implanted to a depth less than the depth of said second layer (30).
43. The method of any of Claims 38-42, characterized in that the step of heating comprises the step of heating the substrate (20) to the diffusion temperature of said first impurity (As).
GB8012509A 1979-08-01 1980-04-16 Method of fabricating P-N junction with high breakdown voltage Withdrawn GB2056168A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4369072A (en) * 1981-01-22 1983-01-18 International Business Machines Corp. Method for forming IGFET devices having improved drain voltage characteristics
EP0328819A2 (en) * 1987-12-04 1989-08-23 Kabushiki Kaisha Toshiba Making of doped regions using phosphorus and arsenic
US4889820A (en) * 1988-03-14 1989-12-26 Fujitsu Limited Method of producing a semiconductor device

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60117681A (en) * 1983-11-29 1985-06-25 Mitsubishi Electric Corp Semiconductor device
JPH063798B2 (en) * 1985-02-06 1994-01-12 日本電気株式会社 Method for manufacturing semiconductor device
DE69739486D1 (en) * 1996-03-27 2009-08-20 Cree Inc METHOD OF MANUFACTURING A SEMICONDUCTOR ARRANGEMENT WITH A SiC LAYER

Family Cites Families (4)

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Publication number Priority date Publication date Assignee Title
IT956828B (en) * 1971-08-05 1973-10-10 Rca Corp PROCESS FOR OBTAINING DIFFUSED SEMICONDUCTOR REGIO NI WITH A REDUCED NUMBER OF CRYSTAL DEFECTS
IL40189A0 (en) * 1971-09-09 1972-10-29 Trusty J Method and apparatus for preparing and analyzing serum samples
DE2304647C2 (en) * 1973-01-31 1984-06-28 Siemens AG, 1000 Berlin und 8000 München Method for producing a doped zone in a semiconductor body
JPS543479A (en) * 1977-06-09 1979-01-11 Toshiba Corp Semiconductor device and its manufacture

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4369072A (en) * 1981-01-22 1983-01-18 International Business Machines Corp. Method for forming IGFET devices having improved drain voltage characteristics
EP0328819A2 (en) * 1987-12-04 1989-08-23 Kabushiki Kaisha Toshiba Making of doped regions using phosphorus and arsenic
EP0328819A3 (en) * 1987-12-04 1989-11-29 Kabushiki Kaisha Toshiba Making of doped regions using phosphorus and arsenic
US4889820A (en) * 1988-03-14 1989-12-26 Fujitsu Limited Method of producing a semiconductor device

Also Published As

Publication number Publication date
IT1145411B (en) 1986-11-05
FR2462780A1 (en) 1981-02-13
DE3028185A1 (en) 1981-02-26
JPS5623742A (en) 1981-03-06
IT8049389A0 (en) 1980-07-31
FR2462780B1 (en) 1983-02-18

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