KR890011027A - 반도체장치의 제조방법 - Google Patents

반도체장치의 제조방법 Download PDF

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KR890011027A
KR890011027A KR1019880015348A KR880015348A KR890011027A KR 890011027 A KR890011027 A KR 890011027A KR 1019880015348 A KR1019880015348 A KR 1019880015348A KR 880015348 A KR880015348 A KR 880015348A KR 890011027 A KR890011027 A KR 890011027A
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introducing
arsenic
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semiconductor device
phosphorus
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KR930000607B1 (ko
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히데키 시바타
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아오이 죠이치
가부시키가이샤 도시바
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H01L21/2652—Through-implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2252—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
    • H01L21/2253—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase by ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

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  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Computer Hardware Design (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Ceramic Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)

Abstract

내용 없음

Description

반도체장치의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제3도(a) 내지 제3도(c)는 본 발명의 1실시예에 관한 반도체장치의 제조방법을 도시해 놓은 공정단면도.
제4도는 본 발명 반도체장치의 제조방법에 따른 불순물 농도의 분포를 도시해 놓은 특성도.
제5도(a) 내지 제5도(d)는 본 발명의 다른 실시예에 관한 반도체장치의 제조방법을 도시해 놓은 공정단면도이다.

Claims (11)

  1. 실리콘기판의 미리 정해진 부분에 비소를 도입시키는 공정을 거친 다음, 상기 미리 정해진 부분에다 인을 도입시키는 공정을 거치도록 해서, 상기 비소와 인을 함유한 N형 불순물영역을 실리콘기판내에 형성시키도록 된 것을 특징으로 하는 반도체장치의 제조방법.
  2. 제 1 항에 있어서, 상기 비소를 도입시키는 공정이 이온주입으로 이루어지고, 상기 인을 도입시키는 공정이 확산으로 이루어진 것을 특징으로 하는 반도체장치의 제조방법.
  3. 제 1 항에 있어서, 상기 비소를 도입시키는 공정과 상기 인을 도입시키는 공정이 각각 미리 정해진 가속전압에서 이온주입으로 이루어지도록 된 것을 특징으로 하는 반도체 장치의 제조방법.
  4. 제 3 항에 있어서, 사기 비소 및 인이온주입의 미리 정해진 가속전압이, 비소농도의 피이크 깊이보다 인농도의 피이크깊이가 얕아지도록 선택되어진 것을 특징으로 하는 반도체장치의 제조방법.
  5. 실리콘기판(11)상에 절연막(13)을 형성시키는 공정과, 이 실리콘기판(11)의 미리 정해진 부분상에 상기 절연막(13)을 선택적으로 제거하는 공정, 상기 미리 정해진 부분에 비소를 도입시키는 공정, 상기 절연막(13)을 선택적으로 제거하는 공정에 이어 적어도 미리 정해진 부분에 다결정실리콘(20)을 형성시키는 공정 및, 상기 비소를 도입시키는 공정에 이어 상기 미리 정해진 부분에 인을 도입시키는 공정으로 이루어진 것을 특징으로 하는 반도체장치의 제조방법.
  6. 제 5 항에 있어서, 상기 비소를 도입시키는 공정이 상기 다결정실리콘층(20)을 형성시키는 공정이전에 이루어지도록 된 것을 특징으로 하는 반도체장치의 제조방법.
  7. 제 5 항에 있어서, 상기 비소를 도입시키는 공정이 상기 다결정실리콘층(20)을 형성시키는 공정 다음에 이루어지도록 된 것을 특징으로 하는 반도체장치의 제조방법.
  8. 제 5 항에 있어서, 상기 인을 도입시키는 공정이 상기 다결정실리콘층(20)을 형성시키는 공정 다음에 이루어지도록 된 것을 특징으로 하는 반도체장치의 제조방법.
  9. 실리콘기판(21)상에 절연막(23)을 형성시키는 공정과, 이 절연막(23)상에 게이트전극(24)을 형성시키는 공정, 이 게이트전극(24)에 인접한 실리콘기판(21)의 미리 정해진 부분으로 비소를 도입시키는 공정 및, 상기 비소를 도입시키는 공정다음에 미리 정해진 부분으로 인을 도입시키는 공정으로 이루어진 것을 특징으로 하는 반도체장치의 제조방법.
  10. 제 9 항에 있어서, 상기 비소를 도입시키는 공정과 상기 인을 도입시키는 공정이, 각각 미리 정해진 가속전압에서 이온주입으로 이루어지도록 된 것을 특징으로 하는 반도체장치의 제조방법.
  11. 제10항에 있어서, 상기 비소 및 인이온주입의 미리 정해진 가속전압이, 비소농도의 피이크깊이보다 인농도의 피이크가 얕아지도록 선택되어진 것을 특징으로 하는 반도체장치의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019880015348A 1987-12-04 1988-11-22 반도체장치의 제조방법 KR930000607B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP62-307010 1987-12-04
JP87-307010 1987-12-04
JP62307010A JPH01147829A (ja) 1987-12-04 1987-12-04 半導体装置の製造方法

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KR890011027A true KR890011027A (ko) 1989-08-12
KR930000607B1 KR930000607B1 (ko) 1993-01-25

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US (1) US5814541A (ko)
EP (2) EP1011129A3 (ko)
JP (1) JPH01147829A (ko)
KR (1) KR930000607B1 (ko)

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Publication number Publication date
EP1011129A2 (en) 2000-06-21
EP0328819A2 (en) 1989-08-23
EP1011129A3 (en) 2000-12-06
EP0328819A3 (en) 1989-11-29
US5814541A (en) 1998-09-29
JPH01147829A (ja) 1989-06-09
KR930000607B1 (ko) 1993-01-25

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