KR890003381B1 - Forming method of thin n-type area - Google Patents
Forming method of thin n-type areaInfo
- Publication number
- KR890003381B1 KR890003381B1 KR8405080A KR840005080A KR890003381B1 KR 890003381 B1 KR890003381 B1 KR 890003381B1 KR 8405080 A KR8405080 A KR 8405080A KR 840005080 A KR840005080 A KR 840005080A KR 890003381 B1 KR890003381 B1 KR 890003381B1
- Authority
- KR
- South Korea
- Prior art keywords
- thin
- forming method
- type area
- film
- substrate
- Prior art date
Links
- 239000000758 substrate Substances 0.000 abstract 2
- 238000009792 diffusion process Methods 0.000 abstract 1
- 238000010438 heat treatment Methods 0.000 abstract 1
- 239000012535 impurity Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
- H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Bipolar Transistors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Photovoltaic Devices (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58159949A JPS6063961A (ja) | 1983-08-30 | 1983-08-30 | 半導体装置の製造方法 |
JP???58-159949 | 1983-08-30 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR850002177A KR850002177A (ko) | 1985-05-06 |
KR890003381B1 true KR890003381B1 (en) | 1989-09-19 |
Family
ID=15704675
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR8405080A KR890003381B1 (en) | 1983-08-30 | 1984-08-22 | Forming method of thin n-type area |
Country Status (5)
Country | Link |
---|---|
US (2) | US4629520A (ko) |
EP (1) | EP0137645B1 (ko) |
JP (1) | JPS6063961A (ko) |
KR (1) | KR890003381B1 (ko) |
DE (1) | DE3484814D1 (ko) |
Families Citing this family (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4682404A (en) * | 1986-10-23 | 1987-07-28 | Ncr Corporation | MOSFET process using implantation through silicon |
IT1197523B (it) * | 1986-10-30 | 1988-11-30 | Sgs Microelettronica Spa | Processo per la fabbricazione di transistori ad effetto di campo a "gate" isolata con giunzioni aventi profondita' estremamente ridotta |
US4740478A (en) * | 1987-01-30 | 1988-04-26 | Motorola Inc. | Integrated circuit method using double implant doping |
JPH01123417A (ja) * | 1987-11-07 | 1989-05-16 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
JPH01147829A (ja) * | 1987-12-04 | 1989-06-09 | Toshiba Corp | 半導体装置の製造方法 |
US5047357A (en) * | 1989-02-03 | 1991-09-10 | Texas Instruments Incorporated | Method for forming emitters in a BiCMOS process |
US4927773A (en) * | 1989-06-05 | 1990-05-22 | Santa Barbara Research Center | Method of minimizing implant-related damage to a group II-VI semiconductor material |
US5296388A (en) * | 1990-07-13 | 1994-03-22 | Matsushita Electric Industrial Co., Ltd. | Fabrication method for semiconductor devices |
SG71664A1 (en) * | 1992-04-29 | 2000-04-18 | Siemens Ag | Method for the production of a contact hole to a doped region |
US5345104A (en) * | 1992-05-15 | 1994-09-06 | Micron Technology, Inc. | Flash memory cell having antimony drain for reduced drain voltage during programming |
IT1256362B (it) * | 1992-08-19 | 1995-12-04 | St Microelectronics Srl | Processo di realizzazione su semiconduttori di regioni impiantate a basso rischio di channeling |
JP3133667B2 (ja) * | 1995-02-23 | 2001-02-13 | 三洋電機株式会社 | スプリットゲート型トランジスタ、スプリットゲート型トランジスタの製造方法、不揮発性半導体メモリ |
DE19511251A1 (de) * | 1995-03-27 | 1996-10-02 | Siemens Ag | Bipolarer Siliziumtransistor |
US5994182A (en) | 1996-01-18 | 1999-11-30 | Micron Technology, Inc. | Method of reducing outdiffusion from a doped three-dimensional polysilicon film into substrate by using angled implants |
JP3075204B2 (ja) * | 1997-02-28 | 2000-08-14 | 日本電気株式会社 | 半導体装置の製造方法 |
US5937299A (en) * | 1997-04-21 | 1999-08-10 | Advanced Micro Devices, Inc. | Method for forming an IGFET with silicide source/drain contacts in close proximity to a gate with sloped sidewalls |
US6011272A (en) * | 1997-12-06 | 2000-01-04 | Advanced Micro Devices, Inc. | Silicided shallow junction formation and structure with high and low breakdown voltages |
US6576521B1 (en) * | 1998-04-07 | 2003-06-10 | Agere Systems Inc. | Method of forming semiconductor device with LDD structure |
US6331468B1 (en) * | 1998-05-11 | 2001-12-18 | Lsi Logic Corporation | Formation of integrated circuit structure using one or more silicon layers for implantation and out-diffusion in formation of defect-free source/drain regions and also for subsequent formation of silicon nitride spacers |
DE10058031B4 (de) * | 2000-11-23 | 2007-11-22 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zur Bildung leicht dotierter Halogebiete und Erweiterungsgebiete in einem Halbleiterbauelement |
US6682992B2 (en) * | 2002-05-15 | 2004-01-27 | International Business Machines Corporation | Method of controlling grain size in a polysilicon layer and in semiconductor devices having polysilicon structures |
US20040121524A1 (en) | 2002-12-20 | 2004-06-24 | Micron Technology, Inc. | Apparatus and method for controlling diffusion |
US7297617B2 (en) * | 2003-04-22 | 2007-11-20 | Micron Technology, Inc. | Method for controlling diffusion in semiconductor regions |
US20060234484A1 (en) * | 2005-04-14 | 2006-10-19 | International Business Machines Corporation | Method and structure for ion implantation by ion scattering |
US8110469B2 (en) | 2005-08-30 | 2012-02-07 | Micron Technology, Inc. | Graded dielectric layers |
US10164043B2 (en) * | 2012-01-11 | 2018-12-25 | Infineon Technologies Ag | Semiconductor diode and method for forming a semiconductor diode |
US9306010B2 (en) | 2012-03-14 | 2016-04-05 | Infineon Technologies Ag | Semiconductor arrangement |
DE102018111213A1 (de) | 2018-05-09 | 2019-11-14 | Infineon Technologies Ag | Halbleitervorrichtung und Herstellungsverfahren |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4364166A (en) * | 1979-03-01 | 1982-12-21 | International Business Machines Corporation | Semiconductor integrated circuit interconnections |
JPS55153365A (en) * | 1979-05-17 | 1980-11-29 | Toshiba Corp | Manufacturing method of semiconductor device |
JPS6043656B2 (ja) * | 1979-06-06 | 1985-09-30 | 株式会社東芝 | 半導体装置の製造方法 |
DE2946963A1 (de) * | 1979-11-21 | 1981-06-04 | Siemens AG, 1000 Berlin und 8000 München | Schnelle bipolare transistoren |
NL8006827A (nl) * | 1980-12-17 | 1982-07-16 | Philips Nv | Werkwijze voor het vervaardigen van een halfgeleiderinrichting. |
US4419810A (en) * | 1981-12-30 | 1983-12-13 | International Business Machines Corporation | Self-aligned field effect transistor process |
JPS5919354A (ja) * | 1982-07-24 | 1984-01-31 | Fujitsu Ltd | 半導体装置 |
JPS5946065A (ja) * | 1982-09-09 | 1984-03-15 | Toshiba Corp | 半導体装置の製造方法 |
US4542580A (en) * | 1983-02-14 | 1985-09-24 | Prime Computer, Inc. | Method of fabricating n-type silicon regions and associated contacts |
-
1983
- 1983-08-30 JP JP58159949A patent/JPS6063961A/ja active Pending
-
1984
- 1984-08-14 US US06/640,577 patent/US4629520A/en not_active Expired - Fee Related
- 1984-08-14 DE DE8484305531T patent/DE3484814D1/de not_active Expired - Fee Related
- 1984-08-14 EP EP84305531A patent/EP0137645B1/en not_active Expired - Lifetime
- 1984-08-22 KR KR8405080A patent/KR890003381B1/ko not_active IP Right Cessation
-
1988
- 1988-05-17 US US07/195,468 patent/US4875085A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
DE3484814D1 (de) | 1991-08-22 |
JPS6063961A (ja) | 1985-04-12 |
KR850002177A (ko) | 1985-05-06 |
EP0137645B1 (en) | 1991-07-17 |
EP0137645A2 (en) | 1985-04-17 |
EP0137645A3 (en) | 1987-10-07 |
US4629520A (en) | 1986-12-16 |
US4875085A (en) | 1989-10-17 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
G160 | Decision to publish patent application | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 19970822 Year of fee payment: 9 |
|
LAPS | Lapse due to unpaid annual fee |