KR950021768A - 실드 확산 접합을 갖는 전계 효과 트랜지스터 - Google Patents

실드 확산 접합을 갖는 전계 효과 트랜지스터 Download PDF

Info

Publication number
KR950021768A
KR950021768A KR1019940031631A KR19940031631A KR950021768A KR 950021768 A KR950021768 A KR 950021768A KR 1019940031631 A KR1019940031631 A KR 1019940031631A KR 19940031631 A KR19940031631 A KR 19940031631A KR 950021768 A KR950021768 A KR 950021768A
Authority
KR
South Korea
Prior art keywords
layer
dielectric layer
field effect
effect transistor
landing pad
Prior art date
Application number
KR1019940031631A
Other languages
English (en)
Other versions
KR0184616B1 (en
Inventor
화 리 쿠오
팅 리우 춘
리우 루이첸
Original Assignee
리챠드 디. 라우만
에이 티 앤드 티 코포레이션
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 리챠드 디. 라우만, 에이 티 앤드 티 코포레이션 filed Critical 리챠드 디. 라우만
Publication of KR950021768A publication Critical patent/KR950021768A/ko
Application granted granted Critical
Publication of KR0184616B1 publication Critical patent/KR0184616B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

전계효과 트랜지스터는 이온주입된 실리사이드층(7)과 확산마스크로 작용하는 전도확산 장벽패드층(9)으로 제조된다. 실리사이드층(7)으로부터의 도펀트는 셀로우 소스/드레인 영역(21)을 형성하도록 기판(1)으로 확산된다.

Description

실드확산 접합을 갖는 전계효과 트랜지스터
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제4도는 본 발명에 따른 여러 제조단계에서의 장치의 일부분에 대한 단면도.

Claims (11)

  1. 기판(1)상에 전계효과 트랜지스터를 제조하는 방법에 있어서, 필드산화물 영역(5)사이에 절연상부층(35)를 갖는 상기 전계효과 트랜지스터의 게이트전극(3)을 형성하는 단계와, 상기 기판(1)상에 놓여 상기 게이트전극(3)을 덮으면 스택랜딩 패드층(9,11)을 형성하는 제1실리사이드층(7)및 전도확산 방지층(9)을 증착하는 단계와, 제1유전체층(13)을 증착하는 단계와, 레지스트층(15)을 형성하는 단게와, 상기 유전체층(13)의 선택부분을 노출하도록 상기 레지스트(15)를 패턴화하는 단계, 및 패턴화된 유전체층을 형성하기 위하여, 상기 스택랜딩 패드층(9,11)의 부분을 노출하도록 상기 유전체층(13)의 상기 노출부분을 제거하는 단계를 구비하는 전계효과 트랜지스터 제조방법.
  2. 제1항에 있어서, 상기 패턴화된 유전체층(13)상에 유전체 스페이서(17)를 형성하는 단계를 더 구비하는 전계효과 트랜지스터 제조방법.
  3. 제1항에 있어서, 상기 패턴화된 랜딩패드(9,11)와 제1실리사이드(7)상에 제2유전체층(19)을 증착하는 단계, 및 상기 패턴화된 랜딩 패드층(9,11)의 부분을 노출하도록 상기 제2유전체층(19)을 패턴화하는 단계를 더 구비하는 전계효과 트랜지스터 제조방법.
  4. 제1항에 있어서, 상기 제1실리사이드층(7)을 도펀트로 도핑하는 단계를 더 구비하는 전계효과 트랜지스터 제조방법.
  5. 제4항에 있어서, 상기 트랜지스터의 소스/드레인 영역(21)을 형성하도록 상기 제1실리사이드층(7)으로부터 상기 기판(1)으로 적어도 일부의 상기 도펀트를 이동하게 하는 가열(heating)단계를 더 구비하는 전계효과 트랜지스터 제조방법.
  6. 제5항에 있어서, 상기 도펀트는 n-타입 및 p-타입 도펀트인, 전계효과 트랜지스터 제조방법.
  7. 제6항에 있어서, 상기 n-타입 및 p-타입 도펀트는 붕소 및 인(phosphorous)인, 전계효과 트랜지스터 제조방법.
  8. 제1항에 있어서, 상기 랜딩 패드층(9,11)은 기본적으로 전도 질화물로 구성되는 전계효과 트랜지스터 제조방법.
  9. 제8항에 있어서, 상기 전도질화물은 티타늄 질화물인, 전계효과 트랜지스터 제조방법.
  10. 제2항에 있어서, 상기 스택 랜딩패드(9,11)층을 에칭하는 에칭 마스크로서 상기 패턴화된 유전체층(13)을 사용하는 단계를 더 구비하는 전계효과 트랜지스터 제조방법.
  11. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019940031631A 1993-12-01 1994-11-29 Method of making field effect transistor with a sealed diffusion junction KR0184616B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/160,600 US5420058A (en) 1993-12-01 1993-12-01 Method of making field effect transistor with a sealed diffusion junction
US160,600 1993-12-01

Publications (2)

Publication Number Publication Date
KR950021768A true KR950021768A (ko) 1995-07-26
KR0184616B1 KR0184616B1 (en) 1999-03-20

Family

ID=22577547

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940031631A KR0184616B1 (en) 1993-12-01 1994-11-29 Method of making field effect transistor with a sealed diffusion junction

Country Status (6)

Country Link
US (1) US5420058A (ko)
EP (1) EP0656645B1 (ko)
JP (1) JP2944903B2 (ko)
KR (1) KR0184616B1 (ko)
DE (1) DE69428329T2 (ko)
TW (1) TW268141B (ko)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR950011982B1 (ko) * 1992-11-06 1995-10-13 현대전자산업주식회사 전도물질 패드를 갖는 반도체 접속장치 및 그 제조방법
US5945738A (en) * 1994-05-31 1999-08-31 Stmicroelectronics, Inc. Dual landing pad structure in an integrated circuit
US5633196A (en) * 1994-05-31 1997-05-27 Sgs-Thomson Microelectronics, Inc. Method of forming a barrier and landing pad structure in an integrated circuit
US5956615A (en) * 1994-05-31 1999-09-21 Stmicroelectronics, Inc. Method of forming a metal contact to landing pad structure in an integrated circuit
US5702979A (en) * 1994-05-31 1997-12-30 Sgs-Thomson Microelectronics, Inc. Method of forming a landing pad structure in an integrated circuit
US5705427A (en) * 1994-12-22 1998-01-06 Sgs-Thomson Microelectronics, Inc. Method of forming a landing pad structure in an integrated circuit
JP4156044B2 (ja) * 1994-12-22 2008-09-24 エスティーマイクロエレクトロニクス，インコーポレイテッド 集積回路におけるランディングパッド構成体の製造方法
US5686761A (en) * 1995-06-06 1997-11-11 Advanced Micro Devices, Inc. Production worthy interconnect process for deep sub-half micrometer back-end-of-line technology
US5719071A (en) * 1995-12-22 1998-02-17 Sgs-Thomson Microelectronics, Inc. Method of forming a landing pad sturcture in an integrated circuit
US6080644A (en) 1998-02-06 2000-06-27 Burr-Brown Corporation Complementary bipolar/CMOS epitaxial structure and process
US6274464B2 (en) 1998-02-06 2001-08-14 Texas Instruments Incorporated Epitaxial cleaning process using HCL and N-type dopant gas to reduce defect density and auto doping effects
US6096599A (en) * 1998-11-06 2000-08-01 Advanced Micro Devices, Inc. Formation of junctions by diffusion from a doped film into and through a silicide during silicidation
US6380040B1 (en) 1999-08-02 2002-04-30 Advanced Micro Devices, Inc. Prevention of dopant out-diffusion during silicidation and junction formation

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4788160A (en) * 1987-03-31 1988-11-29 Texas Instruments Incorporated Process for formation of shallow silicided junctions
US4764481A (en) * 1987-08-24 1988-08-16 Delco Electronics Corporation Grown side-wall silicided source/drain self-align CMOS fabrication process
US4922311A (en) * 1987-12-04 1990-05-01 American Telephone And Telegraph Company Folded extended window field effect transistor
US4844776A (en) * 1987-12-04 1989-07-04 American Telephone And Telegraph Company, At&T Bell Laboratories Method for making folded extended window field effect transistor
US4923822A (en) * 1989-05-22 1990-05-08 Hewlett-Packard Company Method of fabricating a semiconductor device by capping a conductive layer with a nitride layer
US5206187A (en) * 1991-08-30 1993-04-27 Micron Technology, Inc. Method of processing semiconductor wafers using a contact etch stop

Also Published As

Publication number Publication date
JP2944903B2 (ja) 1999-09-06
EP0656645A3 (en) 1996-07-31
TW268141B (ko) 1996-01-11
EP0656645A2 (en) 1995-06-07
US5420058A (en) 1995-05-30
DE69428329T2 (de) 2002-07-04
KR0184616B1 (en) 1999-03-20
JPH07202201A (ja) 1995-08-04
DE69428329D1 (de) 2001-10-25
EP0656645B1 (en) 2001-09-19

Similar Documents

Publication Publication Date Title
US4717683A (en) CMOS process
KR960042942A (ko) 반도체 디바이스 형성 방법
US5607881A (en) Method of reducing buried contact resistance in SRAM
EP0356202B1 (en) Mosfet and fabrication method
KR950021768A (ko) 실드 확산 접합을 갖는 전계 효과 트랜지스터
CA1198227A (en) Single mask diffusion process
US5504023A (en) Method for fabricating semiconductor devices with localized pocket implantation
US5668051A (en) Method of forming poly plug to reduce buried contact series resistance
KR970077166A (ko) 반도체 기판에 삼중웰을 형성하는 방법
JPH03112136A (ja) 半導体装置の製造方法
US5547903A (en) Method of elimination of junction punchthrough leakage via buried sidewall isolation
EP0732746B1 (en) Method of manufacturing a complementary bipolar transistor integrated circuit
KR0162512B1 (ko) 반도체 집적회로 장치
KR930005508B1 (ko) 반도체장치 및 그 제조방법
KR930005106A (ko) 마스크롬의 제조방법
KR970053502A (ko) 반도체 장치 및 그 제조 방법
KR920010962A (ko) 반도체 디바이스 및 그 형성 방법
KR0167664B1 (ko) 반도체소자 제조방법
KR910001876A (ko) 반도체 장치 제조방법
KR100274979B1 (ko) 반도체소자내의콘택트형성방법
KR100648240B1 (ko) 반도체 소자의 자기정렬 콘택 형성방법
JP2836575B2 (ja) 半導体装置とその製造方法
KR100309645B1 (ko) 반도체장치 및 그 제조방법
KR960012262B1 (ko) 모스(mos) 트랜지스터 제조방법
KR0165355B1 (ko) 반도체 장치의 제조 방법

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20011203

Year of fee payment: 4

LAPS Lapse due to unpaid annual fee