TW268141B - - Google Patents
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- TW268141B TW268141B TW083110281A TW83110281A TW268141B TW 268141 B TW268141 B TW 268141B TW 083110281 A TW083110281 A TW 083110281A TW 83110281 A TW83110281 A TW 83110281A TW 268141 B TW268141 B TW 268141B
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- 229910021332 silicide Inorganic materials 0.000 claims description 18
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 17
- 238000000034 method Methods 0.000 claims description 16
- 238000005530 etching Methods 0.000 claims description 12
- 230000005669 field effect Effects 0.000 claims description 11
- 238000009792 diffusion process Methods 0.000 claims description 9
- 239000002019 doping agent Substances 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 238000007493 shaping process Methods 0.000 claims description 6
- 230000004888 barrier function Effects 0.000 claims description 5
- 239000013078 crystal Substances 0.000 claims description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 2
- 229910052770 Uranium Inorganic materials 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 229910052796 boron Inorganic materials 0.000 claims description 2
- 230000003628 erosive effect Effects 0.000 claims description 2
- 238000010438 heat treatment Methods 0.000 claims description 2
- 229910052698 phosphorus Inorganic materials 0.000 claims description 2
- 239000011574 phosphorus Substances 0.000 claims description 2
- 239000000758 substrate Substances 0.000 claims description 2
- JFALSRSLKYAFGM-UHFFFAOYSA-N uranium(0) Chemical compound [U] JFALSRSLKYAFGM-UHFFFAOYSA-N 0.000 claims description 2
- 238000003307 slaughter Methods 0.000 claims 4
- 150000004767 nitrides Chemical class 0.000 claims 2
- 208000006558 Dental Calculus Diseases 0.000 claims 1
- 241000218033 Hibiscus Species 0.000 claims 1
- 235000005206 Hibiscus Nutrition 0.000 claims 1
- 235000007185 Hibiscus lunariifolius Nutrition 0.000 claims 1
- 240000000233 Melia azedarach Species 0.000 claims 1
- 241000270708 Testudinidae Species 0.000 claims 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical group [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims 1
- 150000001412 amines Chemical class 0.000 claims 1
- 230000002079 cooperative effect Effects 0.000 claims 1
- 230000000694 effects Effects 0.000 claims 1
- 238000009434 installation Methods 0.000 claims 1
- 239000000463 material Substances 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000012856 packing Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000029052 metamorphosis Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 238000001556 precipitation Methods 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 210000003625 skull Anatomy 0.000 description 1
- 239000002689 soil Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
- 238000004804 winding Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
- H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
經濟部中央橾準局員工消费合作社印製 268141 at _B7 _五、發明説明（1 ) 技術背優 本發明一般關於場效電晶體的領域而特別是具有沉澱 護墊的m晶體之領域。 發明背長 正當稹體電路區變得更爲複雜之時，諸如場效電晶» 的組成稹髏電路的各別元件也變得較小且互相貼近°單是 將元件的尺寸縮小並不足以提高電路的複雜性：新的處理 技術及創新的元件亦不可或缺。 一個例子將可說明此論點。一場效電晶體的源BE和汲 區必窬分別實施電連接。通常這是藉由在電晶體上覆上一 電介質層，對電介質層定形以形成一暴露出源/汲面的部 份的窗，然後在該窗上覆上金屬。但是，爲了使元件所用 的基體面稹最小化，源和汲區應儘量小。由閘寬度所決定 的短通道長度爲窗上設置了一最小區隔。也就是，窗必需 相當小且互相貼近，但是關於源/汲區的誤排不可發生於 窗暴露部份的一源及一汲區。 由K. H. Lee, C-Y, Lu及D Yaney所有的美國第 4，844，776 及 4，922，3 1 1 號專利揭示一 窗口所需之排列精密度。這些專利敘述用以製造一元件的 裝置及方法，此元件稱爲褶展窗口場效電晶髖（folded extended window field effect transistor )，而一般 以縮寫表示爲F EWMO S。在一示範實施例中，諸如 T i N的一導電材料層在包括閘電極之上的一絕緣層的tt (請先閲讀背面之注$項再填寫本頁) 裝· 訂 0 本紙張尺度逋用中國國家標準（CNS ) A4规格（210X297公釐） 268141 經濟部中央標準局貝工消费合作社印製 五、發明説明（2 ) 晶體元素被形成後被均厚沉積。當然，WS i 2亦可被採 用。導《材料被定形以形成覆羞至少源/汲區之部份的窗 口墊。假設其在閛《極上不相互接觸則窗α墊可較源/汲 區爲大：其亦可伸展至源/汲®附近的之場氧化區上。改 良之窗口誤排容忍度可因窗口必需暴露較源/汲區大的窗 口墊的部份而獲得。誤排之容忍度亦獏得改善。當電介質 內的窗口被蝕刻時窗口墊當做一鈾刻停止厝因此防止蝕刻 至源/汲面。 摻雜物必需被加入基體以形成源/汲區。此經常經由 離子植入達成。有許多元件特性可藉由形成淺接面而加强 :也就是說，非常淺的源/汲區。由於在離子植入的同時 要維持平順的表面以避免介面粗糙，淺區在製造上有其困 難。在一實施例中，FEWMOS揭示採用一矽化物做爲 窗口墊層材料。源/汲區藉由自離子植入之多晶矽熱導出 而形成。一金屬被沉稹且一矽化物形成。但是，矽化物多 晶矽會導致接面粗糙。 發明概要 依據本發明的一示範實施例，一具有一起落墊的場效 電晶體藉由在場氧化物區之間形成一電晶體的閘電極，沉 稹一第一矽化物層及一作爲擴散屛障層以密封接面的導電 起落墊層而製成。一m介質層接受被沉稹並接著進行光阻 定形以暴霣電介質層的選定部份然後被移去。經定形的電 介質層被用作一蝕刻掩覃以定形導電起落墊及第一矽化物 券-- r * (請先閲讀背面之注意事項再填寫本頁) ： -* Γ 本紙張尺度適用中國國家標準（CNS ) A4规格（210Χ297公釐） 經濟部中央標準局負工消费合作社印製 268141 A7 B7 五、發明説明（3 ) 餍。在一較佳實施例中，電介質間隔在蝕刻前被形成於經 定形的電介質層，電介質層不蘅要被移去，雖然部份被蝕 刻以暴露起落墊層。第一矽化物矽具有一在加熱中擴敝入 基髗以在閘電極和場氧化區之間形成淺接面源/汲區的摻 雜物。元件裝作接著繼績進行。另一電介質層被沉稹窗口 打開其暴露起落墊層之選定部份。起落埜層當作一蝕刻停 止餍。一導電材料被沉稹入窗口內以形成電連接。 圖示之槪要敘述 圚1 — 4爲依照本發明的不同製造階段的場效電晶體 的一部份之剖面圖。 爲求清楚，所描繪的元素並未如尺寸表示。 詳細敘述 本發明將參照一示範實施例被敘述q圖1爲顯示基髖 1，閘電極3，場氧化區5，第一矽化物層7，導電擴散 屛障層9，第二矽化物層1 1，電介質屉1 3，及經定形 光阻層1 5的一剖面圚。層9及J L可被稱_1堆稹Μ蔡埜 J1。閘電極Β在場氧化物區5之間。閘電極3具有閘氧化 物3 1，導電層3 3,絕緣頂層3 5，及電介質側壁3 7 。經定形的蝕阻15暴露覆盖堆積起落墊層之電介質靨 1 3的部份，其將會被移去。 以上所描繪的結構可由热習該項技術之人士運用熟知 材料及热知技術所容易達成。基髅1 一般爲矽而在閘電極 本紙張尺度適用中國國家標率（CNS ) Α4规格（21〇Χ297公釐〉 (請先聞讀背面之注意事項再填寫本頁) .裝. 訂 268141 經濟部中央揉準局貝工消费合作社印裝 A7 B7五、發明説明（4 ) 3內的導《層3 3 —般爲多晶矽。場效電晶髗之閘電極， 以及場氧化物區將可由熟習該技藝藉由俥統的沉稹及定形 技術而容易達成。電介質層1 3，絕緣頂層H，及絕緣 側壁》7 —般爲氧化矽。第一及第二矽化物層由諸如 _ ..... —··.·.—.， — _ --------------- W § i又之赛鼇较化物形.成，其爲經沈積者。贾3 12較 Ti S i2爲儍，Ti S i2 —般藉由將Ti沉稹於S i 上然後使其反應以造成此矽化物。此形成方法導致表面粗 T i n撬一示範選擇。起落墊層當做一擴散屛障以密封接 面。電介質層13—般爲一經沉稹之氧化物。除了以上被 *'' —— 提及之材料亦可被採用：然而必需將諸如蝕刻特性等適當 特性列入考慮。第一矽化物層進一步包含一可被離子植入 的摻雜物。蝕阻一般爲在此蝕阻之敏感性被適當考慮之商 業上可獏得的蝕阻。傳統的石版定形技術可被使用。其中 所描繪的結構可藉由熟知而傳統的處理步驟而形成。 現在定形蝕阻1 5被用作一蝕刻掩罩而電介質層13 的暴露剖份被移去因此將頂層的部份暴露。蝕阻現在以傳 統的技術剝去。若位於伸展至閘電極上的起落埜層間的一 下石空間是所希望的，則一電介質層可如圖2所示被&稹 而服勉m览介質間隔:丄_7。氧化物爲一種方便的電介 質材料。當然，其它方法可被用於形成電介質間隔。具有 間隔1 7的定形電介質.4.3被用作蝕刻及去除堆J*起落墊 —_________—..........— . ..... . - ·'' — -------------- » 9暴露部份的彼刻叛.軍。具有在電介質及起落墊層中隨 所意選擇的乾蝕可由热習該項技藝者所選擇。自第一矽化 (請先閲讀背面之注意事項再填寫本頁) -裝.
.IT 線 本紙張尺度逋用中國國家橾牟（CNS ) A4規格（210X297公釐） 068141 經濟部中央標準局員工消費合作社印製 A7 B7_五、發明説明（5 ) 物層7向外擴散形成源/汲區2 1其所得之結構如圖3所 描繪。 如需要可將剩下的電介質層移去；但是，另一電介質 層1 9 一般被沉積及定形，且此間並無迫切的理由必需在 製造過程中將電介質層13移去。 在前一段中所提到的電介質層19現在被沉稹且蝕阻 屠被形成。蝕阻接著被定形以形成暴露電介質層13的選 擇部份的開口。電介質層13的經暴露部份在堆稹起落墊 層的部份之上其當電介質13被定形時將被暴露。電介質 層的暴露部份現在被移去因而使堆稹起落埜層之部份被暴 露。因爲蝕刻層13及停止於層9上經常有其困難，第二 矽化物層11被使用。在此情況中，堆積窗口墊屠只有兩 層。所得的結構如圖4所示。元件製造現在以傳統程序完 成。例如，金爾被沉装―於暴霡窗口起落整來擠之部份的電 --..... ...... . ............· .· 貧窗P 〇 數種電晶體的好處於此討論。淺接面之構造避免接面 介面粗糙。T i Ν層將接面密封以避免擴散及消除步階聚 琴之問單，否則其可能在屛障材料的沉稹時發生。計算指 出壤積層起落及閘電橱之間的重叠並不會造成明顯的電 象。再者，使用WS i2作爲第一層可省去一掩罩，因爲 經發現磷可防止硼擴散，其分別爲η型及P型摻雜物。 在所敘述的實施例中之改變可由热習技藝者達成，若 由石版定出的介於起落埜厝部份之間的間隔足夠多，間隔 規劃可省略。 本紙張尺度適用中國國家揉準（CNS ) Α4规格（210X297公釐） (請先Μ讀背面之注意事項再填寫本頁) •裝· 訂 線
C
Claims (1)
- 268141 A8 B8 C8 D8 經濟部中央標率局負工消费合作社印製 六、申請專利範圍 —種在一基髗上製造一場效儷晶體的方法包含下 列步蘼： 形成一賅場效電晶體之阑電極於場氧化物α (例如5 )之閜，該閘電極（例如3 )具有一絕緣頂層（例如3 5)； 沉稹一第一矽化物層（例如7 )及一導電擴散屛，陣屠 (例如9)，賅第一矽化物屠（例如7〉及胲屛陣屠（例 如9 >形成堆稹起落蟄屠（例如9，1 1 )，該層在賅基 體上且覆董賅閛電極（例如3): 沉稹一第一Μ介質層（例如13): 形成一鈾阻層（例如15): 對胲蝕阻（例如1 5 )定形以暴露賅電介質屠（例如 13〉之所選揮部份：及 移去胲《介質層（例如1 3 )之暴露部份以暴霣孩堆 稹起落墊層（例如9，1 1〉之部份，賅移去動作形成一 經定形的電介質靨。 如申請專利範圓第1項所述的方法進一步包含以 下步驟： 在該定形電介質層（例如1 3 )上形成一電介質問隔 0 >3/.如申請專利範園第1項所述的方法，包含進一步 的步驟，在胲經定型起落墊（例如9 )及第一矽化物層（ 例如7)上沉稹一第二《介質層（例如19),及 對賅第二電介質層（例如1 9 )定形以暴露陔經定形 (請先閱讀背面之注$項再填寫本頁) 裝· -訂 -il« In Ji · 本紙張尺度適用中鬮8家揉率（CNS >A4規^ ( 210x297公釐） 268141 A8 B8 C8 D8 六、申請專利範園 起落墊暦（例如9，1 1 )的部份。 4/.如申請専利範_第1項所述的方法，包含進一步 的將第一矽化物層（例如7 )摻入摻雜物的步蘼。 I·如申請專利範圏第4項所述的方法，包含進一步 的步蘼，加熱以造成賅摻雜物的至少一些自該第一矽化物 層（例如7 )移向胺基酱（例如1一)以形成賅電晶酱的濂 /汲® (例如2 1 )。 §/.如申請専利範園第5項所述的方法，其中該一摻 雜物爲η型及p型摻雜物。 如申請專利範_第6項所述的方法，其中該η型 及Ρ型摻雜物爲硼及磷。 8/·如申請專利範第1項所述的方法，其中賅起落 墊層（例如9，11)基本上由氮化物組成。 如申繭専利範圓第8項所述的方法，其中賅導電 氮化物爲氮化鈦。 .如申請專利範園第2項所述的方法，包含進一 步的步骤，使用經定形的電介質層（例如1 3 )爲一用以 蝕刻胲堆稹起落墊（例如9，1 1 )層之蝕刻掩單。 本纸張尺度逋用中國國家梂準（CNS > A4洗格（210X297公釐） (請先《讀背面之注$項再填寫本頁) 訂 經濟部中央梯準局負工消费合作社印裝 -J1 - - J— · -10 - 告本件1 申請曰期 83年11月 7曰 案 號 83110281 類 則 (以上各攔由本局填註） 系83110281 專利申妍$明書修正真 民网84年8 η 9 268141 Α4 C4雲靈專利説明書 發明 新型 名稱 中 文 具有密封擴散接面之場效電晶體的製造方法 英 文 Method of making^field effect transistor with a sealed diffusion junction 姓 名 國 籍 華廷· 國軍奇 李劉路 ⑴(2)(3) Lee, Kuo-Hua Liu, Chun-Ting 劉 Liu, Ruichen (1)美國 ⑴ 美國 裝 發明 創作 人 住、居所 (3! 美國賓州雷郡威斯康辛維爾鄉村俱樂部路一三 〇八號 1308 Country Club Road, Wescosville, Lehigh County, Pi 18106, U. S. A. " 美國新澤西卅•桕克萊高地♦廣角大道七十號 70 Grandview Avenue, Berkeley Heights, NJ 07922, U. S, A. 美國新澤西州♦索摩沙特郡•華倫北山路四號 4 Northridge Way, Warren, Somerset County, NJ 07060, l|. S. Ά.' _ 訂 姓 名 (名稱） Π)美國電話電報股份有限公司 AT&T Co「p· 線 經濟部中央楳準扃貝工消费合作社印装 國 籍 三、申請人 住、居所 (事務所） 代表人 姓 名 Π)美國 (1)美國纽約州♦纽約市美州大道三十二號 32 Avenue of the Americas, New York, NY 10013-2412, U.S.A. ⑴皮.汪市德Wilde, P. V. D· 本紙張尺度適用中國國家樣準（CNS ) A4規格（210X297公釐）
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US08/160,600 US5420058A (en) | 1993-12-01 | 1993-12-01 | Method of making field effect transistor with a sealed diffusion junction |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW268141B true TW268141B (zh) | 1996-01-11 |
Family
ID=22577547
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW083110281A TW268141B (zh) | 1993-12-01 | 1994-11-07 |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US5420058A (zh) |
| EP (1) | EP0656645B1 (zh) |
| JP (1) | JP2944903B2 (zh) |
| KR (1) | KR0184616B1 (zh) |
| DE (1) | DE69428329T2 (zh) |
| TW (1) | TW268141B (zh) |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR950011982B1 (ko) * | 1992-11-06 | 1995-10-13 | 현대전자산업주식회사 | 전도물질 패드를 갖는 반도체 접속장치 및 그 제조방법 |
| US5633196A (en) * | 1994-05-31 | 1997-05-27 | Sgs-Thomson Microelectronics, Inc. | Method of forming a barrier and landing pad structure in an integrated circuit |
| US5956615A (en) * | 1994-05-31 | 1999-09-21 | Stmicroelectronics, Inc. | Method of forming a metal contact to landing pad structure in an integrated circuit |
| US5702979A (en) * | 1994-05-31 | 1997-12-30 | Sgs-Thomson Microelectronics, Inc. | Method of forming a landing pad structure in an integrated circuit |
| US5945738A (en) * | 1994-05-31 | 1999-08-31 | Stmicroelectronics, Inc. | Dual landing pad structure in an integrated circuit |
| US5705427A (en) * | 1994-12-22 | 1998-01-06 | Sgs-Thomson Microelectronics, Inc. | Method of forming a landing pad structure in an integrated circuit |
| JP4156044B2 (ja) * | 1994-12-22 | 2008-09-24 | エスティーマイクロエレクトロニクス，インコーポレイテッド | 集積回路におけるランディングパッド構成体の製造方法 |
| US5686761A (en) * | 1995-06-06 | 1997-11-11 | Advanced Micro Devices, Inc. | Production worthy interconnect process for deep sub-half micrometer back-end-of-line technology |
| US5719071A (en) * | 1995-12-22 | 1998-02-17 | Sgs-Thomson Microelectronics, Inc. | Method of forming a landing pad sturcture in an integrated circuit |
| US6080644A (en) | 1998-02-06 | 2000-06-27 | Burr-Brown Corporation | Complementary bipolar/CMOS epitaxial structure and process |
| US6274464B2 (en) | 1998-02-06 | 2001-08-14 | Texas Instruments Incorporated | Epitaxial cleaning process using HCL and N-type dopant gas to reduce defect density and auto doping effects |
| US6096599A (en) * | 1998-11-06 | 2000-08-01 | Advanced Micro Devices, Inc. | Formation of junctions by diffusion from a doped film into and through a silicide during silicidation |
| US6380040B1 (en) | 1999-08-02 | 2002-04-30 | Advanced Micro Devices, Inc. | Prevention of dopant out-diffusion during silicidation and junction formation |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4788160A (en) * | 1987-03-31 | 1988-11-29 | Texas Instruments Incorporated | Process for formation of shallow silicided junctions |
| US4764481A (en) * | 1987-08-24 | 1988-08-16 | Delco Electronics Corporation | Grown side-wall silicided source/drain self-align CMOS fabrication process |
| US4844776A (en) * | 1987-12-04 | 1989-07-04 | American Telephone And Telegraph Company, At&T Bell Laboratories | Method for making folded extended window field effect transistor |
| US4922311A (en) * | 1987-12-04 | 1990-05-01 | American Telephone And Telegraph Company | Folded extended window field effect transistor |
| US4923822A (en) * | 1989-05-22 | 1990-05-08 | Hewlett-Packard Company | Method of fabricating a semiconductor device by capping a conductive layer with a nitride layer |
| US5206187A (en) * | 1991-08-30 | 1993-04-27 | Micron Technology, Inc. | Method of processing semiconductor wafers using a contact etch stop |
-
1993
- 1993-12-01 US US08/160,600 patent/US5420058A/en not_active Expired - Lifetime
-
1994
- 1994-11-07 TW TW083110281A patent/TW268141B/zh not_active IP Right Cessation
- 1994-11-23 DE DE69428329T patent/DE69428329T2/de not_active Expired - Fee Related
- 1994-11-23 EP EP94308646A patent/EP0656645B1/en not_active Expired - Lifetime
- 1994-11-29 KR KR1019940031631A patent/KR0184616B1/ko not_active IP Right Cessation
- 1994-11-30 JP JP6319366A patent/JP2944903B2/ja not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| DE69428329T2 (de) | 2002-07-04 |
| EP0656645A3 (en) | 1996-07-31 |
| KR0184616B1 (en) | 1999-03-20 |
| EP0656645B1 (en) | 2001-09-19 |
| KR950021768A (ko) | 1995-07-26 |
| EP0656645A2 (en) | 1995-06-07 |
| DE69428329D1 (de) | 2001-10-25 |
| JP2944903B2 (ja) | 1999-09-06 |
| US5420058A (en) | 1995-05-30 |
| JPH07202201A (ja) | 1995-08-04 |
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