KR910013542A - 반도체장치의 제조방법 - Google Patents

반도체장치의 제조방법 Download PDF

Info

Publication number
KR910013542A
KR910013542A KR1019900021780A KR900021780A KR910013542A KR 910013542 A KR910013542 A KR 910013542A KR 1019900021780 A KR1019900021780 A KR 1019900021780A KR 900021780 A KR900021780 A KR 900021780A KR 910013542 A KR910013542 A KR 910013542A
Authority
KR
South Korea
Prior art keywords
insulating film
opening
metal layer
laser beam
film
Prior art date
Application number
KR1019900021780A
Other languages
English (en)
Inventor
고이찌 고바야시
Original Assignee
세끼사와 요시
후지쓰 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 세끼사와 요시, 후지쓰 가부시끼가이샤 filed Critical 세끼사와 요시
Publication of KR910013542A publication Critical patent/KR910013542A/ko

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76882Reflowing or applying of pressure to better fill the contact hole
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
    • H01L21/31116Etching inorganic layers by chemical means by dry-etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76808Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/7681Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving one or more buried masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1005Formation and after-treatment of dielectrics
    • H01L2221/101Forming openings in dielectrics
    • H01L2221/1015Forming openings in dielectrics for dual damascene structures
    • H01L2221/1031Dual damascene by forming vias in the via-level dielectric prior to deposition of the trench-level dielectric
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1005Formation and after-treatment of dielectrics
    • H01L2221/101Forming openings in dielectrics
    • H01L2221/1015Forming openings in dielectrics for dual damascene structures
    • H01L2221/1036Dual damascene with different via-level and trench-level dielectrics
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/97Specified etch stop material

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

내용 없음.

Description

반도체장치의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도(a)-(e)는 제1발명에 따른 반도체 장치의 제조방법의 일실시예의 필수적인 단계를 나타내는 일부 절결 단면도,
제2도(a)-(e) 및 제3도(a),(b)는 제2발명에 따른 반도체 장치의 제조방법의 일실시예의 필수적인 단계를 나타내는 일부 절결 단면도.

Claims (24)

  1. 적어도 하나의 하층 절연막 및 하나의 상층 절연막으로 이루어지며, 상기 하층 절연막은 상기 상층 절연막보다 에칭률이 작아서 에칭 스톱퍼의 역할을 하며, 절연막의 에칭률은 최하층 절연막으로 향할수록 점차로 작아지는 복수개의 절연막을 하지층상에 형성하는 단계; 상기 상층 절연막을 에칭하여 제1개구부를 형성하고, 상기 제1개구부에서 상기 하층 절연막을 노출시키는 단계; 상기 제1개구부에서 노출된 상기 하층 절연막을 에칭하여 상기 제1개구부보다 폭이 작은 제2개구부를 형성하고, 상기 제2개구부에서 상기 하지층을 노출시키는 단계; 상기 제2개구부에서 노출된 상기 하지층과 접촉될 수 있도록 상기 제1 및 제2개구부에 금속층을 형성하는 단계 및 상기 금속층에 레이저 빔을 조사하여 상기 제1 및 제2개구부에 금속층을 매몰하고, 매몰된 금속층을 평탄화시키는 단계로 이루어진 반도체장치의 제조방법.
  2. 제1항에 있어서, 상기 복수개의 절연막중 하나는 상기 하지층이 손상되지 않도록 레이저 빔에 관하여 30%이상의 흡수율을 갖는 반도체장치의 제조방법.
  3. 제1항에 있어서, 상기 하지층은 Al, Al 염기화합물 Cu, Cu 염기화합물, 단결정 Si, 다결정 Si 또는 GaAs나 AlGaAs와 같은 화합물 반도체로 이루어진 반도체장치의 제조방법.
  4. 제1항에 있어서, 상기 상층 절연막은 산화 규소막 또는 인(P)을 함유하는 산호 규소막으로 이루어지고, 상기 하층 절연막은 알루미나(Al2O3)로 이루어진 반도체장치의 제조방법.
  5. 제1항에 있어서, 상기 레이저 빔은 엑사이머 레이저 빔으로 이루어진 반도체장치의 제조방법.
  6. 제5항에 있어서, 상기 금속층은 Al, Al 염기 화합물, Cu 또는 Cu 염기 화합물로 이루어진 반도체장치의 제조방법.
  7. 적어도 하나의 제1절연막, 하나의 제2절연막 및 하나의 제3절연막으로 이루어지며, 상기 제2절연막은 상기 제1 및 제3절연막보다 에칭률이 작아서 에칭 스톱퍼 및 차양막의 역할을 하는 복수개의 절연막을 하지층상에 형성하는 단계; 상기 제3절연막을 에칭하여 제1개구부를 형성하고, 상기 제1개구부에서 상기 제2절연막을 노출하는 단계; 상기 제1개구부에서 노출된 상기 제2절연막을 에칭하고 상기 제1절연막을 에칭하여 상기 제1개구부보다 폭이 작은 제2개구부를 형성하고, 상기 제2개구부에서 상기 하지층을 노출시키는 단계; 상기 제2개구부에서 노출된 상기 하지층과 접촉할 수 있도록 상기 제1 및 제2재구부에 금속층을 형성하는 단계 및 상기 금속층에 레이저 빔을 조사하여 상기 금속층을 상기 제1 및 제2개구부에 매몰하고, 매몰된 금속층을 평탄화시키는 단계로 이루어진 반도체장치의 제조방법.
  8. 제7항에 있어서, 상기 제2절연막은 상기 하지층이 손상되지 않도록 레이저 빔에 관하여 30% 이상의 흡수율을 갖는 반도체장치의 제조방법.
  9. 제7항에 있어서, 상기 하지층은 Al, Al 염기화합물, Cu, Cu 염기화합물, 단결정 Si, 다결정 Si 또는 GaAs나 AlGaAs와 같은 화합물 반도체로 이루어진 반도체장치의 제조방법.
  10. 제7항에 있어서, 상기 제1절연막은 산화 규소막 또는 인을 함유하는 산화 규소막으로 이루어지며, 상기 제2절연막은 Al2O3로 이루어지며, 상기 제3절연막은 산화 규소막 또는 인을 함유하는 산화규소막으로 이루어진 반도체장치의 제조방법.
  11. 제7항에 있어서, 상기 레이저 빔은 엑사이며 레이저 빔으로 이루어진 반도체장치의 제조방법.
  12. 제11항에 있어서, 상기 금속층은 Al, Al 염기화합물 Cu 또는 Cu 염기화합물로 이루어진 반도체장치의 제조방법.
  13. 복수개의 절연막의 제1절연막 및 복수개의 절연막의 상기 제1절연막 및 제3절연막 보다 에칭률이 작고 에칭스톱퍼 및 차양막의 역할을 하는 복수개의 절연막의 제2절연막을 하지층상에 차례로 형성되는 단계; 상기 제2절연막을 에칭하여 제1개구부를 형성하고, 상기 제1개구부에서 상기 제1절연막을 노출시키는 단계; 상기 제2절연막 및 상기 제1개구부가 상기 제3절연막으로 덮히도록 상기 제3절연막을 상기 제2절연막상에 형성하는 단계; 상기 제3절연막 및 상기 제1절연막을 에칭하여 상기 제1개구부보다 폭이 큰 제2개구부를 상기 제1개구부상의 상기 제3절연막에 형성하며 또한, 상기 제1개구부와 실질적으로 폭이 같은 제3개구부를 상기 제1절연막에 형성해서, 상기 제3개구부에서 상기 하지층을 노출시키는 단계; 상기 제3개구부에서 노출된 상기 하지층에 접촉할 수 있도록 상기 제1, 제2 및 제3개구부에 금속층을 형성하는 단계 및 상기 금속층에 레이저 빔을 조사하여 상기 제1, 제2 및 제3개구부에 상기 금속층을 매몰하고, 매몰된 금속층을 평탄화시키는 단계로 이루어진 반도체장치의 제조방법.
  14. 제13항에 있어서, 상기 제2절연막은 상기 하지층이 손상되지 않도록 레이저 빔에 관하여 30% 이상의 흡수율을 갖는 반도체장치의 제조방법.
  15. 제13항에 있어서, 상기 하지층은 Al, Al 염기화합물, Cu, Cu 염기화합물, 단결정Si, 다결정 Si 또는 GaAs 나 AlGaAs와 같은 화합물 반도체로 이루어진 반도체장치의 제조방법.
  16. 제13항에 있어서, 상기 제1절연막은 산화 규소막 또는 인을 함유하는 산화 규소막으로 이루어지며, 상기 제2절연막은 Al2O3로 이루어지며, 상기 제3절연막은 산화규소막 또는 인을 함유하는 산화규소막으로 이루어진 반도체장치의 제조방법.
  17. 제13항에 있어서, 상기 레이저 빔은 엑사이며 레이저 빔으로 이루어진 반도체장치의 제조방법.
  18. 제17항에 있어서, 상기 금속층은 Al, Al 염기화합물, Cu 또는 Cu 염기화합물로 이루어진 반도체장치의 제조방법.
  19. 복수개의 절연막의 제1절연막 및 복수개의 절연막의 상기 제1절연막 및 제3절연막 보다 에칭률이 작고 에칭스톱퍼 및 차양막의 역할을 하는 복수개의 절연막의 제2절연막을 하지층상에 차례로 형성되는 단계; 상기 제1 및 제2연막을 에칭하여 제1개구부를 형성하는 단계; 상기 제2절연막 및 상기 제1개구부가 상기 제3절연막으로 덮히도록 상기 제3절연막을 상기 제2절연막상에 형성하는 단계; 상기 제3절연막을 에칭하여 상기 제1개구부보다 폭이 큰 상기 제2개구부를 상기 제1개구부상의 상기 제3절연막에 형성하고 또한, 상기 제1개구부의 상기 제1 및 제2절연막의 측벽상에 측벽 절연막을 형성해서 상기 측벽 절연막에 의해 한정된 개구부에서 상기 하지층을 노출시키는 단계; 상기 측벽 절연막에 의해 한정된 상기 개구부에서 노출된 상기 하지층과 접촉될 수 있도록 상기 제1 및 제2개구부 금속층을 형성하는 단계 및 상기 금속층에 레이저 빔을 조사하여 상기 제1 및 제2개구부에 상기 금속층을 매몰하고, 매몰된 금속층을 평탄화 시키는 단계로 이루어진 반도체장치의 제조방법.
  20. 제19항에 있어서, 상기 제2절연막은 상기 하지층이 손상되지 않도록 레이저 빔에 관하여 30% 이상의 흡수율을 갖는 반도체장치의 제조방법.
  21. 제19항에 있어서, 상기 하지층은 Al, Al 염기화합물, Cu, Cu 염기화합물, 단결정Si, 다결정 Si 또는 GaAs 나 AlGaAs와 같은 화합물 반도체로 이루어진 반도체장치의 제조방법.
  22. 제19항에 있어서, 상기 제1절연막은 산화 규소막 또는 인을 함유한 산화 규소막으로 이루어지며, 상기 제2절연막은 Al2O3로 이루어지며, 상기 제3절연막은 산화 규소막 또는 인을 함유하는 산화 규소막으로 이루어진 반도체장치의 제조방법.
  23. 제19항에 있어서, 상기 레이져 빔은 엑사이며 레이저 빔으로 이루어진 반도체장치의 제조방법.
  24. 제23항에 있어서, 상기 금속층 Al, Al 염기화합물, Cu 또는 Cu 염기화합물인 것을 특징으호 하는 반도체장치의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019900021780A 1989-12-26 1990-12-26 반도체장치의 제조방법 KR910013542A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP1-340971 1989-12-26
JP1340971A JPH03198327A (ja) 1989-12-26 1989-12-26 半導体装置の製造方法

Publications (1)

Publication Number Publication Date
KR910013542A true KR910013542A (ko) 1991-08-08

Family

ID=18342004

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900021780A KR910013542A (ko) 1989-12-26 1990-12-26 반도체장치의 제조방법

Country Status (4)

Country Link
US (1) US5169800A (ko)
EP (1) EP0435187A3 (ko)
JP (1) JPH03198327A (ko)
KR (1) KR910013542A (ko)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2740050B2 (ja) * 1991-03-19 1998-04-15 株式会社東芝 溝埋込み配線形成方法
JP2907599B2 (ja) * 1991-08-26 1999-06-21 シャープ株式会社 配線層の形成方法
JPH05129296A (ja) * 1991-11-05 1993-05-25 Fujitsu Ltd 導電膜の平坦化方法
JPH05160272A (ja) * 1991-12-04 1993-06-25 Nec Corp 半導体装置の製造方法
JP3332456B2 (ja) * 1992-03-24 2002-10-07 株式会社東芝 半導体装置の製造方法及び半導体装置
KR950010041B1 (ko) * 1992-03-28 1995-09-06 현대전자산업주식회사 콘택 홀(contact hole) 구조 및 그 제조방법
JPH06260441A (ja) * 1993-03-03 1994-09-16 Nec Corp 半導体装置の製造方法
DE4400532C1 (de) * 1994-01-11 1995-03-23 Siemens Ag Verfahren zum Herstellen von Flüssigkontakten in Kontaktlöchern
US5635423A (en) * 1994-10-11 1997-06-03 Advanced Micro Devices, Inc. Simplified dual damascene process for multi-level metallization and interconnection structure
US5567329A (en) * 1995-01-27 1996-10-22 Martin Marietta Corporation Method and system for fabricating a multilayer laminate for a printed wiring board, and a printed wiring board formed thereby
US5587342A (en) * 1995-04-03 1996-12-24 Motorola, Inc. Method of forming an electrical interconnect
WO1997010612A1 (en) * 1995-09-14 1997-03-20 Advanced Micro Devices, Inc. Damascene process for reduced feature size
JPH09153545A (ja) * 1995-09-29 1997-06-10 Toshiba Corp 半導体装置及びその製造方法
US5942802A (en) 1995-10-09 1999-08-24 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method of producing the same
JP3402022B2 (ja) * 1995-11-07 2003-04-28 三菱電機株式会社 半導体装置の製造方法
KR100387549B1 (ko) * 1995-11-28 2003-08-19 동경 엘렉트론 주식회사 피처리기판을가열하면서처리가스를이용해반도체를처리하는방법및그장치
KR100195329B1 (ko) * 1996-05-02 1999-06-15 구본준 반도체 소자의 캐패시터 제조 방법
GB2325083B (en) * 1997-05-09 1999-04-14 United Microelectronics Corp A dual damascene process
US6127721A (en) * 1997-09-30 2000-10-03 Siemens Aktiengesellschaft Soft passivation layer in semiconductor fabrication
US6245662B1 (en) 1998-07-23 2001-06-12 Applied Materials, Inc. Method of producing an interconnect structure for an integrated circuit
JP2000150516A (ja) 1998-09-02 2000-05-30 Tokyo Electron Ltd 半導体装置の製造方法
US6228758B1 (en) * 1998-10-14 2001-05-08 Advanced Micro Devices, Inc. Method of making dual damascene conductive interconnections and integrated circuit device comprising same
GB9903110D0 (en) * 1999-02-11 1999-04-07 Univ Bristol Method of fabricating etched structures
US6016011A (en) * 1999-04-27 2000-01-18 Hewlett-Packard Company Method and apparatus for a dual-inlaid damascene contact to sensor
US6251770B1 (en) * 1999-06-30 2001-06-26 Lam Research Corp. Dual-damascene dielectric structures and methods for making the same
US6635566B1 (en) * 2000-06-15 2003-10-21 Cypress Semiconductor Corporation Method of making metallization and contact structures in an integrated circuit
DE10200428A1 (de) * 2002-01-09 2003-04-30 Infineon Technologies Ag Verfahren zur Herstellung von Kontakten und Leiterbahnen mit Hilfe einer vergrabenen Hartmaske
JP2011086969A (ja) * 2011-02-01 2011-04-28 Rohm Co Ltd 半導体装置およびその製造方法
CN110571187B (zh) * 2018-06-05 2022-03-18 中芯国际集成电路制造(上海)有限公司 半导体器件的制造方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1949174B2 (de) * 1968-10-02 1971-09-23 Halbleiterbauelement
CA959383A (en) * 1972-04-05 1974-12-17 North American Rockwell Corporation Thick oxide process for improving metal deposition and stability of semiconductor devices
US4789760A (en) * 1985-04-30 1988-12-06 Advanced Micro Devices, Inc. Via in a planarized dielectric and process for producing same
US4674176A (en) * 1985-06-24 1987-06-23 The United States Of America As Represented By The United States Department Of Energy Planarization of metal films for multilevel interconnects by pulsed laser heating
JPS62260319A (ja) * 1986-05-06 1987-11-12 Mitsubishi Electric Corp 半導体装置の製造方法
JPS62293740A (ja) * 1986-06-13 1987-12-21 Fujitsu Ltd 半導体装置の製造方法
US4920070A (en) * 1987-02-19 1990-04-24 Fujitsu Limited Method for forming wirings for a semiconductor device by filling very narrow via holes
JPS6466953A (en) * 1987-09-07 1989-03-13 Nec Corp Semiconductor device
US4758533A (en) * 1987-09-22 1988-07-19 Xmr Inc. Laser planarization of nonrefractory metal during integrated circuit fabrication

Also Published As

Publication number Publication date
US5169800A (en) 1992-12-08
EP0435187A2 (en) 1991-07-03
JPH03198327A (ja) 1991-08-29
EP0435187A3 (en) 1993-01-20

Similar Documents

Publication Publication Date Title
KR910013542A (ko) 반도체장치의 제조방법
KR960043106A (ko) 반도체장치의 절연막 형성방법
KR970072297A (ko) 반도체 장치의 소자분리막 형성 방법
KR920003508A (ko) 반도체 디바이스 및 이를 제조하는 방법
KR960026594A (ko) 반도체 장치의 소자 분리방법
KR960015848A (ko) 반도체소자의 소자분리절연막 형성방법
KR970053427A (ko) 트렌치 소자분리 영역을 갖는 반도체장치의 마스크 정렬키 형성방법
JPH07249682A (ja) 半導体装置
KR940016503A (ko) 텅스텐을 이용한 콘택플러그 제조방법
KR960042958A (ko) 반도체 소자의 콘택홀 형성 방법
KR970053376A (ko) 반도체 소자의 소자분리막 형성방법
KR940012572A (ko) 반도체 장치에서의 콘택트 형성방법
KR970053411A (ko) 반도체소자의 소자분리막 제조방법
KR920005300A (ko) 다면구조 금속배선 형성방법
KR910008801A (ko) 반도체장치의 제조방법
KR970003520A (ko) 미세 반도체 소자의 콘택홀 형성방법
KR940008174A (ko) 반도체 레이저 다이오드의 제조방법
KR970023740A (ko) 층간 접속구조 및 이를 형성하는 방법
KR960039139A (ko) 반도체 소자의 금속배선층 형성방법
KR930015218A (ko) 반도체 레이저 다이오드 제조방법
KR960026181A (ko) 플러그 형성방법
KR900002432A (ko) 반도체의 사이드벽 형성방법
KR970052787A (ko) 금속배선간 절연막 형성방법
KR940001284A (ko) 반도체소자의 콘택제조방법
KR970052419A (ko) 반도체 소자의 패드 형성 방법

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E601 Decision to refuse application