KR910013542A - 반도체장치의 제조방법 - Google Patents

반도체장치의 제조방법 Download PDF

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KR910013542A
KR910013542A KR1019900021780A KR900021780A KR910013542A KR 910013542 A KR910013542 A KR 910013542A KR 1019900021780 A KR1019900021780 A KR 1019900021780A KR 900021780 A KR900021780 A KR 900021780A KR 910013542 A KR910013542 A KR 910013542A
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insulating film
opening
metal layer
laser beam
film
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고이찌 고바야시
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세끼사와 요시
후지쓰 가부시끼가이샤
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Publication of KR910013542A publication Critical patent/KR910013542A/ko

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Abstract

내용 없음.

Description

반도체장치의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도(a)-(e)는 제1발명에 따른 반도체 장치의 제조방법의 일실시예의 필수적인 단계를 나타내는 일부 절결 단면도,
제2도(a)-(e) 및 제3도(a),(b)는 제2발명에 따른 반도체 장치의 제조방법의 일실시예의 필수적인 단계를 나타내는 일부 절결 단면도.

Claims (24)

  1. 적어도 하나의 하층 절연막 및 하나의 상층 절연막으로 이루어지며, 상기 하층 절연막은 상기 상층 절연막보다 에칭률이 작아서 에칭 스톱퍼의 역할을 하며, 절연막의 에칭률은 최하층 절연막으로 향할수록 점차로 작아지는 복수개의 절연막을 하지층상에 형성하는 단계; 상기 상층 절연막을 에칭하여 제1개구부를 형성하고, 상기 제1개구부에서 상기 하층 절연막을 노출시키는 단계; 상기 제1개구부에서 노출된 상기 하층 절연막을 에칭하여 상기 제1개구부보다 폭이 작은 제2개구부를 형성하고, 상기 제2개구부에서 상기 하지층을 노출시키는 단계; 상기 제2개구부에서 노출된 상기 하지층과 접촉될 수 있도록 상기 제1 및 제2개구부에 금속층을 형성하는 단계 및 상기 금속층에 레이저 빔을 조사하여 상기 제1 및 제2개구부에 금속층을 매몰하고, 매몰된 금속층을 평탄화시키는 단계로 이루어진 반도체장치의 제조방법.
  2. 제1항에 있어서, 상기 복수개의 절연막중 하나는 상기 하지층이 손상되지 않도록 레이저 빔에 관하여 30%이상의 흡수율을 갖는 반도체장치의 제조방법.
  3. 제1항에 있어서, 상기 하지층은 Al, Al 염기화합물 Cu, Cu 염기화합물, 단결정 Si, 다결정 Si 또는 GaAs나 AlGaAs와 같은 화합물 반도체로 이루어진 반도체장치의 제조방법.
  4. 제1항에 있어서, 상기 상층 절연막은 산화 규소막 또는 인(P)을 함유하는 산호 규소막으로 이루어지고, 상기 하층 절연막은 알루미나(Al2O3)로 이루어진 반도체장치의 제조방법.
  5. 제1항에 있어서, 상기 레이저 빔은 엑사이머 레이저 빔으로 이루어진 반도체장치의 제조방법.
  6. 제5항에 있어서, 상기 금속층은 Al, Al 염기 화합물, Cu 또는 Cu 염기 화합물로 이루어진 반도체장치의 제조방법.
  7. 적어도 하나의 제1절연막, 하나의 제2절연막 및 하나의 제3절연막으로 이루어지며, 상기 제2절연막은 상기 제1 및 제3절연막보다 에칭률이 작아서 에칭 스톱퍼 및 차양막의 역할을 하는 복수개의 절연막을 하지층상에 형성하는 단계; 상기 제3절연막을 에칭하여 제1개구부를 형성하고, 상기 제1개구부에서 상기 제2절연막을 노출하는 단계; 상기 제1개구부에서 노출된 상기 제2절연막을 에칭하고 상기 제1절연막을 에칭하여 상기 제1개구부보다 폭이 작은 제2개구부를 형성하고, 상기 제2개구부에서 상기 하지층을 노출시키는 단계; 상기 제2개구부에서 노출된 상기 하지층과 접촉할 수 있도록 상기 제1 및 제2재구부에 금속층을 형성하는 단계 및 상기 금속층에 레이저 빔을 조사하여 상기 금속층을 상기 제1 및 제2개구부에 매몰하고, 매몰된 금속층을 평탄화시키는 단계로 이루어진 반도체장치의 제조방법.
  8. 제7항에 있어서, 상기 제2절연막은 상기 하지층이 손상되지 않도록 레이저 빔에 관하여 30% 이상의 흡수율을 갖는 반도체장치의 제조방법.
  9. 제7항에 있어서, 상기 하지층은 Al, Al 염기화합물, Cu, Cu 염기화합물, 단결정 Si, 다결정 Si 또는 GaAs나 AlGaAs와 같은 화합물 반도체로 이루어진 반도체장치의 제조방법.
  10. 제7항에 있어서, 상기 제1절연막은 산화 규소막 또는 인을 함유하는 산화 규소막으로 이루어지며, 상기 제2절연막은 Al2O3로 이루어지며, 상기 제3절연막은 산화 규소막 또는 인을 함유하는 산화규소막으로 이루어진 반도체장치의 제조방법.
  11. 제7항에 있어서, 상기 레이저 빔은 엑사이며 레이저 빔으로 이루어진 반도체장치의 제조방법.
  12. 제11항에 있어서, 상기 금속층은 Al, Al 염기화합물 Cu 또는 Cu 염기화합물로 이루어진 반도체장치의 제조방법.
  13. 복수개의 절연막의 제1절연막 및 복수개의 절연막의 상기 제1절연막 및 제3절연막 보다 에칭률이 작고 에칭스톱퍼 및 차양막의 역할을 하는 복수개의 절연막의 제2절연막을 하지층상에 차례로 형성되는 단계; 상기 제2절연막을 에칭하여 제1개구부를 형성하고, 상기 제1개구부에서 상기 제1절연막을 노출시키는 단계; 상기 제2절연막 및 상기 제1개구부가 상기 제3절연막으로 덮히도록 상기 제3절연막을 상기 제2절연막상에 형성하는 단계; 상기 제3절연막 및 상기 제1절연막을 에칭하여 상기 제1개구부보다 폭이 큰 제2개구부를 상기 제1개구부상의 상기 제3절연막에 형성하며 또한, 상기 제1개구부와 실질적으로 폭이 같은 제3개구부를 상기 제1절연막에 형성해서, 상기 제3개구부에서 상기 하지층을 노출시키는 단계; 상기 제3개구부에서 노출된 상기 하지층에 접촉할 수 있도록 상기 제1, 제2 및 제3개구부에 금속층을 형성하는 단계 및 상기 금속층에 레이저 빔을 조사하여 상기 제1, 제2 및 제3개구부에 상기 금속층을 매몰하고, 매몰된 금속층을 평탄화시키는 단계로 이루어진 반도체장치의 제조방법.
  14. 제13항에 있어서, 상기 제2절연막은 상기 하지층이 손상되지 않도록 레이저 빔에 관하여 30% 이상의 흡수율을 갖는 반도체장치의 제조방법.
  15. 제13항에 있어서, 상기 하지층은 Al, Al 염기화합물, Cu, Cu 염기화합물, 단결정Si, 다결정 Si 또는 GaAs 나 AlGaAs와 같은 화합물 반도체로 이루어진 반도체장치의 제조방법.
  16. 제13항에 있어서, 상기 제1절연막은 산화 규소막 또는 인을 함유하는 산화 규소막으로 이루어지며, 상기 제2절연막은 Al2O3로 이루어지며, 상기 제3절연막은 산화규소막 또는 인을 함유하는 산화규소막으로 이루어진 반도체장치의 제조방법.
  17. 제13항에 있어서, 상기 레이저 빔은 엑사이며 레이저 빔으로 이루어진 반도체장치의 제조방법.
  18. 제17항에 있어서, 상기 금속층은 Al, Al 염기화합물, Cu 또는 Cu 염기화합물로 이루어진 반도체장치의 제조방법.
  19. 복수개의 절연막의 제1절연막 및 복수개의 절연막의 상기 제1절연막 및 제3절연막 보다 에칭률이 작고 에칭스톱퍼 및 차양막의 역할을 하는 복수개의 절연막의 제2절연막을 하지층상에 차례로 형성되는 단계; 상기 제1 및 제2연막을 에칭하여 제1개구부를 형성하는 단계; 상기 제2절연막 및 상기 제1개구부가 상기 제3절연막으로 덮히도록 상기 제3절연막을 상기 제2절연막상에 형성하는 단계; 상기 제3절연막을 에칭하여 상기 제1개구부보다 폭이 큰 상기 제2개구부를 상기 제1개구부상의 상기 제3절연막에 형성하고 또한, 상기 제1개구부의 상기 제1 및 제2절연막의 측벽상에 측벽 절연막을 형성해서 상기 측벽 절연막에 의해 한정된 개구부에서 상기 하지층을 노출시키는 단계; 상기 측벽 절연막에 의해 한정된 상기 개구부에서 노출된 상기 하지층과 접촉될 수 있도록 상기 제1 및 제2개구부 금속층을 형성하는 단계 및 상기 금속층에 레이저 빔을 조사하여 상기 제1 및 제2개구부에 상기 금속층을 매몰하고, 매몰된 금속층을 평탄화 시키는 단계로 이루어진 반도체장치의 제조방법.
  20. 제19항에 있어서, 상기 제2절연막은 상기 하지층이 손상되지 않도록 레이저 빔에 관하여 30% 이상의 흡수율을 갖는 반도체장치의 제조방법.
  21. 제19항에 있어서, 상기 하지층은 Al, Al 염기화합물, Cu, Cu 염기화합물, 단결정Si, 다결정 Si 또는 GaAs 나 AlGaAs와 같은 화합물 반도체로 이루어진 반도체장치의 제조방법.
  22. 제19항에 있어서, 상기 제1절연막은 산화 규소막 또는 인을 함유한 산화 규소막으로 이루어지며, 상기 제2절연막은 Al2O3로 이루어지며, 상기 제3절연막은 산화 규소막 또는 인을 함유하는 산화 규소막으로 이루어진 반도체장치의 제조방법.
  23. 제19항에 있어서, 상기 레이져 빔은 엑사이며 레이저 빔으로 이루어진 반도체장치의 제조방법.
  24. 제23항에 있어서, 상기 금속층 Al, Al 염기화합물, Cu 또는 Cu 염기화합물인 것을 특징으호 하는 반도체장치의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019900021780A 1989-12-26 1990-12-26 반도체장치의 제조방법 KR910013542A (ko)

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Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2740050B2 (ja) * 1991-03-19 1998-04-15 株式会社東芝 溝埋込み配線形成方法
JP2907599B2 (ja) * 1991-08-26 1999-06-21 シャープ株式会社 配線層の形成方法
JPH05129296A (ja) * 1991-11-05 1993-05-25 Fujitsu Ltd 導電膜の平坦化方法
JPH05160272A (ja) * 1991-12-04 1993-06-25 Nec Corp 半導体装置の製造方法
JP3332456B2 (ja) * 1992-03-24 2002-10-07 株式会社東芝 半導体装置の製造方法及び半導体装置
KR950010041B1 (ko) * 1992-03-28 1995-09-06 현대전자산업주식회사 콘택 홀(contact hole) 구조 및 그 제조방법
JPH06260441A (ja) * 1993-03-03 1994-09-16 Nec Corp 半導体装置の製造方法
DE4400532C1 (de) * 1994-01-11 1995-03-23 Siemens Ag Verfahren zum Herstellen von Flüssigkontakten in Kontaktlöchern
US5635423A (en) * 1994-10-11 1997-06-03 Advanced Micro Devices, Inc. Simplified dual damascene process for multi-level metallization and interconnection structure
US5567329A (en) * 1995-01-27 1996-10-22 Martin Marietta Corporation Method and system for fabricating a multilayer laminate for a printed wiring board, and a printed wiring board formed thereby
US5587342A (en) * 1995-04-03 1996-12-24 Motorola, Inc. Method of forming an electrical interconnect
JPH10509285A (ja) * 1995-09-14 1998-09-08 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 縮小したフィーチャーサイズのためのダマスクプロセス
JPH09153545A (ja) * 1995-09-29 1997-06-10 Toshiba Corp 半導体装置及びその製造方法
US5942802A (en) * 1995-10-09 1999-08-24 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method of producing the same
JP3402022B2 (ja) * 1995-11-07 2003-04-28 三菱電機株式会社 半導体装置の製造方法
US6140256A (en) * 1995-11-28 2000-10-31 Tokyo Electron Limited Method and device for treating semiconductor with treating gas while substrate is heated
KR100195329B1 (ko) * 1996-05-02 1999-06-15 구본준 반도체 소자의 캐패시터 제조 방법
GB2325083B (en) * 1997-05-09 1999-04-14 United Microelectronics Corp A dual damascene process
US6127721A (en) * 1997-09-30 2000-10-03 Siemens Aktiengesellschaft Soft passivation layer in semiconductor fabrication
US6245662B1 (en) * 1998-07-23 2001-06-12 Applied Materials, Inc. Method of producing an interconnect structure for an integrated circuit
JP2000150516A (ja) * 1998-09-02 2000-05-30 Tokyo Electron Ltd 半導体装置の製造方法
US6228758B1 (en) 1998-10-14 2001-05-08 Advanced Micro Devices, Inc. Method of making dual damascene conductive interconnections and integrated circuit device comprising same
GB9903110D0 (en) * 1999-02-11 1999-04-07 Univ Bristol Method of fabricating etched structures
US6016011A (en) * 1999-04-27 2000-01-18 Hewlett-Packard Company Method and apparatus for a dual-inlaid damascene contact to sensor
US6251770B1 (en) * 1999-06-30 2001-06-26 Lam Research Corp. Dual-damascene dielectric structures and methods for making the same
US6635566B1 (en) * 2000-06-15 2003-10-21 Cypress Semiconductor Corporation Method of making metallization and contact structures in an integrated circuit
DE10200428A1 (de) * 2002-01-09 2003-04-30 Infineon Technologies Ag Verfahren zur Herstellung von Kontakten und Leiterbahnen mit Hilfe einer vergrabenen Hartmaske
JP2011086969A (ja) * 2011-02-01 2011-04-28 Rohm Co Ltd 半導体装置およびその製造方法
CN110571187B (zh) * 2018-06-05 2022-03-18 中芯国际集成电路制造(上海)有限公司 半导体器件的制造方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1949174B2 (de) * 1968-10-02 1971-09-23 Halbleiterbauelement
CA959383A (en) * 1972-04-05 1974-12-17 North American Rockwell Corporation Thick oxide process for improving metal deposition and stability of semiconductor devices
US4789760A (en) * 1985-04-30 1988-12-06 Advanced Micro Devices, Inc. Via in a planarized dielectric and process for producing same
US4674176A (en) * 1985-06-24 1987-06-23 The United States Of America As Represented By The United States Department Of Energy Planarization of metal films for multilevel interconnects by pulsed laser heating
JPS62260319A (ja) * 1986-05-06 1987-11-12 Mitsubishi Electric Corp 半導体装置の製造方法
JPS62293740A (ja) * 1986-06-13 1987-12-21 Fujitsu Ltd 半導体装置の製造方法
US4920070A (en) * 1987-02-19 1990-04-24 Fujitsu Limited Method for forming wirings for a semiconductor device by filling very narrow via holes
JPS6466953A (en) * 1987-09-07 1989-03-13 Nec Corp Semiconductor device
US4758533A (en) * 1987-09-22 1988-07-19 Xmr Inc. Laser planarization of nonrefractory metal during integrated circuit fabrication

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