KR910008801A - 반도체장치의 제조방법 - Google Patents

반도체장치의 제조방법 Download PDF

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Publication number
KR910008801A
KR910008801A KR1019900016768A KR900016768A KR910008801A KR 910008801 A KR910008801 A KR 910008801A KR 1019900016768 A KR1019900016768 A KR 1019900016768A KR 900016768 A KR900016768 A KR 900016768A KR 910008801 A KR910008801 A KR 910008801A
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South Korea
Prior art keywords
manufacturing
insulating layer
semiconductor device
resist
forming
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KR1019900016768A
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English (en)
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KR940009996B1 (ko
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히토시 츠지
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아오이 죠이치
가부시키가이샤 도시바
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/268Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66848Unipolar field-effect transistors with a Schottky gate, i.e. MESFET
    • H01L29/66856Unipolar field-effect transistors with a Schottky gate, i.e. MESFET with an active layer made of a group 13/15 material
    • H01L29/66863Lateral single gate transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0272Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers for lift-off processes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28575Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
    • H01L21/28581Deposition of Schottky electrodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28575Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
    • H01L21/28587Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds characterised by the sectional shape, e.g. T, inverted T
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31144Etching the insulating layers by chemical or physical means using masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66446Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT

Abstract

내용 없음

Description

반도체장치의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 1도(a) 내지 제 1 도(e)는 본 발명의 1실시예를 나타낸 측단면도이다.

Claims (5)

  1. 반도체기판(1)상에 제 1절연층(2)을 형성하는 공정과, 상기 제 1절연층(2)상에 전자빔에 감응되는 레지스트를 형성하는 공정. 패턴을 전자빔으로 조사하는 공정. 현상액에 의해 불필요한 영역의 레지스트를 제거해서 레지스트의 잔류패턴(3)을 형성하는 공정, 상기 제 1 절연층(2)의 전면상에 제 2 절연층(4)을 형성하는 공정. 상기 레지스트의 잔류패턴(3)을 제거함으로써 상기 제 2 절연층(4)에 개공패턴을 형성하는 공정, 상기 제 2 절연층(4)을 마스크로 해서 제 1 절연층(2)을 에칭함으로써 상기 반도체기판(1)상에 개공패턴을 형성하는 공정으로 이루어진 것을 특징으로 하는 반도체장치의 제조방법.
  2. 제 1 항에 있어서, 상기 레지스트가 네가형인 것을 특징으로 하는 반도체장치의 제조방법.
  3. 제 1 항에 있어서, 상기 반도체기판(1)이 GaAs로 형성된 것을 특징으로 하는 반도체장치의 제조방법.
  4. 제 1 항에 있어서, 상기 반도체기판(1)에 형성되는 제 1, 제 2 절연층(2,4)이 적어도 SiOnN, Si3N4, SiO2중 어느 하나로 형성되는 것을 특징으로 하는 반도체장치의 제조방법.
  5. 제 1 항에 있어서, 상기 제 1, 제 2 절연층(2,4)은 각각 500∼1000Å의 두께로 형성되는 것을 특징으로 하는 반도체장치의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019900016768A 1989-10-24 1990-10-20 반도체장치의 제조방법 KR940009996B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP1274971A JPH03138938A (ja) 1989-10-24 1989-10-24 半導体装置の製造方法
JP01-274971 1989-10-24

Publications (2)

Publication Number Publication Date
KR910008801A true KR910008801A (ko) 1991-05-31
KR940009996B1 KR940009996B1 (ko) 1994-10-19

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Application Number Title Priority Date Filing Date
KR1019900016768A KR940009996B1 (ko) 1989-10-24 1990-10-20 반도체장치의 제조방법

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EP (1) EP0425957A3 (ko)
JP (1) JPH03138938A (ko)
KR (1) KR940009996B1 (ko)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020155389A1 (en) 2000-10-24 2002-10-24 Bharath Rangarajan Inverse resist coating process
JP4645018B2 (ja) * 2003-11-06 2011-03-09 セイコーエプソン株式会社 コンタクトホールの形成方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4144101A (en) * 1978-06-05 1979-03-13 International Business Machines Corporation Process for providing self-aligned doping regions by ion-implantation and lift-off
JPS60194577A (ja) * 1984-03-16 1985-10-03 Nippon Telegr & Teleph Corp <Ntt> 電界効果トランジスタの製造方法
JPS60214532A (ja) * 1984-04-11 1985-10-26 Nippon Telegr & Teleph Corp <Ntt> パタ−ン形成方法
JPS6229175A (ja) * 1985-07-29 1987-02-07 Nippon Telegr & Teleph Corp <Ntt> 電界効果型トランジスタの製造方法
JPS6455872A (en) * 1987-08-26 1989-03-02 Sumitomo Electric Industries Manufacture of self-alignment type gate electrode
JPH01136375A (ja) * 1987-11-24 1989-05-29 Sumitomo Electric Ind Ltd 電界効果トランジスタの製造方法

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Publication number Publication date
EP0425957A3 (en) 1991-07-24
JPH03138938A (ja) 1991-06-13
KR940009996B1 (ko) 1994-10-19
EP0425957A2 (en) 1991-05-08

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