DE69025939D1 - Apparat und verfahren zur herstellung einer speicherzelle mit schwebendem gate und doppelter dielektrikumschicht - Google Patents

Apparat und verfahren zur herstellung einer speicherzelle mit schwebendem gate und doppelter dielektrikumschicht

Info

Publication number
DE69025939D1
DE69025939D1 DE69025939T DE69025939T DE69025939D1 DE 69025939 D1 DE69025939 D1 DE 69025939D1 DE 69025939 T DE69025939 T DE 69025939T DE 69025939 T DE69025939 T DE 69025939T DE 69025939 D1 DE69025939 D1 DE 69025939D1
Authority
DE
Germany
Prior art keywords
layer
forming
conducting
insulating layer
dielectric layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69025939T
Other languages
English (en)
Other versions
DE69025939T2 (de
Inventor
Daniel Guterman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xicor LLC
Original Assignee
Xicor LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xicor LLC filed Critical Xicor LLC
Application granted granted Critical
Publication of DE69025939D1 publication Critical patent/DE69025939D1/de
Publication of DE69025939T2 publication Critical patent/DE69025939T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H01L29/42328—Gate electrodes for transistors with a floating gate with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7883—Programmable transistors with only two possible levels of programmation charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
DE69025939T 1989-06-21 1990-05-08 Apparat und verfahren zur herstellung einer speicherzelle mit schwebendem gate und doppelter dielektrikumschicht Expired - Fee Related DE69025939T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US36913489A 1989-06-21 1989-06-21
PCT/US1990/002555 WO1990016085A1 (en) 1989-06-21 1990-05-08 Apparatus and method for a dual thickness dielectric floating gate memory cell

Publications (2)

Publication Number Publication Date
DE69025939D1 true DE69025939D1 (de) 1996-04-18
DE69025939T2 DE69025939T2 (de) 1996-08-01

Family

ID=23454223

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69025939T Expired - Fee Related DE69025939T2 (de) 1989-06-21 1990-05-08 Apparat und verfahren zur herstellung einer speicherzelle mit schwebendem gate und doppelter dielektrikumschicht

Country Status (4)

Country Link
EP (1) EP0478577B1 (de)
AT (1) ATE135495T1 (de)
DE (1) DE69025939T2 (de)
WO (1) WO1990016085A1 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5331189A (en) * 1992-06-19 1994-07-19 International Business Machines Corporation Asymmetric multilayered dielectric material and a flash EEPROM using the same
DE19941684B4 (de) * 1999-09-01 2004-08-26 Infineon Technologies Ag Halbleiterbauelement als Verzögerungselement
US8320191B2 (en) 2007-08-30 2012-11-27 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4203158A (en) * 1978-02-24 1980-05-13 Intel Corporation Electrically programmable and erasable MOS floating gate memory device employing tunneling and method of fabricating same
JPS6046554B2 (ja) * 1978-12-14 1985-10-16 株式会社東芝 半導体記憶素子及び記憶回路
US4486769A (en) * 1979-01-24 1984-12-04 Xicor, Inc. Dense nonvolatile electrically-alterable memory device with substrate coupling electrode
US4300212A (en) * 1979-01-24 1981-11-10 Xicor, Inc. Nonvolatile static random access memory devices
US4328565A (en) * 1980-04-07 1982-05-04 Eliyahou Harari Non-volatile eprom with increased efficiency
JPS5857750A (ja) * 1981-10-01 1983-04-06 Seiko Instr & Electronics Ltd 不揮発性半導体メモリ
JPS5933873A (ja) * 1982-08-20 1984-02-23 Hitachi Ltd 半導体素子の製造方法
JPS611056A (ja) * 1984-06-14 1986-01-07 Toshiba Corp 不揮発性半導体記憶装置
JPS6288368A (ja) * 1985-10-15 1987-04-22 Seiko Instr & Electronics Ltd 半導体不揮発性メモリ
US4706102A (en) * 1985-11-07 1987-11-10 Sprague Electric Company Memory device with interconnected polysilicon layers and method for making
JPS6367783A (ja) * 1986-09-09 1988-03-26 Mitsubishi Electric Corp 半導体記憶装置
JPH0196950A (ja) * 1987-10-08 1989-04-14 Fujitsu Ltd 半導体装置の製造方法

Also Published As

Publication number Publication date
EP0478577B1 (de) 1996-03-13
EP0478577A1 (de) 1992-04-08
ATE135495T1 (de) 1996-03-15
EP0478577A4 (en) 1992-07-08
DE69025939T2 (de) 1996-08-01
WO1990016085A1 (en) 1990-12-27

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee