WO1995028000A3 - Method of manufacturing a semiconductor device with a multilayer wiring structure containing narrow vias - Google Patents

Method of manufacturing a semiconductor device with a multilayer wiring structure containing narrow vias Download PDF

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Publication number
WO1995028000A3
WO1995028000A3 PCT/IB1995/000180 IB9500180W WO9528000A3 WO 1995028000 A3 WO1995028000 A3 WO 1995028000A3 IB 9500180 W IB9500180 W IB 9500180W WO 9528000 A3 WO9528000 A3 WO 9528000A3
Authority
WO
WIPO (PCT)
Prior art keywords
layer
manufacturing
semiconductor device
multilayer wiring
wiring structure
Prior art date
Application number
PCT/IB1995/000180
Other languages
French (fr)
Other versions
WO1995028000A2 (en
Inventor
Hermanus Leonardus Peek
Daniel Wilhelmus Elisa Verbugt
Original Assignee
Philips Electronics Nv
Philips Norden Ab
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Electronics Nv, Philips Norden Ab filed Critical Philips Electronics Nv
Priority to EP95910699A priority Critical patent/EP0704105A2/en
Priority to JP7526198A priority patent/JPH08511659A/en
Publication of WO1995028000A2 publication Critical patent/WO1995028000A2/en
Publication of WO1995028000A3 publication Critical patent/WO1995028000A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A method of manufacturing a semiconductor device with a semiconductor body (2) having a surface (1) which is provided with a multilayer wiring structure (3, 9) of conductor tracks made of a same conductive material. A first wiring layer (3) comprising conductor tracks (4, 16, 18, 19, 22, 23, 24, 29, 30) is formed on the surface. These tracks are covered with an insulating layer (5, 20, 21, 25, 26, 27, 31, 32). An auxiliary layer (12, 15) of insulating material is provided on the insulation layer. Openings (13) are etched into the auxiliary layer at the areas of the contact windows. Then the contact windows are formed in that the semiconductor body is subjected to a wet etching process capable of selectively etching the insulating material of the insulation layer not only relative to the conductive material but also relative to the insulating material of the auxiliary layer. Then a layer (10) of the conductive material is deposited on the surface, and a second wiring layer (9) of narrow conductor tracks (11) is formed therein.
PCT/IB1995/000180 1994-04-07 1995-03-17 Method of manufacturing a semiconductor device with a multilayer wiring structure containing narrow vias WO1995028000A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP95910699A EP0704105A2 (en) 1994-04-07 1995-03-17 Method of manufacturing a semiconductor device with a semiconductor body having a surface provided with a multilayer wiring structure
JP7526198A JPH08511659A (en) 1994-04-07 1995-03-17 Method for manufacturing a semiconductor device having a multilayer wiring structure provided on the surface of a semiconductor body

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP94200940 1994-04-07
EP94200940.8 1994-07-04

Publications (2)

Publication Number Publication Date
WO1995028000A2 WO1995028000A2 (en) 1995-10-19
WO1995028000A3 true WO1995028000A3 (en) 1995-12-28

Family

ID=8216774

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB1995/000180 WO1995028000A2 (en) 1994-04-07 1995-03-17 Method of manufacturing a semiconductor device with a multilayer wiring structure containing narrow vias

Country Status (4)

Country Link
EP (1) EP0704105A2 (en)
JP (1) JPH08511659A (en)
KR (1) KR100374527B1 (en)
WO (1) WO1995028000A2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6046100A (en) * 1996-12-12 2000-04-04 Applied Materials, Inc. Method of fabricating a fabricating plug and near-zero overlap interconnect line
CN100416409C (en) * 2001-03-29 2008-09-03 大日本印刷株式会社 Method for making electronic component using wet corrosion agent
DE10320166B4 (en) * 2002-05-16 2007-06-06 Dalsa Corp., Waterloo Pixel design for CCD image sensors
EP2044637B1 (en) * 2006-07-25 2015-09-16 LG Chem, Ltd. Method of manufacturing organic light emitting device and organic light emitting device manufactured by using the method

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0004164A1 (en) * 1978-03-02 1979-09-19 Sperry Corporation Method of making interlayer electrical connections in a multilayer electrical device
EP0282820A1 (en) * 1987-03-13 1988-09-21 Siemens Aktiengesellschaft Method for producing contact holes with sloping walls in intermediate oxide layers
US4943539A (en) * 1989-05-09 1990-07-24 Motorola, Inc. Process for making a multilayer metallization structure
DE3914602A1 (en) * 1989-05-03 1990-11-08 Bosch Gmbh Robert Tapering via prodn. esp. in multilevel circuits - by etching insulation layers with different etch rates
EP0523856A2 (en) * 1991-06-28 1993-01-20 STMicroelectronics, Inc. Method of via formation for multilevel interconnect integrated circuits
EP0555032A1 (en) * 1992-02-06 1993-08-11 STMicroelectronics, Inc. Semiconductor contact via structure and method

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0004164A1 (en) * 1978-03-02 1979-09-19 Sperry Corporation Method of making interlayer electrical connections in a multilayer electrical device
EP0282820A1 (en) * 1987-03-13 1988-09-21 Siemens Aktiengesellschaft Method for producing contact holes with sloping walls in intermediate oxide layers
DE3914602A1 (en) * 1989-05-03 1990-11-08 Bosch Gmbh Robert Tapering via prodn. esp. in multilevel circuits - by etching insulation layers with different etch rates
US4943539A (en) * 1989-05-09 1990-07-24 Motorola, Inc. Process for making a multilayer metallization structure
EP0523856A2 (en) * 1991-06-28 1993-01-20 STMicroelectronics, Inc. Method of via formation for multilevel interconnect integrated circuits
EP0555032A1 (en) * 1992-02-06 1993-08-11 STMicroelectronics, Inc. Semiconductor contact via structure and method

Also Published As

Publication number Publication date
JPH08511659A (en) 1996-12-03
WO1995028000A2 (en) 1995-10-19
KR100374527B1 (en) 2003-05-09
KR960702940A (en) 1996-05-23
EP0704105A2 (en) 1996-04-03

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