KR100374527B1 - Semiconductor device manufacturing method - Google Patents

Abstract

The invention comprises a semiconductor body (2) having a surface (1) formed with a multilayer wiring structure (3, 9) of conductor tracks made of the same conductive material. A method for manufacturing a semiconductor device. A first wiring layer 3 comprising conductor tracks 4, 16, 18, 19, 22, 23, 24, 29 and 30 is formed on this surface. These tracks are insulated layers 5, 20 and 21 in which contact windows 8 are formed by a wet etching process capable of selectively etching the material of the insulating layer relative to the conductive material. And 25,26,27,31,32, the contact window locally exposing at least a portion of the conductive track of the first wiring layer. Then, a layer 10 of conductive material is deposited on the surface, in which a second wiring layer 9 of the conductor track 11 is formed. Before the contact window is formed, auxiliary layers 12 and 15 of insulating material are provided on the insulating layer. Openings 13 are etched into the auxiliary layer of the contact window area. The contact window is then formed by a wet etching process in which the semiconductor body can selectively etch the insulating material of the insulating layer, not only for the conductive material but also for the insulating material of the auxiliary layer. Due to the use of the auxiliary layer, the conductor track of the second wiring layer can be made relatively narrow.

Description

Semiconductor device manufacturing method

The present invention relates to a method of manufacturing a semiconductor device having a semiconductor body having a surface provided with a multilayer wiring structure of conductor tracks made of the same conductive material. A first wiring layer is formed on the surface and then covered with an insulating layer, in which the contact windows are formed by a wet etching process, the wet etching. The treatment allows the material of the insulating layer to be selectively etched with respect to the conductive material, the contact window locally exposing at least a portion of the conductor track of the first wiring layer, after which the layer of conductive material is deposited on the surface ( and a second wiring layer of conductor track is formed in this conductive material.

The conductor track consisting of these two wiring layers can be made of, for example, conductive polycrystalline silicon, aluminum, tungsten, or a metal silicide, and the insulating layer is, for example, silicon It may be made of silicon oxide. Such a multilayer wiring structure is particularly used for semiconductor memories and charge coupled devices.

In practice, this first wiring layer may comprise two different conductor tracks, and the insulating layer provided on the conductor tracks may also have locally different thicknesses. A problem therefore arises during the etching of the contact window which locally exposes the conductor tracks of the first wiring layer. This is because, within the contact window, the etching process must continue until the conductor track is exposed, even in a position where the insulation layer is relatively thick. At this time, the conductor track is etched for a relatively long period even in a position where the insulating layer is relatively thin. Thus, for these latter conductor tracks the upper part of their thickness is scraped off. This can cause interruption of the conductor track in a location where the apprentice track is also relatively thin. Thus, the contact window is provided in the insulating layer by the wet etching process, whereby the material of the insulating layer can be selectively etched with respect to the conductor material. The wet etching treatment can achieve an etching selectivity that is sufficiently good to prevent the above problem.

The English abstract of JP-A-57 / 31157 discloses a method of the kind mentioned at the outset, whereby an insulating layer made of silicon oxide is deposited on the first wiring layer. The contact window is etched into the insulating layer by HF solution. Thus, since the contact window is formed by a wet etching process, the silicon oxide is very selectively etched with respect to the conductor track.

After a photoresist mask having openings in the area of the contact window is provided in the insulating layer, the semiconductor body is immersed in an etching bath so that the contact window is etched into the insulating layer. A disadvantage of the contact window formation by the wet etching process is that the etching process proceeds isotropically. At this time, the etching proceeds at substantially the same speed in the horizontal direction and the vertical direction. Thus, the contact window in the insulating layer is larger than the opening in the photoresist mask. According to current photolithographical techniques, very small openings with a length and width of, for example, 0.5 μm can be realized in the photoresist mask. This results in a contact window having a length and width of approximately 0.9 μm in an approximately 0.2 μm thick layer of insulating material. These contact windows are filled during deposition of the conductive material layer forming the second wiring layer. Since the conductor tracks of these two wiring layers are formed of the same conductive material, the conductor tracks of the first wiring layer should not be exposed while etching the conductor tracks of the second wiring layer. In the meantime, the conductor track of the second wiring layer must completely shield the contact window in the insulating layer. Photoresist masks are also used for the etching of these conductor tracks. If this photoresist mask can be arranged for a contact window formed with an error of ± 0.1 μm, the conductor track of the second wiring layer should have a width greater than 1.1 μm in the area of the contact window.

It is an object of the present invention, in particular, to provide a method of the kind mentioned at the outset so that the contact window does not need to be completely shielded by the conductor tracks of the second wiring layer during the formation of the second wiring layer, so that these conductor tracks are It is to allow a relatively small width.

According to the present invention, a method for achieving the above object is provided in which an auxiliary layer consisting of an insulating layer is provided on an insulating layer before a contact window is formed, and then an opening is first etched into the auxiliary layer of the contact window region, and then And the semiconductor body is wet etched so that the insulating material of the insulating layer can be selectively etched not only for the conductive material but also for the insulating material of the auxiliary layer, thereby forming a contact window in the insulating layer.

As will become more apparent below, the openings may be etched into the auxiliary layer at a length and width that substantially matches the length and width of the openings in the photoresist mask used to etch the contact window. The window is formed in the insulating layer to be larger than the opening in the auxiliary layer while etching the contact window into the insulating layer located below the auxiliary layer. At this time, the insulating layer is removed in the narrow window below the edge of the auxiliary layer. This contact window also fills the bottom of the auxiliary layer during the deposition of the conductive material layer forming the second wiring layer. In this way, the conductor track is formed in the generation of the second wiring layer of the conductor track with a width substantially the same size as the width of the opening etched into the auxiliary layer. Etching of the conductive layer is stopped in the auxiliary layer, and the edge of the auxiliary layer protects the underlying conductive material. If the opening in the auxiliary layer is given with a length and width of 0.5 μm under the same conditions as described above, a conductor track having a width of 0.7 μm at most can be formed on the auxiliary layer.

Preferably, the auxiliary layer is deposited on the entire surface of the semiconductor body by a chemical vapor deposition process. The layer thus deposited exhibits a substantially uniform thickness over its entire surface area. This opening may be etched in this auxiliary layer to a width and length substantially equal to the length and width of the opening in the photoresist mask, for example, by an anisotropic plasma etching process such as a reactive ion etching process. Can be. This etching process has an etching selectivity lower than that of the wet etching process, but since the deposited layer has a substantially uniform thickness over the entire surface, the underlying layer is local to the etching plasma for a predetermined length of time. The contact window can be etched in the auxiliary layer without being treated with. The etching process may simply be stopped after a predetermined duration determined by the test, without the insulation layer located under the auxiliary layer being greatly affected.

In addition, when the auxiliary layer is deposited to a thickness of less than 50 nm, the openings in the auxiliary layer can be isotropically etched, for example, in a wet etching process, whereby the openings in the auxiliary layer are made larger than the openings in the photoresist mask. However, this extension remains limited. Since the isotropic etching process proceeds at substantially equal speeds in the horizontal and vertical directions, this expansion can be kept limited to the thickness in the auxiliary layer. As in the embodiment described above, when the opening in the photoresist layer is given a length and width of 0.5 μm and the thickness of the auxiliary layer is less than 50 nm, the opening is larger than 0.5 μm and less than 0.6 μm in length and width. It is created in the auxiliary layer. If the conductor track can be provided with an accuracy of ± 0.1 μm, then the conductor track should have a width greater than 0.7 μm and less than 0.8 μm to protect the contact window.

Preferably, the conductor track of the first wiring layer is provided on an insulating sub-layer made of a material from which the material of the insulating layer can be selectively etched, preferably the same material as the material of the auxiliary layer. . At this time, the conductor track of the first wiring layer can be made narrower than the contact window. The substrate is protected by an insulating servo layer during the etching of the contact window, and without this servo layer, the substrate can also be etched. The contact window will have a length and width of approximately 0.9 μm using the photolithographic process mentioned above. In the absence of a servo layer, the conductor tracks located underneath these contact windows should be at least 1.1 μm wide, but with the servo layer they may even be narrower than 0.5 μm achievable by photolithographic processing. have. For example, when a 0.5 μm wide polycrystalline silicon track is provided with an insulating silicon oxide layer via thermal oxidation, very narrow conductor tracks are formed. The invention will be explained in more detail by the examples with reference to the following schematic cross-sectional views.

1 through 4 illustrate several steps in the manufacture of a first semiconductor device in which another method is used in the present invention.

4 is a cross sectional view taken on the line A-A in FIG.

5 and 6 show several steps in the fabrication of a second embodiment of a semiconductor device.

7 and 8 illustrate some steps in the fabrication of a third embodiment of a semiconductor device.

9 shows steps in the manufacture of a fourth semiconductor device.

10 and 11 illustrate several steps in the fabrication of a fifth embodiment of a semiconductor device.

12 and 13 illustrate several steps in the fabrication of a sixth embodiment of a semiconductor device.

FIG. 14 is a cross sectional view taken on line B-B in FIG.

15, 16 and 17 illustrate several steps in the manufacture of a seventh semiconductor device.

1 to 4 show schematic, cross-sectional views of several steps in the manufacture of a first semiconductor device in which the method according to the invention is used. After the first wiring layer 3 of the conductor track 4 of approximately 200 nm thickness made of polycrystalline silicon on the surface 1 of the silicon semiconductor body 2 is formed in a conventional manner, approximately 200 nm thick of silicon oxide is formed. Covered with an insulating layer 5. Then, after the photoresist mask 6 having the opening 7 is provided, the semiconductor body is immersed in an etching solution containing a usual buffered HF solution, and the material of the insulating layer is a conductive material. A contact window 8 is formed in the insulating layer 5 by a wet etching process that can be selectively etched against. The contact window 8 locally exposes at least a portion of the conductor track 4 of the first wiring layer 3. In the figure, all conductor tracks 4 are exposed, but in practice the conductors not shown in the first wiring layer 3 can also be used, for example, in the interconnect semiconductor region provided in the semiconductor body 2. However, such conductor tracks are not critical to the present invention. After the contact window 8 is formed, the same conductive material as the material forming the conductor track 4, in this embodiment a layer 10 made of polycrystalline silicon, is deposited, and the second wiring layer of the conductor track 11 is deposited thereon. (9) is formed.

According to the invention, an auxiliary layer 12 of insulating material is provided on the insulating layer 5 before the contact window 8 is formed, and then the photoresist mask 6 is removed in the area of the contact window 8. The first opening 13 is etched into the auxiliary layer 12 by use thereof, and then the semiconductor body 2 is insulated from the insulating layer 5 not only for the conductive material but also for the insulating material of the auxiliary layer 12. The wet etching process, which can selectively etch the material, is performed to form a contact window 8 in the insulating layer 5.

Thus, a half-cell device comprising a semiconductor body 2 having a surface 1 provided with a multilayer wiring structure of conductor tracks 4 and 10 made of the same conductive material is obtained. In a given embodiment, the conductor tracks 4 and 10 of the two wiring layers 3 and 9 may be made of conductive polycrystalline silicon, but may also be made of aluminum, tungsten, or metal silicide, for example. Insulation layer 5 is silicon oxide, but other suitable materials may be silicon nitride and silicon oxide.

The opening 13 is introduced into the auxiliary layer 12 with a length and width that substantially matches the position and size of the opening 7 in the photoresist mask 6 used to define the position and size of the contact window 8. Can be etched. While etching the contact window 8 in the insulating layer 5 located below the auxiliary layer 12, the contact window 8 is larger in the insulating layer 5 than the opening 13 in the auxiliary layer 12. Is formed. At this time, the insulating layer 5 is removed in the contact window 8 below the edge 14 of the auxiliary layer 12. This contact window 8 is also filled below the edge 14 of the auxiliary layer 12 during the deposition of the conductive material layer 10 forming the second wiring layer 9. During formation of the second wiring layer 9 of the conductor track 11, it will be possible to form the conductor track 11 with a width substantially the same size as the width of the opening 13 etched in the auxiliary layer 12. Etching of the conductive layer 10 is stopped at the auxiliary layer 12, and the edge 14 of the auxiliary layer protects the underlying conductive material. If the opening 13 in the auxiliary layer 12 is given 0.5 μm in length and width, these conductor tracks 11 are etched, with photoresist capable of arranging with an error of ± 0.1 μm over the contact windows 8 formed. If a mask (not shown) is used, it is possible to form a conductor track with a width of only 0.7 μm on the auxiliary layer.

Preferably, the auxiliary layer 12 is deposited on the semiconductor body 2 in a chemical vapor deposition process. In this embodiment, for example, a silicon nitride layer of approximately 200 nm thickness is deposited by a CVD process, and a mixed gas of silane and ammonia is conducted through the wafer while the semiconductor body is heated to a temperature of approximately 900 ° C. The thus deposited layer 12 exhibits a substantially uniform thickness over the entire surface area. The openings 13 can be etched into such an auxiliary layer 12 by an anisotropic plasma etching, for example, by a conventional reactive ion etching process, so that these openings 13 are in the photoresist mask. Has a length and width substantially coincident with the length and width of the opening. This etching process has an etching selectivity lower than that of the wet etching process, but since the deposited layer 12 has a substantially uniform thickness over its entire surface area, the underlying layer 5 is etched for a long time. The contact window 13 can be etched into the auxiliary layer 12 without being exposed locally. The etching process may simply be stopped after the predetermined time determined by the test has elapsed, and thus does not significantly affect the insulating layer 5 located under the auxiliary layer 12.

5 and 6 show in schematic cross-sectional views some steps in the manufacture of a second semiconductor device in which the method according to the invention is used. In this embodiment, an auxiliary layer 15 made of silicon nitride less than 50 nm thick is deposited in a similar manner as the auxiliary layer 12. The opening 13 in the auxiliary layer 15 may be evenly isotropically etched, for example, with irritating phosphoric acid by a conventional wet etching process, which causes the opening 13 in the auxiliary layer 15 to be photoresist mask 6 Although made larger than the opening 7 in the interior, this expansion is limited. Since the isotropic etching process proceeds at substantially the same speed in the substantially horizontal and vertical directions, this expansion can be kept limited to the thickness of the auxiliary layer. As in the example described above, if the opening 7 in the photoresist layer 6 is given 0.5 μm in length and width, and the thickness of the auxiliary layer is less than 50 nm, then the length greater than 0.5 μm and less than 0.6 μm and An opening 13 having a width is created in the auxiliary layer 15. If the conductor track 11 can be provided with an accuracy of ± 0.1 μm, the conductor track should have a width larger than 0.7 μm and smaller than 0.8 μm to protect the contact window.

7 and 8 show, in schematic cross-section, several steps in the manufacture of a third semiconductor device in which the method according to the invention is used. The conductor track 16 of the first wiring layer 3 in this embodiment is preferably of the same material as the material of the auxiliary layer 14, in which the material of the insulating layer 5 can be selectively etched, in this embodiment. In this example it is provided on insulating sublayer 17, which is silicon nitride with a thickness of approximately 200 nm. At this time, the conductor track 16 of the first wiring layer 3 can be narrower than the contact window 8. The substrate 2 is protected by the insulating sublayer 17 during the etching of the contact window 8. Without such sublayers, the substrate can also be eroded by the etchant. The contact window 8 will have a length and width of approximately 0.9 μm using the photolithographic process mentioned above. In the absence of sublayers 17, the conductor tracks 16 located underneath these contact windows 8 should be at least 1.1 μm wide, but with the sublayers 17 it is possible to achieve even by lithographic processes. Can be as narrow as 0.5 μm.

9 shows a schematic cross-sectional view of several steps in the manufacture of a fourth semiconductor device in which the method according to the invention is used. This embodiment is almost identical to the embodiment given in FIGS. 7 and 8. The only difference is that the auxiliary layer 15 is a silicon nitride layer less than 50 nm thick. Also in this case, the conductor track 16 may have a width in which the contact window 8 is smaller than the size.

In the given embodiment, since the insulating layer 5 is deposited on the conductor tracks 4 and 16, the insulating layer 5 is provided on the conductor tracks 4 and 16 of the first wiring layer 3. In the following examples, this layer is formed by thermal oxidation of the conductor tracks. Very narrow conductor tracks may then be formed. For example, if an insulating silicon oxide layer of approximately 200 nm thickness is provided on a polycrystalline silicon track of 500 nm width and 200 nm thickness by thermal oxidation, the conductor track will be kept approximately 300 nm wide and approximately 100 nm thick. .

10 and 11 illustrate, in schematic cross-sectional views, several steps in the manufacture of a fifth semiconductor device in which the method according to the invention is used. In this embodiment, an insulating layer made of thermal silicon oxides 20 and 21 is provided in conductor tracks 18 and 19 made of polycrystalline silicon belonging to the first wiring layer 3. In this embodiment the conductor track 18 is approximately 200 nm thick, with an insulating layer of about 200 nm thick provided thereon, while the conductor track 19 is approximately 100 nm thick and about 100 nm thereon. A thick insulating layer is provided. This situation frequently occurs where the first wiring layer 3 comprises conductor tracks 18 and 19 of different thicknesses, and the insulating layers 20 and 21 provided on the conductor tracks 18 and 19 have different thicknesses. This situation is described herein with reference to the embodiment in which the insulating layers 20 and 21 are provided through oxidation of the conductor tracks 18 and 19, but in the above-described case where the insulating layer 5 is provided through deposition. A similar situation may occur in. Thus, problems may arise during the etching of the contact window 8 which locally exposes the conductor tracks 18 and 19 of the first wiring layer 3. This is because in the contact window 8, even in these positions where the insulating layer 19 is relatively thick, the etching process must continue until the conductor track 18 is exposed. In that case, the conductor tracks 19 are exposed to the etching process for a relatively long period even in a position where the insulating layer 21 is relatively thin. These conductor tracks 19 may then be etched above their thickness at such locations. This may cause interruption of the conductor track in the position where the conductor track 19 is also relatively thin. Thus, the contact window 18 is provided in the insulating layers 20 and 21 by a wet etching process capable of etching the insulating layer 20, 21 material selectively with respect to the conductor material. The wet etch process can provide etch selectivity that is high enough to avoid the above problem.

After the opening 13 is provided in the auxiliary layer 12, the contact window 8 is etched with the insulating layers 20 and 21, and the conductor track 11 of the second conductor track layer 9 is formed.

12, 13 and 14 show in schematic cross-section some steps in the manufacture of a sixth semiconductor device in which the method according to the invention is used. Narrow conductor tracks 22, 23 and 24, each consisting of polycrystalline silicon, each having a thickness of 100 nm, 75 nm, 50 nm and a width of 300 nm, 300 nm, 100 nm, respectively, belonging to the first wiring layer 3. In this embodiment, an insulating layer of thermal silicon oxides 25, 26, and 27 is provided on the sublayer 17 made of silicon nitride, each having a thickness of 200 nm, 100 nm, and 50 nm. An auxiliary layer 14 of silicon nitride with a thickness of less than 50 nm is also used in this case. After the photoresist mask 6 having the opening 7 is applied, the opening 15 is etched into the auxiliary layer 14. The opening 15 is etched by a wet etching process in this embodiment, but it is possible to do this also by a reactive ion etching process. Since the auxiliary layer 14 and the sublayer 17 are made of the same material, here silicon nitride, a portion 28 of the sublayer 17 near the conductor track 24 is etched. The sublayer 17 can prevent too much of its thickness from being etched in that the etching process is stopped after a predetermined duration predetermined by the test. After the opening 15 is etched into the auxiliary layer 14, the contact window 8 is etched into the insulating layers 25, 26 and 27. The sublayer near the conductor tracks 22 remains covered by the residue of the insulating layer 25 and the sublayers 17 near the other conductor tracks 23 and 24 are exposed. The second wiring layer 9 with the conductor track 11 is provided after etching the contact window 8. It can be seen that the contacts can be produced in this way with very narrow conductor tracks 22, 23 and 24 of the first wiring layer 3. FIG. 14 shows a cross sectional view taken on line B-B in FIG. 13. From this figure, it will be apparent that the conductor track 11 can be narrower than the contact window 8 as well for the very narrow conductor track 24.

Figures 15, 16 and 17 show, in schematic cross section, several steps in the manufacture of a seventh semiconductor device in which the method according to the invention is used. In this embodiment the first wiring layer 3 comprises overlapping conductor tracks 29 and 30 provided on a sublayer made of silicon nitride 17. Both tracks are provided with insulating layers 31 and 32 made of thermally grown silicon nitride. In such cases, the method according to the invention can also be usefully applied. The contact window 8 may be etched after providing a photoresist mask 6 having a silicon nitride auxiliary layer 14 and an opening 7 less than 50 nm thick. This can be done here with a reactive ion etch process. A part 23 of the sublayer 17 exposed by this etching process is etched through a small part of their thickness. A portion 34 of the auxiliary layer 14 is here intact. However, the conductive layer 10 forming the conductor track 11 of the second wiring layer has excellent contact with the overlapping conductor tracks 28 and 29, as is apparent from FIG. FIG. 17 shows a cross sectional view taken on line C-C in FIG. 16. It will be clear from this figure that the conductor track 11 can also be narrower than the contact window 8 even with this complicated first wiring layer with overlapping conductor tracks 28, 29.

Claims (7)

A semiconductor device manufacturing method comprising a semiconductor body having a surface on which a multilayer wiring structure of conductor tracks made of the same conductive material is formed, the method comprising: After forming a first wiring layer of the conductor track on the surface, it is covered with an insulating layer, and the material of the insulating layer can be selectively etched with respect to the conductive material. A contact window is formed in the insulation layer by a wet etching process, the contact window locally exposing at least a portion of the conductor track of the first wiring layer, and then the surface. A layer of the conductive material is deposited thereon, and a second wiring layer of a conductor track is formed in the conductive material. In the method of manufacturing the semiconductor device, Forming an auxiliary layer of an insulating material on the insulating layer before the contact window is formed; Etching openings into the auxiliary layer in the contact window region; Forming the contact window in the insulating layer by wet etching the semiconductor body so that the insulating material of the insulating layer can be selectively etched not only with respect to the conductive material but also with the insulating material of the auxiliary layer; Forming conductor tracks of the second wiring layer having a width substantially the same size as the width of the opening etched in the auxiliary layer. According to claim 1, And the auxiliary layer is deposited over the entire surface of the semiconductor body by a chemical vapor deposition process. The method of claim 2, And wherein the auxiliary layer is deposited on the entire surface of the semiconductor body to a thickness of less than 50 nm. The method according to any one of claims 1 to 3, And wherein the conductor track of the first wiring layer is provided on an insulating sub-layer on which the material of the insulating layer can be selectively etched. The method of claim 4, wherein And the conductor track of the first wiring layer is provided on an insulating sublayer made of the same material as that of the auxiliary layer. The method of claim 5, And the sublayer and auxiliary layer are formed of silicon nitride. The method of claim 5, Wherein the conductor track of the first wiring layer is formed of polycrystalline silicon, and the insulating layer on these conductors is formed through oxidation of the polycrystalline silicon.