KR900005565A - 개선된 패턴 형성방법 - Google Patents

개선된 패턴 형성방법 Download PDF

Info

Publication number
KR900005565A
KR900005565A KR1019890013017A KR890013017A KR900005565A KR 900005565 A KR900005565 A KR 900005565A KR 1019890013017 A KR1019890013017 A KR 1019890013017A KR 890013017 A KR890013017 A KR 890013017A KR 900005565 A KR900005565 A KR 900005565A
Authority
KR
South Korea
Prior art keywords
film
layer
substrate
pattern forming
forming method
Prior art date
Application number
KR1019890013017A
Other languages
English (en)
Other versions
KR930005943B1 (ko
Inventor
가츠야 오쿠무라
도오루 와타나베
마사미 와타세
Original Assignee
아오이 죠이치
가부시키가이샤 도시바
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 아오이 죠이치, 가부시키가이샤 도시바 filed Critical 아오이 죠이치
Publication of KR900005565A publication Critical patent/KR900005565A/ko
Application granted granted Critical
Publication of KR930005943B1 publication Critical patent/KR930005943B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors

Abstract

내용 없음

Description

개선된 패턴 형성방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제3도(a) 내지 제3도(d)는 본 발명의 제1실시예를 설명하기 위한 단면도,
제4도(a) 내지 제4도(d)는 본 발명의 제2실시예를 설명하기 위한 단면도.

Claims (10)

  1. 제1주표면을 갖는 기판(30)의 상기 제1주표면상에 제1막(31)을 형성하는 단계, 이 제1막(31)상에 제2막(33)을 형성하는 단계, 제1패턴화막(33a,33b)을 형성시키기 위해 상기 제2막(33)을 선택적으로 제거하는 단계, 상기 제1막(31)의 감광부상에 제3막(35)을 선택적으로 형성시키기 위해 제1패턴화막(33a,33b)을 갖는 기판(30)을 선택적으로 형성시키기 위해 제1패턴화막(33a,33b)을 갖는 기판(30)을 소정 용액 속에 담그어 주는 단계, 상기 제1패턴화막(33a,33b)을 제거하는 단계 및, 상기 제3막(35)을 마스크로 해서 상기 제1막(31)을 에칭하는 단계로 이루어진 것을 특징으로 하는 패턴형성방법.
  2. 제1항에 있어서, 단차부(34)를 갖는 상기 기판(30)상에 이단차부(34)가 덮여지게끔 제1막(31)을 형성하도록 된 것을 특징으로 하는 패턴형성방법.
  3. 제1항에 있어서, 상기 제1막(31)이 금속막이고, 상기 제2막(33)이 포토레지스트막인 것을 특징으로 하는 패턴형성방법.
  4. 제1항에 있어서, 상기 제3막(35)이 유리막인 것을 특징으로 하는 패턴형성방법.
  5. 제4항에 있어서, 상기 제3막(35)을 SOG법(Spin On Glass법)으로 형성하도록 된 것을 특징으로 하는 패턴형성방법.
  6. 제1항에 있어서, 상기 제2막(33)을 형성하기 전에 상기 제1막(31)이 덮여지도록 제4막(53)을 형성하는 단계와 상기 제3막(35)을 마스크로 해서 제4막(53)을 에칭하는 단계를 구비하여 이루어진 것을 특징으로 하는 패턴형성방법.
  7. 제1항에 있어서, 상기 제2막(33)을 친수성(親水性)을 갖는 물질로 형성하고, 상기 기판(30)을 담그기 전에 소수성(疎水性)을 갖는 물질로 상기 제2막(33)을 덮는 단계를 구비하여 이루어진 것을 특징을 하는 패턴형성방법.
  8. 제1주표면을 갖는 기판(30,31)을 준비하는 단계와, 이 제1주표면상에 제1막(33)을 형성하는 단계, 제1패턴화막(33a,33b)을 형성시키기 위해 상기 제1막(33)을 선택적으로 제거하는 단계, 상기 제1막(33)이 제거된 제1주표면상에 제2막(35)을 선택적으로 형성시키기 위해 제1패턴화막(33a,33b)를 갖는 기판(30,31)을 소정용액속에 담그어 주는 단계, 상기 제1패턴화막(33a,33b)을 제거하는 단계 및 상기 제2막(35)을 마스크로 해서 상기 기판(30,31)을 에칭하는 단계로 이루어진 것을 특징으로 하는 패턴형성방법.
  9. 제8항에 있어서, 상기 기판(30,31)이 반도체기판인 것을 특징으로 하는 패턴성형방법.
  10. 제8항에 있어서, 상기 제1막(33)을 친수성을 갖는 물질로 형성하고, 상기 기판(30,31)을 담그기 전에 소수성을 갖는 물질로 상기 제1막(33)을 덮는 단계를 구비하여 이루어진 것을 특징으로 하는 패턴형성방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019890013017A 1988-09-08 1989-09-08 개선된 패턴형성방법 KR930005943B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP63-223503 1988-09-08
JP88-223503 1988-09-08
JP63223503A JP2606900B2 (ja) 1988-09-08 1988-09-08 パターン形成方法

Publications (2)

Publication Number Publication Date
KR900005565A true KR900005565A (ko) 1990-04-14
KR930005943B1 KR930005943B1 (ko) 1993-06-29

Family

ID=16799165

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890013017A KR930005943B1 (ko) 1988-09-08 1989-09-08 개선된 패턴형성방법

Country Status (5)

Country Link
US (1) US4954218A (ko)
EP (2) EP0630044B1 (ko)
JP (1) JP2606900B2 (ko)
KR (1) KR930005943B1 (ko)
DE (2) DE68925398T2 (ko)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3255942B2 (ja) * 1991-06-19 2002-02-12 株式会社半導体エネルギー研究所 逆スタガ薄膜トランジスタの作製方法
IT1248534B (it) * 1991-06-24 1995-01-19 Sgs Thomson Microelectronics Procedimento per la realizzazione di strutture di calibrazione particolarmente per la taratura di macchine di misura del disallineamento in circuiti integrati in genere.
US5390412A (en) * 1993-04-08 1995-02-21 Gregoire; George D. Method for making printed circuit boards
US5536603A (en) * 1993-12-21 1996-07-16 Kabushiki Kaisha Toshiba Phase shift mask and method of fabricating the same
JPH08262289A (ja) * 1995-03-20 1996-10-11 Sumitomo Electric Ind Ltd チューブ集合光ケーブル
US5994211A (en) * 1997-11-21 1999-11-30 Lsi Logic Corporation Method and composition for reducing gate oxide damage during RF sputter clean
US6197644B1 (en) * 1998-11-06 2001-03-06 Advanced Micro Devices, Inc. High density mosfet fabrication method with integrated device scaling
US20040209190A1 (en) * 2000-12-22 2004-10-21 Yoshiaki Mori Pattern forming method and apparatus used for semiconductor device, electric circuit, display module, and light emitting device
US6489237B1 (en) 2001-12-04 2002-12-03 Taiwan Semiconductor Manufacturing Company Method of patterning lines in semiconductor devices
KR100455293B1 (ko) * 2002-05-15 2004-11-06 삼성전자주식회사 친수성 영역과 소수성 영역으로 구성되는 생물분자용어레이 판의 제조방법
US7205228B2 (en) * 2003-06-03 2007-04-17 Applied Materials, Inc. Selective metal encapsulation schemes
JP3828514B2 (ja) 2003-06-30 2006-10-04 Ｔｄｋ株式会社 ドライエッチング方法及び情報記録媒体の製造方法
CN1914558A (zh) * 2004-02-11 2007-02-14 国际商业机器公司 混合碱用于提高铬或敏感基材上的图案化抗蚀剂分布的应用
US20100204057A1 (en) * 2009-02-10 2010-08-12 Samsung Electronics Co., Ltd. Substrate for microarray, method of manufacturing microarray using the same and method of obtaining light data from microarray
CN102148202B (zh) * 2010-02-09 2016-06-08 精材科技股份有限公司 晶片封装体及其形成方法
WO2013100061A1 (ja) * 2011-12-28 2013-07-04 株式会社ニコン エンコーダ、エンコーダ用スケールの製造方法、エンコーダの製造方法及び駆動装置

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52136590A (en) * 1976-05-11 1977-11-15 Matsushita Electric Ind Co Ltd Production of semiconductor device
FR2354633A1 (fr) * 1976-06-11 1978-01-06 Ibm Procede pour realiser des configurations metalliques sur un substrat isolant
JPS57166035A (en) * 1981-04-03 1982-10-13 Citizen Watch Co Ltd Forming method for mask for dry etching
JPS57196744A (en) * 1981-05-29 1982-12-02 Nippon Sheet Glass Co Ltd Surface treatment of glass containing alkali metal
US4496419A (en) * 1983-02-28 1985-01-29 Cornell Research Foundation, Inc. Fine line patterning method for submicron devices
JPS60214532A (ja) * 1984-04-11 1985-10-26 Nippon Telegr & Teleph Corp <Ntt> パタ−ン形成方法
US4674174A (en) * 1984-10-17 1987-06-23 Kabushiki Kaisha Toshiba Method for forming a conductor pattern using lift-off
US4576834A (en) * 1985-05-20 1986-03-18 Ncr Corporation Method for forming trench isolation structures
US4624749A (en) * 1985-09-03 1986-11-25 Harris Corporation Electrodeposition of submicrometer metallic interconnect for integrated circuits
JPS6450425A (en) * 1987-08-20 1989-02-27 Toshiba Corp Formation of fine pattern
JPH01140629A (ja) * 1987-11-26 1989-06-01 Sharp Corp パターン形成方法

Also Published As

Publication number Publication date
US4954218A (en) 1990-09-04
EP0630044A2 (en) 1994-12-21
EP0630044A3 (en) 1995-03-29
DE68925398D1 (de) 1996-02-22
EP0358350B1 (en) 1996-01-10
EP0358350A3 (en) 1991-10-16
EP0358350A2 (en) 1990-03-14
EP0630044B1 (en) 1998-11-18
DE68928856T2 (de) 1999-05-20
DE68925398T2 (de) 1996-07-25
JP2606900B2 (ja) 1997-05-07
KR930005943B1 (ko) 1993-06-29
JPH0272624A (ja) 1990-03-12
DE68928856D1 (de) 1998-12-24

Similar Documents

Publication Publication Date Title
KR900005565A (ko) 개선된 패턴 형성방법
KR880004543A (ko) 집적회로 제작방법
KR840006728A (ko) 집적회로 제조방법
KR910020802A (ko) 마스크의 제작방법
JPS57183030A (en) Manufacture of semiconductor device
KR960014056B1 (ko) 감광막 패턴 형성방법
KR970008372A (ko) 반도체장치의 미세 패턴 형성방법
KR910008801A (ko) 반도체장치의 제조방법
KR920004910B1 (ko) 반도체 장치의 최소 접속창 형성방법
KR950015609A (ko) 포토마스크 패턴 형성방법
KR890011047A (ko) 차광성 박막의 에칭방법
JPS5696845A (en) Manufacture of semiconductor device
KR950021154A (ko) 반도체 소자의 광역단차 평탄화 방법
JPS55130140A (en) Fabricating method of semiconductor device
KR930001396A (ko) 금속 배선 제조 방법
JPS57118641A (en) Lifting-off method
KR950012848A (ko) 반도체 소자의 제조 방법
KR950006981A (ko) 포토레지스트패턴 형성방법
KR960026231A (ko) 텅스텐 플러그 제조방법
KR950025486A (ko) 반도체소자의 미세패턴 형성방법
KR950021047A (ko) 포토레지스트의 미세패턴 형성방법
KR970018041A (ko) 반도체 소자의 미세 콘택홀 형성 방법
KR940002957A (ko) 감광막 패턴 형성방법
KR900001024A (ko) Sram의 제조방법
KR890007384A (ko) 반도체 다층 배선장치의 제조방법

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20030530

Year of fee payment: 11

LAPS Lapse due to unpaid annual fee