IT1248534B - Procedimento per la realizzazione di strutture di calibrazione particolarmente per la taratura di macchine di misura del disallineamento in circuiti integrati in genere. - Google Patents
Procedimento per la realizzazione di strutture di calibrazione particolarmente per la taratura di macchine di misura del disallineamento in circuiti integrati in genere.Info
- Publication number
- IT1248534B IT1248534B ITMI911727A ITMI911727A IT1248534B IT 1248534 B IT1248534 B IT 1248534B IT MI911727 A ITMI911727 A IT MI911727A IT MI911727 A ITMI911727 A IT MI911727A IT 1248534 B IT1248534 B IT 1248534B
- Authority
- IT
- Italy
- Prior art keywords
- calibration
- misalignment
- procedure
- general
- integrated circuits
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
- G03F7/70605—Workpiece metrology
- G03F7/70616—Monitoring the printed patterns
- G03F7/70633—Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/0035—Multiple processes, e.g. applying a further resist layer on an already in a previously step, processed pattern or textured surface
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/975—Substrate or mask aligning feature
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Length Measuring Devices With Unspecified Measuring Means (AREA)
Abstract
Procedimento per la realizzazione di strutture di calibrazione particolarmente per la taratura di macchine di misura del disallineamento in circuiti integrati in genere, la peculiarità del quale consiste nel fatto di realizzare strutture di calibrazione che presentano il disallineamento di uno strato rispetto ad un altro strato imposto di ampiezza nota mediante un'unica mascheratura.
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
ITMI911727A IT1248534B (it) | 1991-06-24 | 1991-06-24 | Procedimento per la realizzazione di strutture di calibrazione particolarmente per la taratura di macchine di misura del disallineamento in circuiti integrati in genere. |
GB9212413A GB2257804B (en) | 1991-06-24 | 1992-06-11 | Photolithographic process for manufacturing calibration strctures |
JP4164610A JPH05198644A (ja) | 1991-06-24 | 1992-06-23 | 校正構造の製造方法 |
FR9208054A FR2678108B1 (fr) | 1991-06-24 | 1992-06-23 | Procede de fabrication de structures d'etalonnage, en particulier pour l'etalonnage de machines de mesure d'alignement dans des circuits integres. |
US08/149,707 US5332470A (en) | 1991-06-24 | 1993-11-09 | Process for manufacturing calibration structures particularly for the calibration of machines for measuring alignment in integrated circuits in general |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
ITMI911727A IT1248534B (it) | 1991-06-24 | 1991-06-24 | Procedimento per la realizzazione di strutture di calibrazione particolarmente per la taratura di macchine di misura del disallineamento in circuiti integrati in genere. |
Publications (3)
Publication Number | Publication Date |
---|---|
ITMI911727A0 ITMI911727A0 (it) | 1991-06-24 |
ITMI911727A1 ITMI911727A1 (it) | 1992-12-24 |
IT1248534B true IT1248534B (it) | 1995-01-19 |
Family
ID=11360186
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ITMI911727A IT1248534B (it) | 1991-06-24 | 1991-06-24 | Procedimento per la realizzazione di strutture di calibrazione particolarmente per la taratura di macchine di misura del disallineamento in circuiti integrati in genere. |
Country Status (5)
Country | Link |
---|---|
US (1) | US5332470A (it) |
JP (1) | JPH05198644A (it) |
FR (1) | FR2678108B1 (it) |
GB (1) | GB2257804B (it) |
IT (1) | IT1248534B (it) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5401691A (en) * | 1994-07-01 | 1995-03-28 | Cypress Semiconductor Corporation | Method of fabrication an inverse open frame alignment mark |
US5952247A (en) * | 1994-11-23 | 1999-09-14 | Intel Corporation | Method of accessing the circuitry on a semiconductor substrate from the bottom of the semiconductor substrate |
US5611855A (en) * | 1995-01-31 | 1997-03-18 | Seh America, Inc. | Method for manufacturing a calibration wafer having a microdefect-free layer of a precisely predetermined depth |
US5545570A (en) * | 1995-09-29 | 1996-08-13 | Taiwan Semiconductor Manufacturing Company | Method of inspecting first layer overlay shift in global alignment process |
US5599464A (en) * | 1995-10-06 | 1997-02-04 | Vlsi Standards, Inc. | Formation of atomic scale vertical features for topographic instrument calibration |
US5936311A (en) * | 1996-12-31 | 1999-08-10 | Intel Corporation | Integrated circuit alignment marks distributed throughout a surface metal line |
US5904486A (en) * | 1997-09-30 | 1999-05-18 | Intel Corporation | Method for performing a circuit edit through the back side of an integrated circuit die |
US5998226A (en) * | 1998-04-02 | 1999-12-07 | Lsi Logic Corporation | Method and system for alignment of openings in semiconductor fabrication |
KR100295049B1 (ko) * | 1998-07-23 | 2001-11-30 | 윤종용 | 위상반전마스크제조방법 |
US6146910A (en) * | 1999-02-02 | 2000-11-14 | The United States Of America, As Represented By The Secretary Of Commerce | Target configuration and method for extraction of overlay vectors from targets having concealed features |
US6358860B1 (en) | 1999-10-07 | 2002-03-19 | Vlsi Standards, Inc. | Line width calibration standard manufacturing and certifying method |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4307179A (en) * | 1980-07-03 | 1981-12-22 | International Business Machines Corporation | Planar metal interconnection system and process |
US4576900A (en) * | 1981-10-09 | 1986-03-18 | Amdahl Corporation | Integrated circuit multilevel interconnect system and method |
US4888450A (en) * | 1981-12-11 | 1989-12-19 | At&T Bell Laboratories | Circuit board fabrication leading to increased capacity |
US4731318A (en) * | 1985-02-26 | 1988-03-15 | Societe Pour L'etude Et La Fabrication Des Circuits Integres Speciaux - E.F.C.I.S. | Integrated circuit comprising MOS transistors having electrodes of metallic silicide and a method of fabrication of said circuit |
JPH0682727B2 (ja) * | 1986-02-18 | 1994-10-19 | ホ−ヤ株式会社 | 検査用基板とその製造方法 |
GB2204992A (en) * | 1987-05-05 | 1988-11-23 | British Telecomm | Bipolar transistor |
DE68921995T2 (de) * | 1988-01-19 | 1995-12-07 | Nat Semiconductor Corp | Verfahren zum Herstellen eines Polysiliciumemitters und eines Polysiliciumgates durch gleichzeitiges Ätzen von Polysilicium auf einem dünnen Gateoxid. |
JP2606900B2 (ja) * | 1988-09-08 | 1997-05-07 | 株式会社東芝 | パターン形成方法 |
EP0369053B1 (de) * | 1988-11-17 | 1994-03-02 | International Business Machines Corporation | Verfahren zur Herstellung von Masken mit Strukturen im Submikrometerbereich |
EP0416809A3 (en) * | 1989-09-08 | 1991-08-07 | American Telephone And Telegraph Company | Reduced size etching method for integrated circuits |
US4996167A (en) * | 1990-06-29 | 1991-02-26 | At&T Bell Laboratories | Method of making electrical contacts to gate structures in integrated circuits |
IT1251393B (it) * | 1991-09-04 | 1995-05-09 | St Microelectronics Srl | Procedimento per la realizzazione di strutture metrologiche particolarmente per l'analisi dell'accuratezza di strumenti di misura di allineamento su substrati processati. |
-
1991
- 1991-06-24 IT ITMI911727A patent/IT1248534B/it active IP Right Grant
-
1992
- 1992-06-11 GB GB9212413A patent/GB2257804B/en not_active Expired - Fee Related
- 1992-06-23 JP JP4164610A patent/JPH05198644A/ja not_active Withdrawn
- 1992-06-23 FR FR9208054A patent/FR2678108B1/fr not_active Expired - Lifetime
-
1993
- 1993-11-09 US US08/149,707 patent/US5332470A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPH05198644A (ja) | 1993-08-06 |
GB2257804A (en) | 1993-01-20 |
GB2257804B (en) | 1995-01-04 |
US5332470A (en) | 1994-07-26 |
ITMI911727A0 (it) | 1991-06-24 |
ITMI911727A1 (it) | 1992-12-24 |
FR2678108B1 (fr) | 1996-09-06 |
FR2678108A1 (fr) | 1992-12-24 |
GB9212413D0 (en) | 1992-07-22 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
0001 | Granted | ||
TA | Fee payment date (situation as of event date), data collected since 19931001 |
Effective date: 19970628 |