GB2204992A - Bipolar transistor - Google Patents
Bipolar transistor Download PDFInfo
- Publication number
- GB2204992A GB2204992A GB08710618A GB8710618A GB2204992A GB 2204992 A GB2204992 A GB 2204992A GB 08710618 A GB08710618 A GB 08710618A GB 8710618 A GB8710618 A GB 8710618A GB 2204992 A GB2204992 A GB 2204992A
- Authority
- GB
- United Kingdom
- Prior art keywords
- base
- window
- contact
- forming
- dielectric layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000000034 method Methods 0.000 claims abstract description 7
- 239000004065 semiconductor Substances 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 claims 1
- 238000009792 diffusion process Methods 0.000 description 2
- 101100008046 Caenorhabditis elegans cut-2 gene Proteins 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42304—Base electrodes for bipolar transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Bipolar Transistors (AREA)
Abstract
A method for providing the base contacts of a non-self-aligned bipolar transistor comprises forming a base window in a dielectric layer 2 to produce the base region 4; forming a second dielectric layer 5 over the layer 2 and the base region 4; and then forming a contact window in the second layer 5 to expose part of the top surface of the layer 2 and that part of the base region adjacent the periphery of the base window. This enables the size of the base to be reduced by doing away with the tolerance otherwise necessary for the contact window positions. <IMAGE>
Description
BIPOLAR TRANSISTORS
The present invention relates to bipolar transistors and in particular to the arrangement of the base contacts in such transistors.
In high speed bipolar integrated circuits and elsewhere there is a continuing desire to increase the operating speed of bipolar transistors. One way in which the operating speed can generally be increased is by reducing the area of the base region, since the maximum oscillation frequency ##mar. at which the unilateral or power gain becomes unity) is inversely proportional to the square root of the capacitance between the base and the collector (which of course is proportional to the area of the base).
However although small base areas are desirable from the ps-t of view of increasing operating speed, there are several constraints which limit the extent to which the base size can be reduced. Notable among these constraints, at least for non-self-aligned processes, is the fact that base contacts have to be defined within the base window. Since separate masks are used to define the position of the base contacts and that of the base window, the position of the base contacts within the base window can only be guaranteed as precisely as the relevant alignment tolerances allow.
Allowance is made for these tolerances by placing the base contacts well within the base window, so that even with a worst case misalignment the base contact conductor does not have to accommodate too great a step height.
Unfortunately this arrangelent, which appears to be unlversally used, means that in order to acco=av'a ~ the alignment tolerances the base area has to be larger than is otherwise necessary, despite the well known desireability of reducing base area.
The present invention seeks to overcome these disadvantages of prior art arrangements.
According to the present invention there is provided a method of awaking a bipolar transistor, the method including the steps of: a) forking a base window through a first dielectric layer
over a seniconductor substrate; b) forming a base region in said semiconductor through
said window; c) forming a second dielectric layer over said first
layer and said base region d) forming an opening for a base contact through said
second dielectric layer, the opening exposing the base
region at the foot of the sidewall of the base window
and the top surface of the first dielectric layer
adjacent the periphery of the base window.
Embodiments of the invention will now be described with reference to the accompanying drawings in which:
Figure 1 shows a base contact arrangement according to
the invention;
Figure 2 a) shows a correctly aligned conventional
base contact arrangement;
figure 2 b) shows the effect of incorrect positioning
and alignment on a conventional base contact
arrangement.
Figure 3 a) shows undesirable direct contact between
the base contacts and the collector;
Figure 3 b) shows how the undesirable contact of
Figure 3 a) can be avoided.
An arrangement of the base contacts according to the invention is shown in Figure 1 and is contrasted with the prior art arrangements of Figure 2a (correctly aligned) and 2b (wrongly positioned and misaligned). In the
Figures the active semiconductor region is deRignatcss 1; the field oxide, which is about 0.5 pm thick, is 2; the dielectric layer, typically oxide, through which the base contacts are cut, is 5; and the base region formed by implanting or diffusing a dopant species through the base window is designated 4.
In the prior art arrangesent shown in Figure 2a the base contact windows 6 and by are positioned well within (about 2 pm) the periphery of the base window. The reason for this positioning is, as indicated above, to avoid the creation of excessively high step heights, shown as Y in
Figure 2b, which can occur when mask alignment tolerances result in a base contact window being cut too close to the foot of the dielectric layer 5 formed over the field oxide.
In Figure 1 is shown the equivalent arrangement according to the invention. The base contact spacing, field oxide thickness and base dielectric thickness are the same as in Figures 2a and 2b, but by using larger base contact windows which will over 2 > theFeriperv of the base window within-the permitted range of misalignment it is possible to dramatically reduce the size of the base region. As can be seen, the maximum step height in Figure 1 is dictated by the thickness of the field oxide, and is substantially the same as that shown in Figure 2a.
Typically the base contact windows only need to be made about 50t wider than the equivalent conventional windows.
Of course the alignment tolerances, the minimum acceptable base contact area and the base contact seperation need to be borne in mind when determining the permissible reduction in base region size, the size of the base contacts being such that their overlap within the base window is always sufficient (within the acceptable range of misalignment) to provide no less than the minimum acceptable base contact area.
In a particular conventional process, the base contact windows were cut 2 ym wide and an alignment tolerance of 1 um allowed between the base window mask and the base contact mask (the separation 7 between the edge of the base window and the adjacent edge of the base contact window typically being designed to be 2 pea). When modified according to the teachings of the present invention the width of the base contact was increased to 3 um and the base window width reduced by 2 pa on each side.
One problem which could conceivably arise with the base contact arrangement according to the present invention is the incidence of short circuits between the base contact and the collector. Such short circuits might arise if the base implant/diffusion does not spread laterally sufficiently and/or if there is over etching of the beee contact windows, as shown in Figure 3a. Although this situation is not likely to occur, it is possible to ensure that it does not by forcing diffused base contacts, as shown in Figure 3b. Since the diffusions for the base contacts are formed through the base contact windows, their lateral spread ensures that the base contacts do not contact the collector region directly.
Claims (4)
1. A method of making a bipolar transistor, the
method including the steps of:
a) forming a base window through a first dielectric
layer over a semiconductor substrate;
b) forming a base region in said semiconductor
through said window;
c) forming a second dielectric layer over said first
layer and said base region;
d) forming an opening for a base contact through
said second dielectric layer, the opening exposing the
base region at the foot of the sidewall of the base
window and the top surface of the first dielectric
layer adjacent the periphery of the base window.
2. A method as claimed in claim 1, comprising the
additional step of forming in the base region a more
heavily doped contact region by diffusing or
implanting through the base contact opening.
3. A bipolar transistor wherein the base contact or
contacts contact the base region at the periphery of
the base window.
4. A bipolar transistor wherein the base contact or
contacts overlap the periphery of the base window, the
base region being contacted at the periphery of the
base window.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB08710618A GB2204992A (en) | 1987-05-05 | 1987-05-05 | Bipolar transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB08710618A GB2204992A (en) | 1987-05-05 | 1987-05-05 | Bipolar transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB8710618D0 GB8710618D0 (en) | 1987-06-10 |
| GB2204992A true GB2204992A (en) | 1988-11-23 |
Family
ID=10616848
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB08710618A Withdrawn GB2204992A (en) | 1987-05-05 | 1987-05-05 | Bipolar transistor |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2204992A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2678108A1 (en) * | 1991-06-24 | 1992-12-24 | Sgs Thomson Microelectronics | Method of manufacturing calibration structures, in particular for calibrating machines for measuring alignment in integrated circuits |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2014361A (en) * | 1977-12-26 | 1979-08-22 | Tokyo Shibaura Electric Co | Method of producing semiconductor devices |
| GB2047960A (en) * | 1979-04-20 | 1980-12-03 | Philips Nv | Bipolar transistor manufacture |
| US4512076A (en) * | 1982-12-20 | 1985-04-23 | Raytheon Company | Semiconductor device fabrication process |
| EP0180256A1 (en) * | 1984-09-18 | 1986-05-07 | Koninklijke Philips Electronics N.V. | Method of manufacturing contacts on a semiconductor device |
-
1987
- 1987-05-05 GB GB08710618A patent/GB2204992A/en not_active Withdrawn
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2014361A (en) * | 1977-12-26 | 1979-08-22 | Tokyo Shibaura Electric Co | Method of producing semiconductor devices |
| GB2047960A (en) * | 1979-04-20 | 1980-12-03 | Philips Nv | Bipolar transistor manufacture |
| US4512076A (en) * | 1982-12-20 | 1985-04-23 | Raytheon Company | Semiconductor device fabrication process |
| EP0180256A1 (en) * | 1984-09-18 | 1986-05-07 | Koninklijke Philips Electronics N.V. | Method of manufacturing contacts on a semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2678108A1 (en) * | 1991-06-24 | 1992-12-24 | Sgs Thomson Microelectronics | Method of manufacturing calibration structures, in particular for calibrating machines for measuring alignment in integrated circuits |
Also Published As
| Publication number | Publication date |
|---|---|
| GB8710618D0 (en) | 1987-06-10 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |