JPS6140145B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION In bipolar integrated circuit manufacturing, a method of forming an isolation region using an insulating material, particularly silicon oxide, increases the degree of integration and reduces parasitic capacitance compared to a method of forming an isolation region using a PN junction. It is known to be effective. When forming a normal NPN transistor using a silicon oxide isolation method, the emitter region is at least partially adjacent to silicon oxide (oxide film), and other regions are also at least partially adjacent to the oxide film. This is called an isoplanar or wall emitter, and it is possible to manufacture extremely small transistors. The present invention aims to improve the performance of integrated circuits manufactured using wall emitters.

The technology of the present invention is effective in preventing collector-emitter short circuits that tend to occur when manufacturing NPN transistors with a wall-emitter structure, and improves the controllability of the active base junction depth. properties, specifically hfe
When manufacturing high-speed logic elements with improved characteristics, it is possible to reduce the number of steps by two compared to the mask alignment process using the conventional technology. A conventional method for manufacturing a semiconductor device is shown in FIGS. 1A to 1E.
Shown below. 1A to 1E, 1 is a semiconductor substrate, 2 is an N ⁺ type buried layer, 3 is a P ⁺ type pre-isolation region, 4, 4A, 4B are N type epitaxial layers, 5 is an oxide film, 6 is a nitride film, 7 is a groove provided in the isolation region, 8 is an oxide film, 9 is a raised part of the oxide film, 10 is an edge portion of the oxide film, 11 is a deep collector region, and 12 is an uncircumcised region. An active base region, 13 is an active base region, 14 is an emitter region, 15 is a collector region, and 16 is an end of the emitter and base regions.

First, as shown in FIG. 1A, a P-type semiconductor substrate 1 is
First, an N ⁺ type buried layer 2 is formed, and then a P ⁺ type pre-isolation region 3 is formed. This pre-isolation region 3, together with a part of the insulating oxide that will be formed by performing oxidation treatment later,
This is for forming a separation region. Next, after removing the oxide over the entire surface, an N-type epitaxial layer 4 is deposited on the semiconductor substrate 1. Next, a buffer oxide film 5 with a thickness of, for example, 700 Å is formed on the surface of the epitaxial layer 4, and a nitride film 6 serving as an oxidation-resistant mask is deposited on the oxide film 5, and then the oxide film and nitride film in the isolation region are removed. After peeling off and forming an opening, the semiconductor substrate is etched to form grooves 7 so that the semiconductor substrate after oxidation treatment becomes substantially flat.

When a semiconductor substrate having such a structure is subjected to oxidation treatment in an oxidizing atmosphere, an isolation region is formed (FIG. 1B). As the volume increases with oxidation, groove 7
is completely filled, and the oxide that forms in this area reaches a level approximately equal to the height of the epitaxial layer under the deposited mask. Since the oxidation effect also occurs laterally from the sidewalls of the groove 7, ridges 9 of the oxide film are formed even in areas where the epitaxial layer is present at its original thickness due to the increase in volume caused by the oxidation. As is well known, oxygen also diffuses laterally from the edges of the oxide layer, so that oxidation also occurs under the oxide film 5. As a result of the oxidation of the semiconductor substrate below the oxide film, edge portions 10 are formed in each of the oxide films 5.

Next, first, the nitride film 6 is removed, and after further oxidation treatment is performed to increase the thickness of the oxide film 5, a high concentration N ⁺ type diffusion region for reducing collector resistance, that is, a deep collector region 11 is provided in the region 4B. (Figure 1C). Thereafter, first, a heavily doped P ⁺ type region for reducing base resistance, that is, an inactive base region 12 is formed in the region 4A. Next, after forming the active base region 13, drive-in is performed which also serves as oxidation treatment to obtain a mask oxide film for emitter diffusion (FIG. 1D).

After that, windows are formed in the emitter and collector regions, and then the emitter region 14 and the collector region 15 are formed. At this time, in the process of opening the base region and the emitter region twice, the bird's beak at the part where the elements are in contact becomes shorter, and there is a risk that the emitter region will diffuse outside the base diffusion region, and the collector・Causes emitter short circuit.

This will be discussed in a little more detail in FIGS. 2A-2C, which are enlarged views of the emitter and end portions 16 of the base region.

In FIGS. 2A to 2C, 101 is a collector, 102 is an oxide film, 103 is an inert base, 1
04 is the resist, 105 is the edge of the isolation oxide film,
106 resist, 107 active base, 108
109 is an emitter, and 109 is an oxide film termination. Second
Figure A shows the state after opening the active base region. P ⁺ type inert base 1 to N type collector 101
After forming 03 and forming an oxide film on the surface which also serves as a drive-in, an active base pattern is formed. At this time, a larger resist pattern 104 is formed so that the size of the region to be diffused is defined by the thick film termination position 105 of the isolation oxide film. If the oxide film is then etched and an active base window is opened, the result will be as shown in FIG. 2A. Next, an active base 107 is formed, and an oxide film that can serve as an anti-diffusion mask for the emitter is simultaneously formed on the surface, resulting in a cross-sectional shape as shown in FIG. 2B. Next, when the oxide film is removed using the emitter resist pattern 106, the gradually thinning region of the bird's beak is also etched at the same time, and depending on the degree of etching, the edge of the emitter opening may overlap the base diffusion region. There is a danger of it spreading further. FIG. 2C shows such a case, and the emitter 108 and the collector 101 are short-circuited at the oxide film termination portion 109. As described above, the wall emitter technology has traditionally had the drawback that emitter-collector short circuits tend to occur during emitter formation due to the influence of bird's beak, and various efforts have been made to overcome this drawback.

Among them, for example, there is a method of diffusing gallium through an oxide film after forming an active base and converting the entire surface area of the emitter formation region to P-type before diffusing the emitter. According to this method, the P layer spreads around the base layer, resulting in an increase in the capacitance of the base, which impedes high-speed operation of the semiconductor device. Furthermore, in the conventional technology, emitters are formed using punched patterns, so they are wider than the actual mask dimensions.
This has been an obstacle to miniaturization for higher integration and higher cutoff frequencies.

To summarize the conventional wall emitter technology, when forming a transistor, the bird's beak area needs to be etched at least twice with active base photolithography and emitter photolithography. A short circuit occurs. Current countermeasures include diffusing gallium, for example, but this poses a problem in terms of high-speed operation of the device.

In the present invention, the collector is removed by excessively etching the bird's beak portion, unlike the conventional technique.
Focusing on the point that an emitter short circuit occurs, we eliminated the etching process of the oxide film until the end of emitter diffusion after forming a deep collector, and formed an isolation region by oxidation treatment in an oxidizing atmosphere, and then formed this isolation region. The present invention provides a method for reducing the number of times of etching and/or mask alignment by using the mask material in the next process, that is, when forming a deep collector, and also as a mask when molding an inert base. Other features of the method of the present invention will be explained below with reference to embodiment figures. FIGS. 3A to 3E are cross-sectional views illustrating steps of an embodiment of the method of the present invention.

First, as shown in FIG. 3A, a P-type semiconductor substrate 30 is
1, an N ⁺ type buried layer 302 is formed, and then a P ⁺ type pre-isolation region 303 is formed. This pre-isolation region 303 is for forming an isolation region together with a portion of the insulating oxide that will be formed later by performing an oxidation treatment. Next, after removing the oxide over the entire surface, an N-type epitaxial layer 304 is deposited on the semiconductor substrate 301. Next, on the surface of the epitaxial layer 304,
After depositing polycrystalline silicon 305, silicon nitride 306 is deposited on this polycrystalline silicon 305. Thereafter, isolation oxidation patterns are formed by a known etching method, and grooves 307 are further formed by mesa etching.

When the semiconductor substrate 301 having such a structure is subjected to heat treatment in an oxidizing atmosphere, an isolation region 308 is formed (FIG. 3B). Next, of the nitride film 306 used as a mask for isolation oxidation, the nitride film 306a on the area where the deep collector is to be formed is removed, and N-type impurities are introduced through the exposed polycrystalline silicon 305, which also serves as a drive-in. By oxidizing the exposed polycrystalline silicon 305 into an oxide film 309, the deep collector 3
10 (Figure 3C). Next, among the nitride film 306 that remains even in the state shown in FIG. 3 _C1 and serves as a mask during isolation oxidation and deep collector formation,
The nitride film 306b remaining in areas other than the area where the emitter is planned to be formed is removed, P-type impurity ions are implanted into the exposed polycrystalline silicon 305, and oxidation treatment is also performed to serve as a drive-in. , an oxide film 3 of polycrystalline silicon containing P-type impurities.
09, and a P ⁺ type inactive base region 311 is formed in the N type epitaxial layer 304 (FIG. 3D). For ease of understanding, the remaining nitride film 306 on the area where the deep collector is to be formed is 306a, and that on the area where the inert base is to be formed and the emitter is to be formed is 306a.
Please note that it is expressed as 06b (3rd
Figures B to 3D).

Next, by immersing the nitride film in a solution that selectively dissolves the nitride film, such as phosphoric acid, the remaining nitride film 3 on the emitter formation area can be removed without mask alignment.
06b is removed to expose the polycrystalline silicon 305.

At this time, the oxide film 309 on other regions such as the inactive base and deep collector remains. First, in order to form the active base region 312, an ion implantation method is used to implant P-type impurities into the polycrystalline silicon 305, and a drive-in which also serves as an annealing treatment is performed to form the active base region 312. Furthermore, in order to form the emitter region 313,
N-type impurities are implanted into the exposed polycrystalline silicon layer 305 using an ion implantation method. Next, by performing appropriate heat treatment, an emitter region 31 is formed in the single crystal.
3 is formed, and then a highly doped polycrystalline silicon layer 314 (emitter electrode) is formed (FIG. 3E).

According to this embodiment, the formation of the active base region 312 and the formation of the emitter region 313 are performed independently, but both regions 312 and 313 are formed as follows.
can also be formed at the same time.

That is, boron is implanted as an impurity to form the active base region 312 into the exposed polycrystalline silicon 305 by ion implantation, and subsequently arsenic is implanted as an impurity to form the emitter region 313 by the same ion implantation method. . By subsequently performing heat treatment, the active base region 312, which is deeper than the emitter region 313, may be simultaneously formed by utilizing the difference in diffusion rate between boron and arsenic.

According to the method of the present invention described in detail above, there is no need for the step of etching the bird's beak portion of the isolation oxide film, so the active base opening end and the emitter opening end on the isolation oxide film side are the same. Be in position.

In this regard, the ends (circled) of the emitter and base region shown in FIG. 3E are shown enlarged in FIG. FIG. 4A shows the state after formation of the inert base. FIG. 4B shows a state in which an active base is formed, and FIG. 4C shows a state in which an emitter is formed.

Furthermore, when impurities are diffused a certain distance in the depth direction, the same amount (70 to 80%) is diffused laterally from the edge of the opening.
known to spread. Therefore, the positional relationship between the base and emitter after diffusion is the same as the width of the base, and the active base region expands in the lateral direction, so that no emitter-collector short circuit occurs.

Furthermore, the present invention does not require an oxide film etching process using hydrofluoric acid until the emitter diffusion is completed after the deep collector is formed, so the bird's beak film thickness does not change. Therefore, the positions of the ends of the base and emitter openings on the isolation oxide film side remain unchanged. In the final transistor structure, the base depth is deeper than the emitter depth by an amount controlled by the current gain factor, and the same degree of lateral expansion occurs, so that collector-emitter shorting does not occur.

In addition, the method of the present invention selectively leaves the mask used for forming the isolation region at a desired stage and utilizes it as a mask material for forming the deep collector region and the inert base region, thereby forming the isolation region. The nitride film removal step and the photolithography step (twice) for forming the active base region 13 and the inactive base region 12 can be omitted once.

Furthermore, since the active base region and the emitter region can be formed simultaneously or differently, it becomes easier to control the breakdown voltage characteristics, current gain characteristics, or cutoff frequency characteristics determined by the depth of the active base region. . In other words, if both regions are formed at the same time, there is no need to consider re-diffusion of the active base region during the formation of the emitter region, so the parameters governing the current gain and cut-off frequency characteristics are the impurity dose and one drive-in. You can decide.

On the other hand, this process in which both regions can be formed independently is particularly advantageous for forming transistors that require high breakdown voltage.

[Brief explanation of the drawing]

1A-E and 2A-C are process diagrams of a conventional integrated circuit manufacturing method, FIGS. 3A-E are process diagrams of an integrated circuit manufacturing method according to the present invention, and FIGS. 4A-4
C is a diagram for explaining the usefulness of the device obtained based on the method of the present invention. 301...Semiconductor substrate, 302...N ⁺ type buried layer, 303...P ⁺ type pre-isolation region, 304...N type epitaxial layer, 305...
...Polycrystalline silicon film, 306, 306a, 306
b...Nitride film, 307a...Groove provided in isolation region, 308, 309...Oxide film, 310...Deep collector region, 311...Inactive base region, 312...Active base region, 313...Emitter Region 314: Highly doped polycrystalline silicon layer.

Claims (1)

[Claims] 1. After selectively forming a polycrystalline silicon film and a nitride film on the main surface of the semiconductor substrate other than the area where insulation is to be separated, the substrate is exposed to an oxidizing atmosphere and covered with these composite films. forming an oxidized isolation region in the main surface of the substrate that is not covered by the oxidized isolation region, and peeling off the nitride film remaining on the region where the deep collector is to be formed separated by the oxidized isolation region;
A deep collector region is formed in the main surface of the substrate by introducing an N-type impurity into the exposed polycrystalline silicon film, and exposing the polycrystalline silicon film doped with the N-type impurity to an oxidizing atmosphere. A step of converting the polycrystalline silicon film doped with an N-type impurity into an oxide, and peeling off the remaining nitride film, leaving the nitride film remaining on the emitter formation region separated by the oxidation isolation region. , introducing a P-type impurity into the exposed polycrystalline silicon film, and exposing the polycrystalline silicon film doped with the P-type impurity to an oxidizing atmosphere to form an inactive base region within the main surface of the substrate; At the same time, there is a step of converting the polycrystalline silicon film doped with the P-type impurity into an oxide, and after peeling off the nitride film remaining on the emitter formation area, the semiconductor is passed through the exposed polycrystalline silicon film. 1. A method of manufacturing a semiconductor device, comprising forming an active base region containing P-type impurities and an emitter region containing N-type impurities in the main surface of a substrate.