KR0172749B1 - Method of forming gate electrode in semiconductor device - Google Patents
Method of forming gate electrode in semiconductor device Download PDFInfo
- Publication number
- KR0172749B1 KR0172749B1 KR1019950048754A KR19950048754A KR0172749B1 KR 0172749 B1 KR0172749 B1 KR 0172749B1 KR 1019950048754 A KR1019950048754 A KR 1019950048754A KR 19950048754 A KR19950048754 A KR 19950048754A KR 0172749 B1 KR0172749 B1 KR 0172749B1
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- South Korea
- Prior art keywords
- gate electrode
- forming
- entire structure
- oxide film
- layer
- Prior art date
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- 238000000034 method Methods 0.000 title claims abstract description 22
- 239000004065 semiconductor Substances 0.000 title claims abstract description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 7
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 6
- 150000004767 nitrides Chemical class 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 125000006850 spacer group Chemical group 0.000 claims description 6
- 229910052785 arsenic Inorganic materials 0.000 claims description 5
- 229910052698 phosphorus Inorganic materials 0.000 claims description 5
- 239000011574 phosphorus Substances 0.000 claims description 5
- -1 phosphorus ions Chemical class 0.000 claims description 5
- 238000005468 ion implantation Methods 0.000 claims description 4
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 claims 1
- 150000002500 ions Chemical class 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000011324 bead Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
본 발명은 게이트 전극의 길이가 필드 산화막에 형성되는 버즈빅의 길이 만큼 짧게 하는 초미세 게이트 전극을 형성하는 반도체 소자의 게이트 전극 형성 방법이 개시된다.The present invention discloses a method for forming a gate electrode of a semiconductor device in which an ultra-fine gate electrode is formed such that the length of the gate electrode is as short as the length of the buzzvik formed in the field oxide film.
Description
제1도는 종래의 반도체 소자 제조 방법을 설명하기 위한 단면도.1 is a cross-sectional view for explaining a conventional semiconductor device manufacturing method.
제2a도 내지 제2i도는 본 발명에 따른 반도체 소자 제조 방법을 설명하기 위한 단면도.2A to 2I are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1,11 : 실리콘 기판 2,12 : 게이트 산화막1,11 silicon substrate 2,12 gate oxide film
3,13 : 폴리실리콘 4,14 : N-이온 주입 영역3,13: polysilicon 4,14: N - ion implantation region
5,15 : 산화막 스페이서 6,16 : N+이온 주입 영역5,15: oxide spacer 6,16: N + ion implantation region
17 : 게이트 전극 18 : 패드 산화막17 gate electrode 18 pad oxide film
19 : 질화막 20 : 열 산화막19 nitride film 20 thermal oxide film
본 발명은 반도체 소자의 게이트 전극 형성 방법에 관한 것으로서, 특히 게이트 전극 형성용 마스크의 임계 치수보다 더 작은 초미세 게이트 전극을 형성할 수 있도록 한 반도체 소자의 게이트 전극 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a gate electrode of a semiconductor device, and more particularly, to a method for forming a gate electrode of a semiconductor device capable of forming an ultrafine gate electrode smaller than a critical dimension of a mask for forming a gate electrode.
일반적으로, 반도체 소자의 게이트 전극을 형성하는 방법을 제1도를 통해 설명하면 다음과 같다. 쪽, 실리콘 기판(1)상에 게이트 산화막(2) 및 폴리실리콘층이 패터닝되어 적층된 구조로 이루어진 게이트 전극이 형성된다. 상기 전체 구조 상부에 N-이온이 주입된 N-이온 주입 영역(4)이 형성되고 상기 게이트 전극 측벽에 산화막 스페이서(5)가 형성된 후, N+이온이 주입 되어 N+이온 주입 영역(6)이 형성되는 종래의 게이트 전극 형성 방법은 게이트 전극 형성용 마스크의 임계 치수이하로는 형성할 수 없는 단점이 있다. 따라서 본 발명은 열 산화막에 의한 필드 산화막에 형성되는 버즈빅을 이용하여 게이트 전극을 형성하는 방법을 제공하는데 그 목적이 있다.In general, a method of forming a gate electrode of a semiconductor device will be described with reference to FIG. 1. On the silicon substrate 1, a gate electrode having a structure in which the gate oxide film 2 and the polysilicon layer are patterned and stacked is formed. To the entire structure the upper N-N ions are implanted After the ion implanted region (4) is formed is formed the oxide film spacer 5 on the gate electrode side wall, N + is ion implanted N + ion-implanted region 6 The conventional method of forming the gate electrode, which is formed, has a disadvantage that it cannot be formed below the critical dimension of the mask for forming the gate electrode. Accordingly, an object of the present invention is to provide a method of forming a gate electrode using buzzviks formed in a field oxide film by a thermal oxide film.
상기한 목적을 달성하기 위한 본 발명은 실리콘 기판상에 패드 산화막을 형성하고, 그 상부의 선택된 영역에 질화막 패턴을 형성하여 가상의 게이트 전극을 형성하는 단계와, 상기 가상의 게이트 전극을 이온 주입 저지층으로 하여 상기 전체 구조 상부에 인 이온을 주입하여 제1차 N+접합영역을 형성하는 단계와, 상기 전체 구조 상부에 산화막을 증착하고, 마스크를 이용한 식각 공정으로 가상의 게이트 전극 측벽에 산화막 스페이서를 형성하는 단계와, 상기 전체 구조 상부에 비소(As)원자를 주입하여 제2차 N+접합영역을 형성하는 단계와, 상기 전체 구조 상부에 HF가스를 사용하여 상기 가상의 게이트 전극 측벽의 산화막 스페이서 및 패드 산화막을 습식식각공정으로 식각하는 단계와, 상기 전체 구조 상부에 열 산화공정으로 열 산화막을 증착하고, 상기 N-접합영역 및 N+접합영역을 확산하는 단계와, 상기 가상의 게이트 전극을 인산 용액으로 제거한 후, HF용액으로 패드 산화막을 제거하는 단계와, 상기 전체 구조 상부에 게이트 산화막 및 폴리실리콘층을 형성한 후, 그 상부에 게이트 산화막 및 폴리실리콘층 패턴이 형성된 구조로 이루어진 게이트 전극을 형성하는 것을 특징으로 한다.According to an aspect of the present invention, a pad oxide film is formed on a silicon substrate, and a nitride film pattern is formed on a selected region of the silicon substrate to form a virtual gate electrode, and the virtual gate electrode is ion implanted. Forming a first N + junction region by implanting phosphorus ions into the upper portion of the entire structure as a layer, depositing an oxide layer on the entire structure, and etching an oxide layer on a sidewall of the virtual gate electrode by using an etching process. Forming a second N + junction region by injecting arsenic (As) atoms over the entire structure, and using an HF gas over the entire structure, and forming an oxide film on the sidewall of the virtual gate electrode. Etching the spacer and pad oxide layers by a wet etching process, depositing a thermal oxide layer on the entire structure by a thermal oxidation process, Diffusing the N − junction region and the N + junction region, removing the virtual gate electrode with a phosphoric acid solution, and then removing a pad oxide layer with an HF solution, a gate oxide layer and a polysilicon layer on the entire structure. After the formation of the gate electrode, a gate electrode having a structure in which a gate oxide film and a polysilicon layer pattern are formed thereon is formed.
이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제2a도 내지 제2i도는 본 발명에 따른 반도체 소자 제조 방법을 설명하기 위한 단면도이다.2A to 2I are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.
제2a도와 관련하여, 실리콘 기판상에 패드 산화막 및 질화막이 각각 200 내지 300Å 및 1,000 내지 1,200Å의 두께로 증착된다.In connection with FIG. 2A, a pad oxide film and a nitride film are deposited on the silicon substrate to a thickness of 200 to 300 mW and 1,000 to 1,200 mW, respectively.
제2b도와 관련하여, 상기 전체 구조 상부에 포토리소그래피 공정으로 상기 질화막이 식각되어 가장의 게이트 전극이 형성된다.In relation to FIG. 2B, the nitride film is etched by a photolithography process on the entire structure to form a gate electrode of the most.
제2c도와 관련하여, 상기 가상의 게이트 전극이 이온 주입 저지층으로 되어 1×1012내지 1×1016원자/㎤, 30 내지 60Kev의 조건으로 인 이온이 주입된다. 상기 인 이온이 주입된 제1차 N-접합영역이 형성된다.In connection with FIG. 2C, the imaginary gate electrode becomes an ion implantation blocking layer and phosphorus ions are implanted under the conditions of 1 × 10 12 to 1 × 10 16 atoms / cm 3 and 30 to 60 Kev. The first N − junction region into which the phosphorus ion is implanted is formed.
제2d도와 관련하여, 상기 전체 구조 상부에 산화막이 증착되고, 마스크를 이용한 식각공정으로 가상의 게이트 전극 측벽에 산화막 스페이서가 형성된다.In relation to FIG. 2D, an oxide film is deposited on the entire structure, and an oxide spacer is formed on the sidewall of the virtual gate electrode by an etching process using a mask.
제2e도와 관련하여, 상기 전체 구조 상부에 1×1014내지 1×1017원자/㎤, 30 내지 60Kev의 조건으로 비소(AS)원자가 주입되어 제2차 N+접합영역이 형성된다.In relation to the second e diagram, arsenic (AS) atoms are implanted on the entire structure under conditions of 1 × 10 14 to 1 × 10 17 atoms / cm 3 and 30 to 60 Kev to form a second N + junction region.
제2f도와 관련하여, 상기 전체 구조 상부에 HF가스를 사용하여 상기 게이트 전극 측벽의 산화막 스페이서 및 패드 산화막이 습식식각공정에 의해 식각된다.In connection with FIG. 2F, the oxide spacer and the pad oxide layer of the sidewall of the gate electrode are etched by a wet etching process using HF gas over the entire structure.
제2g도와 관련하여, 상기 전체 구조 상부에 열 산화공정으로 열 산화막이 200 내지 400Å두께로 증착된다. 이때, N-접합영역 및 N+접합영역이 확산하게 된다.In relation to the second g degree, a thermal oxide film is deposited to a thickness of 200 to 400 kPa by a thermal oxidation process on the entire structure. At this time, the N − junction region and the N + junction region are diffused.
제2h도와 관련하여, 상기 게이트 전극이 인산용액으로 제거된후, HF용액으로 패드 산화막이 제거된다.In relation to the second figure, after the gate electrode is removed with a phosphoric acid solution, a pad oxide film is removed with an HF solution.
제2i도와 관련하여, 상기 전체 구조 상부에 게이트 산화막 및 폴리실리콘층이 패터닝되어 적층된 구조로 이루어진 게이트 전극이 형성된다.Referring to FIG. 2I, a gate electrode having a structure in which a gate oxide film and a polysilicon layer is patterned and stacked is formed on the entire structure.
상술한 바와 같이 본 발명에 의하여 버즈빅 발생 길이 만큼 게이트 전극의 길이가 짧아지는 초미세 게이트 전극을 형성할 수 있는 탁월한 효과가 있다.As described above, according to the present invention, there is an excellent effect of forming an ultrafine gate electrode whose length is shortened as much as the occurrence of the buzz bead.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950048754A KR0172749B1 (en) | 1995-12-12 | 1995-12-12 | Method of forming gate electrode in semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950048754A KR0172749B1 (en) | 1995-12-12 | 1995-12-12 | Method of forming gate electrode in semiconductor device |
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| Publication Number | Publication Date |
|---|---|
| KR970054325A KR970054325A (en) | 1997-07-31 |
| KR0172749B1 true KR0172749B1 (en) | 1999-02-01 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950048754A KR0172749B1 (en) | 1995-12-12 | 1995-12-12 | Method of forming gate electrode in semiconductor device |
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| Country | Link |
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| KR (1) | KR0172749B1 (en) |
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1995
- 1995-12-12 KR KR1019950048754A patent/KR0172749B1/en not_active IP Right Cessation
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| Publication number | Publication date |
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| KR970054325A (en) | 1997-07-31 |
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