KR100271794B1 - A mothod of forming a buried contact in simiconductor device - Google Patents
A mothod of forming a buried contact in simiconductor device Download PDFInfo
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- KR100271794B1 KR100271794B1 KR1019980010264A KR19980010264A KR100271794B1 KR 100271794 B1 KR100271794 B1 KR 100271794B1 KR 1019980010264 A KR1019980010264 A KR 1019980010264A KR 19980010264 A KR19980010264 A KR 19980010264A KR 100271794 B1 KR100271794 B1 KR 100271794B1
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- polysilicon layer
- insulating film
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- 239000000758 substrate Substances 0.000 claims abstract description 40
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 36
- 229920005591 polysilicon Polymers 0.000 claims abstract description 36
- 239000004065 semiconductor Substances 0.000 claims abstract description 24
- 238000000034 method Methods 0.000 claims abstract description 22
- 239000012535 impurity Substances 0.000 claims abstract description 19
- 238000009792 diffusion process Methods 0.000 claims abstract description 13
- -1 phosphorous ions Chemical class 0.000 claims abstract description 9
- 229910052698 phosphorus Inorganic materials 0.000 claims description 7
- 239000011574 phosphorus Substances 0.000 claims description 7
- RLOWWWKZYUNIDI-UHFFFAOYSA-N phosphinic chloride Chemical compound ClP=O RLOWWWKZYUNIDI-UHFFFAOYSA-N 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 1
- 239000002019 doping agent Substances 0.000 claims 1
- 229910052814 silicon oxide Inorganic materials 0.000 claims 1
- 238000009413 insulation Methods 0.000 abstract 5
- 238000004519 manufacturing process Methods 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 238000005468 ion implantation Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
본 발명은 반도체장치의 콘택 형성방법에 관한 것으로서 특히, 반도체장치의 활성영역의 콘택부에서 높은 저항을 감소시키기 위하여 이중 폴리실리콘층과 이온주입 및 포클(POCl3)처리를 실시하여 형성한 반도체장치의 매몰형 콘택(buried contact) 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact of a semiconductor device, and more particularly, to a semiconductor device formed by performing a double polysilicon layer, ion implantation, and fockle (POCl 3 ) treatment in order to reduce high resistance in a contact portion of an active region of a semiconductor device. It relates to a buried contact forming method of the.
반도체장치의 매몰형 콘택은 종래의 버티드 콘택(butted contact)과 달리 폴리실리콘과 실리콘기판의 실리콘이 금속을 매개체로 이용하지 아니하고 서로 직접 접촉연결되어 셀의 크기(size)의 축소에 유리하고 고집적회로에서 부수적인 상호 연결에 유리한 콘택 방법이다. 따라서 종래의 반도체장치의 매몰형 콘택구조에서는 폴리실리콘과 실리콘기판 사이에서 직접적인 콘택으로 칩의 크기를 감소시키도록 하였다.Unlike conventional butted contacts, the buried contact of a semiconductor device is advantageous in reducing the size of a cell because polysilicon and silicon of a silicon substrate are directly contacted with each other without using a metal as a medium. It is an advantageous contact method for ancillary interconnections in the circuit. Therefore, in the buried contact structure of the conventional semiconductor device, the chip size is reduced by direct contact between the polysilicon and the silicon substrate.
도 1 은 종래 기술에 따라 형성된 반도체장치의 콘택을 도시하는 단면도이다.1 is a cross-sectional view showing a contact of a semiconductor device formed according to the prior art.
도 1 을 참조하면, 실리콘기판(1)에 LOCOS(local oxidation of silicon) 방법으로 소자 격리를 위한 필드산화막(2)을 형성한 다음 기판(1)의 전면에 게이트산화막(3)을 증착하여 형성한 다음 포토리소그래피(photolithography) 방법으로 매몰형 콘택 형성 부위의 게이트산화막(3)을 제거한다.Referring to FIG. 1, a field oxide film 2 for device isolation is formed on a silicon substrate 1 by a local oxidation of silicon (LOCOS) method, and then a gate oxide film 3 is formed on the entire surface of the substrate 1. Then, the gate oxide film 3 at the buried contact formation site is removed by photolithography.
그리고 매몰형콘택부위를 포함하는 기판(1)의 전면에 폴리실리콘층(4)을 증착하여 형성한 다음, 다시 사진식각공정을 실시하여 폴리실리콘층(4)과 잔류한 게이트산화막(3)을 선택적으로 제거하여 매몰형 콘택을 형성한다.The polysilicon layer 4 is deposited on the entire surface of the substrate 1 including the buried contact portion, and then subjected to a photolithography process to form the polysilicon layer 4 and the remaining gate oxide film 3. It is selectively removed to form an investment contact.
그러나, 상술한 종래 기술에 따른 반도체장치의 콘택 형성방법은 폴리실리콘과 기판의 실리콘이 직접 접촉하게 되어 이러한 콘택부위에서의 높은 저항은 결국 프로세스의 범용화에 곤란한 문제점이 있었다.However, the contact forming method of the semiconductor device according to the prior art described above has a problem that polysilicon and silicon of the substrate are in direct contact with each other, so that the high resistance at the contact portion is difficult to generalize the process.
따라서, 본 발명의 목적은 반도체장치의 활성영역의 콘택부에서 높은 저항을 감소시키기 위하여 이중 폴리실리콘층과 이온주입 및 포클(POCl3)처리를 실시하여 형성한 반도체장치의 매몰형 콘택(buried contact) 형성방법을 제공하는데 있다.Accordingly, an object of the present invention is to provide a buried contact of a semiconductor device formed by performing a double polysilicon layer and ion implantation and fockle (POCl 3 ) treatment in order to reduce high resistance in the contact portion of the active region of the semiconductor device. ) To provide a formation method.
상기 목적들을 달성하기 위한 본 발명에 따른 반도체장치의 콘택 형성방법은 제 1 도전형 반도체기판 위에 제 1 절연막을 형성하는 단계와, 제 1 절연막 위에 제 1 폴리실리콘층을 형성하는 단계와, 제 1 폴리실리콘층의 소정 부위를 제거하여 제 1 절연막의 일부를 노출시키는 단계와, 노출된 제 1 절연막의 일부 하부의 반도체기판에 제 2 도전형 불순물확산층을 형성하는 단계와, 노출된 제 1 절연막의 일부를 제거하는 단계와, 노출된 기판의 표면을 포함하는 기판의 전면에 도핑되지 아니한 제 2 폴리실리콘층을 형성하는 단계와, 제 2 폴리실리콘층과 기판의 제 2 도전형 불순물확산층 상부를 제 2 도전형 불순물로 도핑시키는 단계와, 도핑된 기판의 불순물확산층 상부의 일부를 노출시키는 단계로 이루어진다.According to an aspect of the present invention, there is provided a method of forming a contact for a semiconductor device, the method including forming a first insulating film on a first conductive semiconductor substrate, forming a first polysilicon layer on the first insulating film, and Removing a predetermined portion of the polysilicon layer to expose a portion of the first insulating film, forming a second conductive impurity diffusion layer on a semiconductor substrate under the exposed portion of the first insulating film, and Removing a portion, forming an undoped second polysilicon layer on the front surface of the substrate including the exposed substrate surface, and removing the second polysilicon layer and the second conductive impurity diffusion layer on the substrate. Doping with a second conductivity type impurity and exposing a portion of an upper portion of the impurity diffusion layer of the doped substrate.
도 1 은 종래 기술에 따라 형성된 반도체장치의 콘택을 도시하는 단면도.1 is a cross-sectional view showing a contact of a semiconductor device formed according to the prior art.
도 2a 내지 도 2e 는 본 발명에 따른 반도체장치의 콘택 형성방법을 도시하는 공정단면도.2A to 2E are process cross-sectional views showing a contact forming method of a semiconductor device according to the present invention.
본 발명은 매몰형 콘택 부위에 포클처리에서의 인(phosphorus) 이온들이 폴리실리콘과 게이트산화막의 계면으로 부터 기판의 실리콘안으로 침투하여 매몰형 콘택부위의 저항을 감소하게 한다.According to the present invention, phosphorus ions in the fockle treatment in the buried contact portion penetrate into the silicon of the substrate from the interface between the polysilicon and the gate oxide film to reduce the resistance of the buried contact portion.
이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2e 는 본 발명에 따른 반도체장치의 콘택 형성방법을 도시하는 공정단면도이다.2A to 2E are process cross-sectional views showing a contact forming method of a semiconductor device according to the present invention.
도 2a 에 있어서, 소자격리를 위한 필드산화막(22)이 형성된 제 1 도전형 반도체기판인 인 p 형 실리콘기판(21) 위에 게이트산화막(23)을 증착하여 형성한 다음, 다시 상기 게이트 산화막(23) 위에 제 1 폴리실리콘층(24)을 증착하여 형성한다.In FIG. 2A, a gate oxide film 23 is formed on a p-type silicon substrate 21, which is a first conductive semiconductor substrate on which a field oxide film 22 for device isolation is formed, and then the gate oxide film 23 is formed again. ) Is formed by depositing a first polysilicon layer (24).
도 2b 에 있어서, 제 1 폴리실리콘층(24)위에 포토레지스트를 도포한 다음 매몰형 콘택이 형성될 부위를 노출시키기 위한 제 1 폴리실리콘층(24) 표면을 노출시키는 제 1 포토레지스트패턴(도시 안함)을 사진공정으로 정의한다.In FIG. 2B, a first photoresist pattern is formed by applying a photoresist on the first polysilicon layer 24 and then exposing a surface of the first polysilicon layer 24 for exposing a portion where a buried contact is to be formed. None) as a photo process.
그다음 제 1 포토레지스트패턴으로 보호되지 아니하는 부위의 제 1 폴리실리콘층(24)을 제거하여 게이트산화막(23)의 일부 표면을 노출시킨다.Then, the first polysilicon layer 24 in the portion not protected by the first photoresist pattern is removed to expose a part of the surface of the gate oxide film 23.
도 2c에 있어서, 기판(21)의 전면에 제 2 도전형인 인(phosphorus) 이온을 사용하는 매몰형콘택 이온주입을 실시하여 노출된 게이트산화막(23) 하단의 실리콘기판(21) 표면하에 불순물매몰층(200)을 형성한다. 이때 불순물매몰층(200)은 필드산화막(22) 하부의 기판(21)에는 형성되지 아니한다.In FIG. 2C, an impurity is buried under the surface of the silicon substrate 21 below the exposed gate oxide film 23 by implanting a buried contact ion implantation using a second conductivity type phosphorus ion on the entire surface of the substrate 21. Form layer 200. In this case, the impurity buried layer 200 is not formed on the substrate 21 under the field oxide film 22.
도 2d에 있어서, 불순물매몰층(200)의 인이온을 충분히 확산시키기 위하여 기판(21)에 어닐링을 실시하여 확산층(201)을 기판 내부에 형성한다.In FIG. 2D, in order to sufficiently diffuse the phosphorus ions of the impurity buried layer 200, the substrate 21 is annealed to form a diffusion layer 201 inside the substrate.
그 다음, 노출된 게이트산화막(23)을 습식식각으로 제거하여 필드산화막(22)과 기판(21)의 표면을 다시 노출시킨 후 제 1 포토레지스트패턴을 제거한다.Next, the exposed gate oxide layer 23 is removed by wet etching to expose the surface of the field oxide layer 22 and the substrate 21 again, and then the first photoresist pattern is removed.
그리고 도핑되지 아니한 제 2 폴리실리콘을 기판(21)의 전면에 증착하여 제 2 폴리실리콘층(25)을 형성한다. 따라서 노출된 기판(21)의 표면과 도핑되지 아니한 제 2 폴리실리콘층(25)이 접촉하게 된다.The second polysilicon layer undoped is deposited on the entire surface of the substrate 21 to form the second polysilicon layer 25. Therefore, the surface of the exposed substrate 21 and the undoped second polysilicon layer 25 are in contact with each other.
도 2e 에 있어서, 도핑되지 아니한 제 2 폴리실리콘층(25)에 포클처리를 실시하여 제 2 폴리실리콘층을 인(phosphorus)이온으로 도핑시킨다. 이때 포클처리에서 인입된 인 이온들은 실리콘기판(21)으로 확산되어 추가도핑층(202)을 형성하는데, 이들의 확산경로는 제 1 폴리실리콘층(24)과 필드산화막(22)이 형성된 부위에 의하여 차단되고 그 이외의 기판(21)으로만 확산된다.In FIG. 2E, the second polysilicon layer is doped with phosphorus ions by performing a fockle treatment on the undoped second polysilicon layer 25. At this time, phosphorus ions introduced in the fockle treatment are diffused onto the silicon substrate 21 to form an additional doping layer 202, and the diffusion paths are formed at a portion where the first polysilicon layer 24 and the field oxide film 22 are formed. Is blocked and diffused only to the other substrate 21.
그 다음, 제 2 폴리실리콘층(25)의 표면에 포토레지스트를 도포한 후 매몰형 콘택부위를 형성하기 위한 사진공정을 실시하여 제 2 포토레지스트패턴(26)을 정의 한 다음 이로 부터 보호되지 아니하는 부위의 제 2 폴리실리콘층(25), 잔류한 제 1 폴리실리콘층(24) 그리고 게이트산화막(23)을 제거하여 매몰형 콘택을 형성한다.Next, after the photoresist is applied to the surface of the second polysilicon layer 25, a photolithography process is performed to form a buried contact portion, thereby defining the second photoresist pattern 26 and then not protected therefrom. A buried contact is formed by removing the second polysilicon layer 25, the remaining first polysilicon layer 24, and the gate oxide film 23 at the portion to be removed.
이후 제 2 포토레지스트패턴(26)을 제거한다.Thereafter, the second photoresist pattern 26 is removed.
따라서, 본 발명은 반도체장치의 매몰형 콘택 부위에 포클처리에서의 인(phosphorus) 이온들이 폴리실리콘으로 부터 기판으로 침투하여 매몰형 콘택부위의 높은 저항을 감소시키는 효과가 있다.Therefore, the present invention has the effect of reducing the high resistance of the buried contact portion by the phosphorus (phosphorus) ions in the fockle treatment in the buckle contact portion of the semiconductor device penetrates into the substrate from the polysilicon.
Claims (6)
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| KR1019980010264A KR100271794B1 (en) | 1998-03-25 | 1998-03-25 | A mothod of forming a buried contact in simiconductor device |
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| KR1019980010264A KR100271794B1 (en) | 1998-03-25 | 1998-03-25 | A mothod of forming a buried contact in simiconductor device |
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| JPH0917746A (en) * | 1995-06-27 | 1997-01-17 | Matsushita Electric Works Ltd | Semiconductor device and its manufacture |
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|---|---|---|---|---|
| JPH0917746A (en) * | 1995-06-27 | 1997-01-17 | Matsushita Electric Works Ltd | Semiconductor device and its manufacture |
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