KR930008890B1 - Method of forming separated layer of semiconductor - Google Patents
Method of forming separated layer of semiconductor Download PDFInfo
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- KR930008890B1 KR930008890B1 KR1019910015844A KR910015844A KR930008890B1 KR 930008890 B1 KR930008890 B1 KR 930008890B1 KR 1019910015844 A KR1019910015844 A KR 1019910015844A KR 910015844 A KR910015844 A KR 910015844A KR 930008890 B1 KR930008890 B1 KR 930008890B1
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- channel stopper
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- 238000000034 method Methods 0.000 title claims abstract description 22
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 35
- 239000012535 impurity Substances 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000000151 deposition Methods 0.000 claims abstract description 6
- 238000005530 etching Methods 0.000 claims abstract description 5
- 238000000059 patterning Methods 0.000 claims abstract description 5
- 238000002955 isolation Methods 0.000 claims description 19
- 238000003780 insertion Methods 0.000 claims description 17
- 230000037431 insertion Effects 0.000 claims description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 238000005468 ion implantation Methods 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 230000008021 deposition Effects 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 7
- 150000004767 nitrides Chemical class 0.000 description 7
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000002265 prevention Effects 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
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- Condensed Matter Physics & Semiconductors (AREA)
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Element Separation (AREA)
Abstract
Description
제 1 도는 본 발명의 일실시예를 나타낸 반도체소자 분리층 형성방법의 공정도.1 is a process diagram of a method for forming a semiconductor device isolation layer showing an embodiment of the present invention.
제 2 도는 본 발명의 다른 실시예를 나타낸 반도체소자 분리층 형성방법의 공정도.2 is a process diagram of a method for forming a semiconductor device isolation layer showing another embodiment of the present invention.
본 발명은 반도체장치의 제조방법에 관한 것으로, 특히 반도체 기판 위에 형성되는 고집적 반도체 소자들간의 전기적 분리 특성을 향상시킨 반도체소자 분리층 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a semiconductor device isolation layer having improved electrical separation characteristics between highly integrated semiconductor devices formed on a semiconductor substrate.
종래, 반도체 기판 내에 형성된 소자간의 분리를 위한 소자분리 영역 형성 기술인 LIF(Localized channel stop implantation through field oxide)기술은 실리콘 기판에 300Å 두께의 패드산화막을 성장시키고 폴리층을 형성시키고 실리콘 질화막을 형성시킨후 액티브 포토공정을 진행한 다음 얇은 박막의 질화막 및 HTO막을 형성시킨후 비등방성 식각법으로 스페이서(spacer)를 형성한다. 이어 산화법에 의해 필드산화막을 성장시킨후 포토레지스트로 액티브(active)영역을 가린후 충분히 높은 에너지로 필드산화막을 통해 채널스토퍼 이온을 주입하는 방법으로 이는 과도하게 채널스토퍼 이온을 주입할 경우 접합 누설전류(Junction Leakage Current)가 증가하는 문제와 접합 항복(Junction Breakdown)전압이 감소하는 문제 및 트랜지스터의 내로우 채널효과(narrow channel effect)가 커서 전류 구동력이 떨어지는 문제를 모두 해결할 수는 있으나, 포토미스얼라인(photo misalign)을 고려치 않아 일부 활성(activa)영역에 불순물이 주입되고 필드 산화막 내로 불순물이 확산되어 들어가게 된다.Conventionally, localized channel stop implantation through field oxide (LIF) technology, which is a device isolation region formation technology for isolation between devices formed in a semiconductor substrate, grows a 300 Å thick pad oxide film on a silicon substrate, forms a poly layer, and forms a silicon nitride film. After the active photo process, a thin nitride film and an HTO film are formed, and a spacer is formed by anisotropic etching. Subsequently, the field oxide film is grown by the oxidation method, and the active region is covered by the photoresist, and then channel stopper ions are injected through the field oxide film with a sufficiently high energy. (Junction Leakage Current) increases, the junction breakdown voltage decreases, and the narrow channel effect of the transistor is large, it can solve the problem of falling current driving force, but can be solved In consideration of the photo misalignment, impurities are injected into some of the activation regions and impurities are diffused into the field oxide layer.
따라서, 실리콘 기판과 필드산화막 계면의 불순물농도가 저하되어 충분한 펀치 드루우 방지효과를 얻을 수 없게 된다.Therefore, the impurity concentration at the interface between the silicon substrate and the field oxide film is lowered, so that a sufficient punch draw prevention effect cannot be obtained.
본 발명의 목적은 내로우 채널효과(narrow channel effact)를 감소시키면서 다소의 미스얼라인에 구애받지 않고 채널스토퍼 이온을 주입하여 펀치드로우 방지효과를 얻을 수 있음으로써 높은 정밀도의 소자 분리 특성이 있는 반도체소자 분리층 형성방법을 제공하는데 있다.SUMMARY OF THE INVENTION An object of the present invention is to reduce the narrow channel effect and to prevent punch draw by injecting channel stopper ions regardless of some misalignment, thereby achieving high precision device isolation characteristics. It is to provide a device isolation layer forming method.
이하, 첨부 도면을 참조로하여 본 발명을 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
본 발명은 실리콘 기판 표면에 소자분리 영역으로 되는 필드산화막(1)을 선택적으로 형성하는 공정과, 전면에 기저 포토레지스트(Bottom photoresist :2), 제 1 삽입층(3) 및 상부 포토레지트(4)를 차례로 증착하는 공정과, 상기 상부 포토레지스트(4)를 식각에 의해 상기 필드산화막(1) 상부에 개공부를 갖도록 패터닝하는 공정과, 이 패터닝에 의해 형성된 개공부를 통해 상부 포토레지스트(4)를 마스크로 하여 상기 제 1 삽입층(3)과 기저 포토레지스트(2)l의 일부를 식각하는 공정과, 여기에 이온주입을 하거나 상기 상부 포토레지스트(4)를 스트립하고 제 2 삽입층(5)을 증착시킨후 채널스토퍼 불순물을 이온주입하는 공정과 상기 제 2 삽입층(5), 제 1 삽입층(3), 기저 포토레지스트(2)를 스트립하는 공정에 의해 소자분리영역을 형성하는 공정들을 구비하여 이루어진 것을 특징으로 한다.The present invention provides a process of selectively forming a field oxide film 1 serving as an isolation region on a silicon substrate surface, a bottom photoresist (2), a first insertion layer (3), and an upper photoresist (on the front surface). 4) sequentially depositing, patterning the upper photoresist 4 to have openings on the field oxide film 1 by etching, and forming an upper photoresist through the openings formed by the patterning. 4) using the mask as a mask to etch a part of the first insertion layer 3 and the base photoresist 2, and ion implantation or stripping the upper photoresist 4 to the second insertion layer (5) forming a device isolation region by ion implantation of channel stopper impurities and stripping of the second insertion layer 5, the first insertion layer 3, and the base photoresist 2. Made with processes It is characterized by.
상기와 같이 반도체장치의 제조방법을 실시예를 들어 보다 상세히 설명하면 다음과 같다.If the semiconductor device manufacturing method as described above will be described in more detail with reference to the embodiment.
제 1 도는 본 발명의 제 1 실시예를 나타낸 것으로, 실리콘 기판상에 열산화법으로 얇은 산화막을 표면보호막을 형성시킨후 이 얇은 산화막상에 내산화성막으로서 질화막을 형성시킨다. 이어, 소자분리 영역의 형성 예정 위치에 사진식각법으로 상기 질화막, 산화막에 선택적으로 개공부를 형성함으로써 실리콘기판을 노출시킨후 고온에서 장시간에 걸쳐 열산화를 실시하여 내산화성막인 질화막이 존재하는 부분외에 개공부 영역만이 선택적으로 산화되어 소자분리영역인 필드산화막(1)이 형성된다. 이어, 질화막, 산화막을 식각하고 필드산화막(1)을 부분식각하여 호상의 필드산화막(1)이 형성한다. 그후 필드산화막(1)상에 평탄화를 위한 멀티레지스트층(Multi Layer Resist ; MLR)인 기저 포토레지스트(2)를 증착한다. 이어, 제 1 삽입층(3)과 상부 포토레지스트(4)를 차례로 증착시킨후 상기 필드산화막(1) 상부에 개공부를 갖도록 패터닝한다. 그후, 패터닝한 상부 포토레지스트(4)를 마스크로 제 1 삽입층(3)과 기저 포토레지스트(2)를 에치한다. 이때, 기저 포토레지스트(2)는 필드산화막(1)위에 적당한 두께가 남겨지도록 에치한다.1 shows a first embodiment of the present invention, in which a thin oxide film is formed on a silicon substrate by a thermal oxidation method to form a surface protective film, and then a nitride film is formed on the thin oxide film as an oxidation resistant film. Subsequently, the silicon substrate is exposed by selectively forming openings in the nitride film and the oxide film by a photolithography method at the position where the device isolation region is to be formed. In addition to the portion, only the opening region is selectively oxidized to form the field oxide film 1 as the device isolation region. Subsequently, the nitride film and the oxide film are etched and the field oxide film 1 is partially etched to form the arc-shaped field oxide film 1. Subsequently, a base photoresist 2, which is a multi-resist layer (MLR) for planarization, is deposited on the field oxide film 1. Subsequently, the first insertion layer 3 and the upper photoresist 4 are sequentially deposited and then patterned to have openings on the field oxide layer 1. Thereafter, the first insertion layer 3 and the base photoresist 2 are etched using the patterned upper photoresist 4 as a mask. At this time, the base photoresist 2 is etched so that an appropriate thickness is left on the field oxide film 1.
이어, 제 1 삽입층(3)과 같은 막질의 제 2삽입층(5)을 적당한 두께로 증착한 후에 채널스토퍼 불순물을 이온주입한다. 여기서, 제 2 삽입층(5) 증착전에 이온주입을 할 수도 있다. 그후, 계속해서 제 2 삽입층(5), 제 1 삽입층(3)을 습식에치하고 기저 포토레지스트(2)를 스트립하여 소자분리 영역을 형성한다.Subsequently, after the second insertion layer 5 having the same film quality as the first insertion layer 3 is deposited to an appropriate thickness, ion implantation of channel stopper impurities is performed. Here, ion implantation may be performed before deposition of the second insertion layer 5. Thereafter, the second insertion layer 5 and the first insertion layer 3 are then wet etched and the base photoresist 2 is stripped to form an isolation region.
또한 실시예로서 제 2 도에 나타낸 바와같이, 실리콘 기판상에 산화막, 질화막을 증착하고 포토레지스트를 증착시킨후 패터닝하여 소자영역과 소자분리영역을 구분 식각한후 열산화법에 의하여 소자 분리영역을 산화시켜 필드산화막(1)을 형성한다. 이어, 포토레지스트, 질화막, 산화막을 차례로 스트립한후 필드산화막(1)을 부분식각한다.As an example, as shown in FIG. 2, an oxide film and a nitride film are deposited on a silicon substrate, a photoresist is deposited, and then patterned to separate and etch the device and device isolation regions, thereby oxidizing the device isolation region by thermal oxidation. To form the field oxide film 1. Subsequently, the photoresist, the nitride film, and the oxide film are sequentially stripped, and then the field oxide film 1 is partially etched.
상기 필드산화막(1) 형성공정후 멀티레지스트층인 기저 포토레지스트(2)을 도포하고 패너닝하되 상기 필드산화막(1) 상부에 약간의 포토레지스트(2)의 찌꺼기(sucm)가 남겨지도록 통상적인 노출조건보다 노출시간을 줄여 언더노광(underexposure)한다.After the process of forming the field oxide film 1, the base photoresist 2, which is a multi-resist layer, is coated and panned, but a few sucm of the photoresist 2 is left on the field oxide film 1. Underexposure is shortened by exposure time rather than exposure conditions.
이어, 채널스토퍼 불순물의 이온주입을 할때 필드산화막(1) 바로 아래의 피크(peak)를 목표로하여 웨이퍼내에서 움직임 수직거리(projected range ; Rp)를 계산하여 이온주입을 한다.Subsequently, when implanting channel stopper impurities, ion implantation is performed by calculating a projected range Rp in the wafer, aiming at a peak just below the field oxide film 1.
계속해서 기저 포토레지스트(2)를 스트립하여 소자분리영역을 형성한다.Subsequently, the base photoresist 2 is stripped to form an isolation region.
상기와 같은 반도체소자 분리층 형성방법에 있어서, 채널스토퍼 불순물 주입시 필드산화막(1) 형성전에 먼저 1차 채널스토퍼 이온을 주입한후 필드산화막(1)을 형성하고 선택적으로 2차 채널스토퍼 불순물을 주입하는 상기 실시예의 공정들을 차례로 실시한다.In the method of forming a semiconductor device isolation layer as described above, in the case of implanting the channel stopper impurity, the primary channel stopper ion is first implanted before the field oxide film 1 is formed, and then the field oxide film 1 is formed, and the second channel stopper impurity is selectively The processes of the above-described embodiment for injection are carried out in sequence.
이 경우 1차 채널스토퍼 불순물의 농도는 필드산화막(1) 형성시 열에 의해 소자영역까지 확산되지 않도록 설정한다. 또한, 상기와 같이 필드산화막(1)을 형성한 후 질화막을 스트립하기전에 LOCOS 구조, A-LOCOS 즉 SEPOS 구조에서 상기한 여러 실시예를 적용하면 아래와 같은 본 발명의 효과를 얻을 수 있다.In this case, the concentration of the primary channel stopper impurity is set so as not to diffuse to the device region by heat when the field oxide film 1 is formed. In addition, if the above-described embodiments of the LOCOS structure, the A-LOCOS, or the SEPOS structure are applied after the field oxide film 1 is formed and before the nitride film is stripped, the following effects of the present invention can be obtained.
이상에서 설명한 본 발명에 의하면, 채널스토퍼 불순물에 의한 내로우 채널효과를 감소시킬 수 있고 채널스토퍼용 불순물의 확산을 방지할 수 있으며 펀치드루우 방지효과를 충분히 얻을 수 있어 보다 향상된 소자간의 분리특성을 나타낼 수 있다.According to the present invention described above, it is possible to reduce the narrow channel effect due to the channel stopper impurities, to prevent the diffusion of impurities for the channel stopper, and to sufficiently obtain the punch draw prevention effect, thereby improving separation characteristics between devices. Can be represented.
Claims (3)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910015844A KR930008890B1 (en) | 1991-09-11 | 1991-09-11 | Method of forming separated layer of semiconductor |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910015844A KR930008890B1 (en) | 1991-09-11 | 1991-09-11 | Method of forming separated layer of semiconductor |
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| KR930006908A KR930006908A (en) | 1993-04-22 |
| KR930008890B1 true KR930008890B1 (en) | 1993-09-16 |
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| KR1019910015844A KR930008890B1 (en) | 1991-09-11 | 1991-09-11 | Method of forming separated layer of semiconductor |
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