KR100231603B1 - Manufacturing method for transistor of semiconductor device - Google Patents
Manufacturing method for transistor of semiconductor device Download PDFInfo
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- KR100231603B1 KR100231603B1 KR1019960056894A KR19960056894A KR100231603B1 KR 100231603 B1 KR100231603 B1 KR 100231603B1 KR 1019960056894 A KR1019960056894 A KR 1019960056894A KR 19960056894 A KR19960056894 A KR 19960056894A KR 100231603 B1 KR100231603 B1 KR 100231603B1
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- insulating film
- transistor
- spacer
- gate electrode
- region
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 18
- 125000006850 spacer group Chemical group 0.000 claims abstract description 15
- 239000012535 impurity Substances 0.000 claims description 18
- 239000000758 substrate Substances 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 4
- 239000011261 inert gas Substances 0.000 claims 1
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 abstract description 8
- 229910052786 argon Inorganic materials 0.000 abstract description 4
- 239000012212 insulator Substances 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 238000002955 isolation Methods 0.000 description 3
- 239000002245 particle Substances 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
본 발명은 반도체소자의 트랜지스터 제조방법에 관한 것으로, 특히 엘.디.디. (LDD, Lightly Doped Drain, 이하에서 LDD라 함) 구조를 갖는 트랜지스터를 형성할 때 스페이서가 형성될 지역의 절연막에 아르곤을 주입하여 조직을 치밀하게 형성함으로써 후속식각공정시 게이트전극의 측벽 부분에만 상기 아르곤이 주입된 절연막을 남겨 스페이서를 형성하고 후속공정으로 LDD구조의 트랜지스터를 형성할 수 있는 기술이다.The present invention relates to a method of manufacturing a transistor of a semiconductor device, and more particularly, When a transistor having a structure of LDD (Lightly Doped Drain, hereinafter referred to as LDD) is formed, argon is injected into an insulating film in a region where a spacer is to be formed to densely form a structure, A technique in which a spacer is formed by leaving an insulator film into which argon is implanted and a transistor of an LDD structure can be formed in a subsequent process.
Description
본 발명은 반도체소자의 트랜지스터 제조방법에 관한 것으로, 특히 엘.디.디. (Lihgtly Doped Drain, 이하 LDD 라 함 ) 구조를 갖는 트랜지스터를 형성할 때 새로운 절연막 스페이서 형성 방법을 도입하여 공정을 간단하게 하는 트랜지스터 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a transistor of a semiconductor device, and more particularly, (Hereinafter, referred to as " LDD ") structure is formed by introducing a method of forming a new insulating film spacer.
트랜지스터의 채널영역에서 전자가 가속되어 드레인영역에서 전자가 게이트 전극방향으로 트랩되는 핫 일렉트론이 발생되는 문제점을 극복하기 위하여 소오스/드레인 영역에 저농도 영역인 LDD영역을 구비하는 트랜지스터가 일반화되었다.In order to overcome the problem that electrons are accelerated in the channel region of the transistor and electrons are trapped in the drain region in the direction of the gate electrode, a transistor having an LDD region in a low concentration region in the source / drain region is generalized.
종래의 LDD 구조의 트랜지스터 제조과정을 제1도 내지 제4도를 참조하여 설명하면 다음과 같다.A conventional transistor manufacturing process of an LDD structure will be described with reference to FIGS. 1 to 4.
제1도 내지 제4도는 본 발명의 실시예에 의해 트랜지스터를 제조하는 단계를 도시한 단면도이다.FIGS. 1 to 4 are cross-sectional views showing steps of manufacturing a transistor according to an embodiment of the present invention.
제1도은 반도체기판(1)에 P-웰(2)을 형성하고, 소자분리막(3)을 제조하여 액티브영역을 나눈다음, 액티브영역의 반도체기판(1) 상부에 게이트 산화막(4)과 도전층을 증착한다음, 패턴닝 공정으로 상기 도전층의 일정 부분을 식각하여 게이트 전극(5)을 형성하고, 저농도의 n형 불순물을 상기 P-웰(2)영역으로 주입하여 저농도 영역(6)을 형성한 단면도이다.1 shows a method of manufacturing a semiconductor device in which a P-well 2 is formed in a semiconductor substrate 1, an active region is divided by manufacturing an isolation film 3, The gate electrode 5 is formed by etching a predetermined portion of the conductive layer by a patterning process and a low concentration n-type impurity is injected into the P-well region 2 to form the low concentration region 6, Fig.
제2도는 전체구조 상부에 절연막(7) 예를 들어 산화막을 중착한 단면도이다.FIG. 2 is a cross-sectional view in which an insulating film 7, for example, an oxide film is deposited on the entire structure.
제3도는 상기 절연막(7)을 이방성 식각하여 상기 게이트 전극(5)의 측벽에 스페이서 절연막(7')을 형성한 단면도이다.FIG. 3 is a cross-sectional view of the insulating film 7 anisotropically etched to form a spacer insulating film 7 'on the sidewall of the gate electrode 5. FIG.
제4도는 n+형 고농도 불순물을 이온주입하여 소오스/드레인(8)을 형성한 단면도이다.FIG. 4 is a cross-sectional view in which a source / drain 8 is formed by ion implantation of n + -type high concentration impurity.
그러나, 상기한 종래기술은 절연막(7)을 이방성 식각하는 과정에서 또다른 타입 예를 들어 P형 트랜지스터의 LDD 영역을 보호하기 위해서 상기 P형 트랜지스터의 액티브영역을 감광막으로 도포해 놓은 상태에서 식각을 진행하기 때문에 파티클이 발생하는 문제와 공정이 복잡하다는 문제가 있다.However, in the above-described conventional technique, in the process of anisotropically etching the insulating film 7, in order to protect another type of LDD region of the P-type transistor, for example, the active region of the P- There is a problem that particles are generated and the process is complicated.
본 발명은 상기한 문제점을 해결하기 위하여 LDD영역을 형성하기 위해 형성하는 스페이서 절연막을 새로운 방법을 도입하여 파티클이 발생되는 문제와 고정을 간단히 할 수 있는 트랜지스터 제조방법을 제공하는데 그 목적이 있다.It is another object of the present invention to provide a method of manufacturing a transistor which can simplify the problem of generating particles and fixation by introducing a new method of forming a spacer insulating film for forming an LDD region.
제1도 내지 제4도는 종래 기술에 의해 트랜지스터를 제조하는 단계를 도시한 단면도.FIGS. 1 to 4 are cross-sectional views showing steps of manufacturing a transistor by a conventional technique.
제5도 내지 제9도는 본 발명의 실시예에 의해 트랜지스터를 제조하는 단계를 도시한 단면도.FIGS. 5 to 9 are cross-sectional views illustrating steps of fabricating a transistor according to an embodiment of the present invention. FIG.
* 도면의 주요 부분에 대한 부호의 설명DESCRIPTION OF THE REFERENCE NUMERALS
1, 11 : 반도체 기관 2, 12 : p-웰1, 11: semiconductor body 2, 12: p-well
3, 13 : 소자분리막 4, 14 : 게이트 산화막3, 13: Device isolation film 4, 14: Gate oxide film
5, 15 : 게이트 전극 6, 17 : 저농도 불순물 영역5, 15: gate electrode 6, 17: low concentration impurity region
7' : 스페이서 절연막 8, 19 : 소오스/드레인 영역7 ': spacer insulating film 8, 19: source / drain region
18' : 스페이서용 절연막 패턴18 ': Insulating film pattern for spacer
상기한 목적을 달성하기 위한 본 발명에 따른 반도체소자의트랜지스터 제조방법은, 반도체소자 제조방법에 있어서, 반도체기판 상에 게이트절연막과 게이트 전극을 형성하는 단계와, 상기 게이트전극을 마스크로하여 상기 반도체기판의 표면에 저농도 불순물을 주입하여 저농도 불순물영역을 형성하는 단계와, 상기 저농도의 불순물영역 상부의 반도체기판 표면에 절연막을 성장시키는 단계와, 상기 게이트 전극 측벽에 스페이서로 예정된 영역의 절연막에 불순물을 주입하는 단계와, 상기 불순물이 주입된 부분과 타부분과의 식각선택비 차이를 이용한 식각공정으로 상기 게이트전극 측벽에 절연막 스페이서를 형성하는 단계와, 상기 게이트전극과 스페이서를 마스크로하여 고농도의 고농도 불순물을 이온주입하여 소오스/드레인을 형성하는 단계를 포함하는 것을 특징으로 한다.According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a gate insulating film and a gate electrode on a semiconductor substrate; A step of implanting a low concentration impurity into the surface of the substrate to form a low concentration impurity region; growing an insulating film on the surface of the semiconductor substrate above the low concentration impurity region; Forming an insulating film spacer on the sidewall of the gate electrode by an etching process using an etch selectivity difference between the portion into which the impurity is implanted and the other portion of the gate electrode; Implanting impurities to form a source / drain It characterized in that it comprises.
이하, 첨부된 도면을 참조하여 본 발명을 상세하게 설명하기로 한다.DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제5도 내지 제9도는 본 발명의 바람직한 실시예에 의해 트랜지스터를 제조하는 단계를 도시한 단면도이다.5 to 9 are cross-sectional views showing steps of manufacturing a transistor according to a preferred embodiment of the present invention.
제5도는 반도체기판(11)에 P-웰(12)을 형성하고, 소자분리막(13)을 제조하여 액티브영역을 나눈다음, 액티브영역의 반도체기판(11) 상부에 게이트 산화막(14)과 도전층을 증착한다음, 패턴닝 공정으로 상기 도전층의 일정 부분을 식각하여 게이트 전극(15)을 형성하고, 노출된 반도체기판(11)의 표면에 최초 산화막(16)을 약 250Å의 두께로 성장시킨 다음 저농도 (2-5×1013)의 n+형 불순물을 약 10 ∼ 140 KeV 의 에너지로 상기 P-웰(12)영역으로 주입하여 저농도 영역(17)을 형성한 단면도이다.5 shows a state in which the P-well 12 is formed in the semiconductor substrate 11 and the active region is divided by manufacturing the element isolation film 13 and then the gate oxide film 14 and the conductive film 14 are formed on the semiconductor substrate 11 in the active region. A predetermined portion of the conductive layer is etched by a patterning process to form a gate electrode 15 and a first oxide film 16 is grown on the surface of the exposed semiconductor substrate 11 to a thickness of about 250 angstroms And then a low concentration region 17 is formed by implanting low concentration (2-5 × 10 13 ) n + type impurity into the P-well region 12 at an energy of about 10 to 140 KeV.
제6도은 전체구조 상부에 절연막(18) 예를 들어 산화막을 상기 최초 산화막(16)의 상부에 약 400Å의 두께로 성장시킨 단면도이다.FIG. 6 is a cross-sectional view of an insulating film 18, for example, an oxide film grown on the entire structure to a thickness of about 400 Å on the first oxide film 16.
제7도은 상기 절연막(18)상부에 감광막을 도포하고, 노광 및 현상 공정으로 게이트 전극(15)의 상부 및 스페이서가 형성될 부분의 감광막이 제거된 감광막 패턴(19)을 형성한 후 불순물 예를 들어 불황성 개스, BF2, As, P, 아르곤등을 노출된 절연막(18)으로 이온주입하여 더욱 치밀한 조직을 형성한 단면도이다.7 illustrates a process of forming a photoresist pattern 19 on the upper surface of the gate electrode 15 and a photoresist layer on which a spacer is to be formed by an exposure and development process, For example, incombustible gas, BF 2 , As, P, argon or the like is implanted with the exposed insulating film 18 to form a more dense structure.
제8도은 상기 감광막 패턴(19)을 제거한다음, 상기 절연막(18)을 식각하면 치밀한 조직을 갖는 절연막은 남게되고, 다른 지역의 절연막(18)은 식각되어 게이트 전극(15)의 측벽에 스페이서용 절연막 패턴(18')이 형성된 것을 도시한다.8 shows an example in which after the photoresist pattern 19 is removed and the insulating film 18 is etched, the insulating film having a dense structure remains and the insulating film 18 in another region is etched to form a spacer And the insulating film pattern 18 'is formed.
이때 하부에 있는 최초 산화막(16)은 부분적으로 식각된다.At this time, the underlying oxide film 16 is partially etched.
제9도는 n+형 고농도 불순물 (예를 들어 비소, 1-9×1015)을 약 30-50KeV의 에너지로 이온주입하여 소오스/드레인(20)을 형성한 단면도이다.FIG. 9 is a cross-sectional view in which a source / drain 20 is formed by ion-implanting n + -type high concentration impurity (eg, arsenic, 1-9 × 10 15 ) at an energy of about 30-50 KeV.
상기한 본 발명에 의해 LDD구조의 트랜지스터를 형성하는 공정에서 웨이퍼 상부에 감광막 패턴을 완전히 제거한 상태에서 절연막을 식각하여도 아르곤이 주입된 절연막은 조직이 치밀하여 스페이서용 절연막 패턴으로 남게됨으로써 종래의 스페이서 절연막과 동일하게 이용할 수가 있다.According to the present invention, even if the insulating film is etched while the photoresist pattern is completely removed from the upper part of the wafer in the process of forming the LDD structure transistor, the insulating film into which the argon is implanted remains in the insulating film pattern for the spacer, It can be used in the same manner as the insulating film.
상기한 LDD영역을 형성하기 위해 종래에는 스페이서 절연막을 형성하는 과정에서 또다른 타입 예를 들어 P형 트랜지스터의 LDD영역을 보호하기 위해서 상기 P형 트랜지스터의 액티브영역을 감광막으로 도포해 놓은 상태에서 상기 절연막은 식각을 진행하기 때문에 파티클이 발생하였으나 본 발명은 별도의 감광막 패턴을 다른 타입의 트랜지스터에 도포하지 않은 상태에서 공정을 진행함으로써 파티클이 발생되는 문제가 발생되지 않으며, 공정이 용이하다는 정점이 있다.In order to protect the LDD region of another type, for example, the P-type transistor, the active region of the P-type transistor is coated with a photoresist film in the process of forming the LDD region, However, since the present invention does not apply a separate photoresist pattern to other types of transistors, there is no problem that particles are generated and the process is easy.
상기한 본 발명이 상기 실시예에서 한정되지 않으며 많은 변형이 본 발명의 기술적 사상내에서 당분야에서 통상의 지식을 가진자에 의하여 가능함은 명백하다.It is apparent that the present invention is not limited to the above embodiments and that many modifications are possible within the technical scope of the present invention by those skilled in the art.
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| KR1019960056894A KR100231603B1 (en) | 1996-11-23 | 1996-11-23 | Manufacturing method for transistor of semiconductor device |
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| JPH06333919A (en) * | 1992-11-24 | 1994-12-02 | Sumitomo Metal Ind Ltd | Semiconductor device and its manufacture |
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| JPH06333919A (en) * | 1992-11-24 | 1994-12-02 | Sumitomo Metal Ind Ltd | Semiconductor device and its manufacture |
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| KR19980038048A (en) | 1998-08-05 |
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