KR19980058385A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

SUMMARY OF THE INVENTION The present invention provides a semiconductor device and a method of manufacturing the same, in which a gate insulating film in a portion overlapping a junction region is formed without forming an LDD region, thereby preventing hot carriers and increasing an effective channel length of the device. Method of manufacturing a semiconductor device according to the invention comprises the steps of forming a polysilicon film on a semiconductor substrate on which the device isolation film is formed; Doping the polysilicon film and simultaneously forming an impurity diffusion region in the substrate under the polysilicon film; Forming an insulating film on the doped polysilicon film; Etching the insulating film and the polysilicon film to expose a predetermined region of the field oxide film, and forming a predetermined trench in the substrate to space the impurity diffusion region; Forming insulating film spacers on both sidewalls of the trench and both sidewalls of the etched insulating film and the polysilicon film; Forming a gate insulating film on the bottom of the trench and the spacer where the spacer is formed; And forming a patterned gate in a predetermined shape on the gate insulating film, and further comprising forming a predetermined gathered ion region in the substrate under the trench after forming the spacer. do.

Description

Semiconductor device and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device and a method for manufacturing the same, which increase the effective channel length of the device and prevent hot carriers.

In recent years, with the trend of light and short semiconductor technology, the channel region length between the source and the drain of the unit device has been reduced to 0.5 μm or less. As a result, the potential on the channel from the source to the drain becomes high and a strong electric field is applied to the channel of the MOS, and the electrons in the strong electric field have high energy.

These high energy electrons are called hot carriers. Hot carrier electrons enter the gate oxide and not only make the threshold voltage unstable, but also cause severe punch-through problems, which are fatal to the device. It will be damaged. Therefore, in order to prevent hot carriers, a transistor having a lightly doped drain (LDD) structure has been proposed.

1 is a cross-sectional view showing a transistor of the conventional LDD structure described above, with reference to FIG.

As shown in FIG. 1, a field oxide film 2 for inter-element isolation is formed on a semiconductor substrate 1, and a gate insulating film 3 is formed on a substrate 11 between the field oxide films 2. ) And the gate 4. Subsequently, the LDD region 5 is formed by ion implanting low concentration impurities into the substrate 1 using the gate 4 as an ion implantation mask, and oxide film spacers 6 are formed on both sidewalls of the gate 4. Then, a high concentration impurity is implanted into the substrate 1 by using the gate 4 and the spacer 6 as an ion implantation mask to form a high concentration junction region 7 of a source and a drain. Then, a predetermined annealing is performed to activate the impurities.

However, in the conventional LDD structure transistor, the junction region of the LDD structure self-aligned by the gate and the spacer is partially diffused to the lower portion of the gate after the annealing, and the effective channel length L of the transistor is formed due to the formation of a separate LDD region. Decrease).

In other words, the decrease in the channel length deteriorates the short channel effect characteristic according to the high integration of the device, causing a problem of lowering the electrical characteristics such as punch-through and threshold voltage of the device.

Accordingly, the present invention has been made in view of the above-described problems, and it is possible to increase the effective channel length of the device while preventing hot carriers by forming a thick gate insulating film in a portion overlapping the junction region without forming an LDD region. Its purpose is to provide a semiconductor device and a method of manufacturing the same.

1 is a cross-sectional view showing a transistor of a conventional LDD structure.

2A through 2E are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

11 semiconductor substrate, 12 field oxide film, 13 polysilicon film, 14 junction region, 15 first oxide film, 16 trench, 17 oxide film spacer, 18 gathered ion region, 19 gate oxide film, poly Silicon film, 21: photoresist pattern, 22: gate

A semiconductor device according to the present invention for achieving the above object is a semiconductor substrate; An isolation layer formed on a predetermined portion on the substrate; A gate formed in a predetermined portion on the substrate between the device isolation layers and partially buried into the substrate; A junction region of a source and a drain formed in the substrate on both sides of the gate; And a gate insulating layer formed under the gate and having both sides overlapping the junction region with a predetermined portion, and formed with predetermined spacers at both sides of the gate.

In addition, the method for manufacturing a semiconductor device according to the present invention for achieving the above object comprises the steps of forming a polysilicon film on a semiconductor substrate on which the device isolation film is formed; Doping the polysilicon layer and simultaneously forming an impurity diffusion region in the substrate under the polysilicon layer; Forming an insulating film on the doped polysilicon film; Etching the insulating film and the polysilicon film to expose a predetermined region of the field oxide film, and forming a predetermined trench in the substrate to space the impurity diffusion region; Forming insulating film spacers on both sidewalls of the trench and both sidewalls of the etched insulating film and the polysilicon film; And forming a gate insulating film on the bottom and both sides of the trench where the spacer is formed, and forming a gate patterned in a predetermined shape on the gate insulating film.

The method may further include forming a predetermined gathering ion region in the substrate under the trench after forming the spacer.

In addition, the spacer is characterized in that it serves as a predetermined gate insulating film.

According to the present invention having the above structure, since the gate insulating film in the portion overlapping with the junction region of the source and drain is formed by the spacer, the penetration of impurities by the hot carrier can be suppressed and the reliability of the gate can be improved.

In addition, since the LDD region for preventing the hot carrier is not formed separately, the effective channel length of the device may be increased, and the gathering ion region may be formed to gather the combined particles to prevent leakage current.

EXAMPLE

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.

2A through 2E are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

First, as shown in FIG. 2A, a field oxide film 12 for inter-element separation is formed on a semiconductor substrate 11 by a known method. The polysilicon film 13 is deposited on the entire surface of the substrate, and the polysilicon film 13 is doped with a high concentration of impurities. During the high concentration doping, a predetermined impurity diffusion region is formed in the substrate 11 under the polysilicon film 13.

Subsequently, an insulating first oxide film 15 is formed on the doped polysilicon film 13, and a predetermined photoresist pattern (not shown) is formed on the first oxide film 15 by photolithography. The first oxide film 15 and the polysilicon film 13 are etched by using the photoresist pattern as an etch mask to expose a predetermined region of the field oxide film 12 and a predetermined portion of the substrate 11 having the impurity diffusion region formed thereon. A trench 16 is formed to space the impurity diffusion regions on both sides of the trench 16 to form a junction region 14 of a source and a drain. Then, the photosensitive film pattern is removed by a known method.

As shown in FIG. 2B, a second oxide film is deposited on the structure of FIG. 2A, and the second oxide film is anisotropically blanket-etched to form both sidewalls of the trench 16 and the first oxide film 15 on the field oxide film 12. And oxide film spacers 17 on the sidewalls of the polysilicon film 13. At this time, the spacers 17 formed on both sidewalls of the trench 16 serve as gate oxide layers. Subsequently, carbon ions, which are non-conductive materials, are implanted into the exposed substrate 11 under the trench where the spacers 17 are formed to form gathering ion regions 18 for gathering predetermined particles causing defects.

As shown in FIG. 2C, a gate oxide film 19 is formed on the structure of FIG. 2B, and a polysilicon film 20, which is a gate electrode material, is formed on the gate oxide film 19. Next, the photosensitive film pattern 21 is formed by photolithography on the polysilicon film 20 embedded in the trench 16.

As shown in FIG. 2D, a gate partially embedded in the trench 16 in which the spacers 17 are formed by dry etching the polysilicon layer 20 and the gate oxide layer 19 using the photoresist pattern 21 as an etching mask. (22) is formed and the photosensitive film pattern 21 is removed by a well-known method.

As shown in FIG. 2E, the spacers 17 formed on the sidewalls of the first oxide film 15, the polysilicon film 13, the first oxide film 15, and the polysilicon film 13 are removed.

According to the above embodiment, since the gate oxide film in the portion overlapping the junction region of the source and drain is formed by the oxide spacer, the penetration of impurities by the hot carrier can be suppressed to improve the reliability of the gate. In addition, since the LDD region for preventing the hot carrier is not formed separately, the effective channel length of the device can be increased, and the leakage current can be prevented by gathering defective particles using carbon ions, thereby improving the electrical characteristics and reliability of the device. Can be improved.

In addition, this invention is not limited to the said Example, It can variously deform and implement within the range which does not deviate from the technical summary of this invention.

Claims (9)

Semiconductor substrates; An isolation layer formed on a predetermined portion on the substrate; A gate formed in a predetermined portion on the substrate between the device isolation layers and partially buried into the substrate; A junction region of a source and a drain formed in the substrate on both sides of the gate; And, And a gate insulating layer formed under the gate and having both sides overlapping the junction region with a predetermined portion and formed with a predetermined spacer at both sides of the gate. The semiconductor device according to claim 1, further comprising a gathering ion region formed in said substrate between said junction regions. The semiconductor device of claim 2, wherein the gathering ions are non-conductive ions. 4. The semiconductor device of claim 3, wherein the nonconductive ions are carbon. Forming a polysilicon film on the semiconductor substrate on which the device isolation film is formed; Doping the polysilicon layer and simultaneously forming an impurity diffusion region in the substrate under the polysilicon layer; Forming an insulating film on the doped polysilicon film; Etching the insulating film and the polysilicon film to expose a predetermined region of the field oxide film, and forming a predetermined trench in the substrate to space the impurity diffusion region; Forming insulating film spacers on both sidewalls of the trench and both sidewalls of the etched insulating film and the polysilicon film; Forming a gate insulating layer on the bottom and both sides of the trench where the spacer is formed; And, Forming a patterned gate in a predetermined shape on the gate insulating film. The method of claim 5, further comprising forming a predetermined gathering ion region in the substrate under the trench after forming the spacer. The method of claim 6, wherein the gathering ions are non-conductive ions. 8. The method of claim 7, wherein the nonconductive ions are carbon. 6. The method of claim 5, wherein the spacer acts as a predetermined gate insulating film.