ATE135495T1 - Apparat und verfahren zur herstellung einer speicherzelle mit schwebendem gate und doppelter dielektrikumschicht - Google Patents
Apparat und verfahren zur herstellung einer speicherzelle mit schwebendem gate und doppelter dielektrikumschichtInfo
- Publication number
- ATE135495T1 ATE135495T1 AT90907873T AT90907873T ATE135495T1 AT E135495 T1 ATE135495 T1 AT E135495T1 AT 90907873 T AT90907873 T AT 90907873T AT 90907873 T AT90907873 T AT 90907873T AT E135495 T1 ATE135495 T1 AT E135495T1
- Authority
- AT
- Austria
- Prior art keywords
- layer
- forming
- conducting
- insulating layer
- dielectric layer
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0411—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having floating gates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/68—Floating-gate IGFETs
- H10D30/681—Floating-gate IGFETs having only two programming levels
- H10D30/683—Floating-gate IGFETs having only two programming levels programmed by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/68—Floating-gate IGFETs
- H10D30/6891—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode
- H10D30/6892—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/031—Manufacture or treatment of data-storage electrodes
- H10D64/035—Manufacture or treatment of data-storage electrodes comprising conductor-insulator-conductor-insulator-semiconductor structures
Landscapes
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US36913489A | 1989-06-21 | 1989-06-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ATE135495T1 true ATE135495T1 (de) | 1996-03-15 |
Family
ID=23454223
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AT90907873T ATE135495T1 (de) | 1989-06-21 | 1990-05-08 | Apparat und verfahren zur herstellung einer speicherzelle mit schwebendem gate und doppelter dielektrikumschicht |
Country Status (4)
| Country | Link |
|---|---|
| EP (1) | EP0478577B1 (de) |
| AT (1) | ATE135495T1 (de) |
| DE (1) | DE69025939T2 (de) |
| WO (1) | WO1990016085A1 (de) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5331189A (en) * | 1992-06-19 | 1994-07-19 | International Business Machines Corporation | Asymmetric multilayered dielectric material and a flash EEPROM using the same |
| DE19941684B4 (de) * | 1999-09-01 | 2004-08-26 | Infineon Technologies Ag | Halbleiterbauelement als Verzögerungselement |
| US8320191B2 (en) | 2007-08-30 | 2012-11-27 | Infineon Technologies Ag | Memory cell arrangement, method for controlling a memory cell, memory array and electronic device |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4203158A (en) * | 1978-02-24 | 1980-05-13 | Intel Corporation | Electrically programmable and erasable MOS floating gate memory device employing tunneling and method of fabricating same |
| JPS6046554B2 (ja) * | 1978-12-14 | 1985-10-16 | 株式会社東芝 | 半導体記憶素子及び記憶回路 |
| US4300212A (en) * | 1979-01-24 | 1981-11-10 | Xicor, Inc. | Nonvolatile static random access memory devices |
| US4486769A (en) * | 1979-01-24 | 1984-12-04 | Xicor, Inc. | Dense nonvolatile electrically-alterable memory device with substrate coupling electrode |
| US4328565A (en) * | 1980-04-07 | 1982-05-04 | Eliyahou Harari | Non-volatile eprom with increased efficiency |
| JPS5857750A (ja) * | 1981-10-01 | 1983-04-06 | Seiko Instr & Electronics Ltd | 不揮発性半導体メモリ |
| JPS5933873A (ja) * | 1982-08-20 | 1984-02-23 | Hitachi Ltd | 半導体素子の製造方法 |
| JPS6288368A (ja) * | 1985-10-15 | 1987-04-22 | Seiko Instr & Electronics Ltd | 半導体不揮発性メモリ |
| US4706102A (en) * | 1985-11-07 | 1987-11-10 | Sprague Electric Company | Memory device with interconnected polysilicon layers and method for making |
| JPS6367783A (ja) * | 1986-09-09 | 1988-03-26 | Mitsubishi Electric Corp | 半導体記憶装置 |
| JPH0196950A (ja) * | 1987-10-08 | 1989-04-14 | Fujitsu Ltd | 半導体装置の製造方法 |
-
1990
- 1990-05-08 AT AT90907873T patent/ATE135495T1/de not_active IP Right Cessation
- 1990-05-08 EP EP90907873A patent/EP0478577B1/de not_active Expired - Lifetime
- 1990-05-08 WO PCT/US1990/002555 patent/WO1990016085A1/en not_active Ceased
- 1990-05-08 DE DE69025939T patent/DE69025939T2/de not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| WO1990016085A1 (en) | 1990-12-27 |
| EP0478577A1 (de) | 1992-04-08 |
| EP0478577B1 (de) | 1996-03-13 |
| EP0478577A4 (en) | 1992-07-08 |
| DE69025939D1 (de) | 1996-04-18 |
| DE69025939T2 (de) | 1996-08-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0082256A3 (de) | Verfahren zur Herstellung von Halbleiteranordnungen mit dielektrischen Isolationszonen | |
| EP0797245A3 (de) | Verfahren zur Herstellung von einem vertikalen MOS-Halbleiterbauelement | |
| DE69034023D1 (de) | Verfahren zur Herstellung einer Halbleiteranordnung mit einer leitfähigen Schicht | |
| DE3785872D1 (de) | Verfahren zur herstellung eines selbstjustiert positionierten metallkontaktes. | |
| KR900005565A (ko) | 개선된 패턴 형성방법 | |
| DE3879213D1 (de) | Verfahren zur selbstjustierten herstellung von kontakten zwischen in uebereinander angeordneten verdrahtungsebenen einer integrierten schaltung enthaltenen leiterbahnen. | |
| ATE135495T1 (de) | Apparat und verfahren zur herstellung einer speicherzelle mit schwebendem gate und doppelter dielektrikumschicht | |
| KR970072380A (ko) | 반도체 장치 및 그 제조 방법 | |
| JPS57145340A (en) | Manufacture of semiconductor device | |
| KR910005458A (ko) | 반도체장비의 제조방법 | |
| KR960026585A (ko) | 반도체소자의 소자분리 산화막의 제조방법 | |
| JPS57204146A (en) | Manufacture of semiconductor device | |
| KR910000277B1 (ko) | 반도체 장치의 제조방법 | |
| WO1995028000A3 (en) | Method of manufacturing a semiconductor device with a multilayer wiring structure containing narrow vias | |
| KR970053546A (ko) | 반도체 장치의 금속 배선 형성 방법 | |
| KR910008801A (ko) | 반도체장치의 제조방법 | |
| KR960008559B1 (ko) | 반도체 소자의 미세 콘택홀 형성방법 | |
| KR890011058A (ko) | 반도체 장치의 제조방법 | |
| JPS55130140A (en) | Fabricating method of semiconductor device | |
| KR910005436A (ko) | 패턴층을 이용한 반도체 제조방법 | |
| KR930014802A (ko) | 상, 하부 도전층 사이의 층간절연층 제조방법 | |
| JPS5648151A (en) | Wiring formation of semiconductor device | |
| TW255048B (en) | Planarization method between metal layers | |
| KR960005791A (ko) | 반도체소자의 콘택홀 형성방법 | |
| KR930022473A (ko) | 다층배선 구조를 갖는 반도체 장치의 제조방법 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |