KR850002172A - 반도체장치 제조방법 - Google Patents

반도체장치 제조방법 Download PDF

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Publication number
KR850002172A
KR850002172A KR1019840005363A KR840005363A KR850002172A KR 850002172 A KR850002172 A KR 850002172A KR 1019840005363 A KR1019840005363 A KR 1019840005363A KR 840005363 A KR840005363 A KR 840005363A KR 850002172 A KR850002172 A KR 850002172A
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refractory metal
silicon
semiconductor device
aluminum
film
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KR1019840005363A
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KR890003144B1 (ko
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가즈나리 시라이 (외 2)
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야마모도 다꾸마
후지쓰 가부시끼 가이샤
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/019—Contacts of silicides
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/09—Laser anneal

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

내용 없음

Description

반도체장치 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도 내지 제3도는 본 발명에 따른 장치의 제조처리의 각 단계를 보여주는 반도체장치의 주요부분의 단면도.

Claims (22)

  1. 반도체장치 제조방법에 있어서, 반도체기판위 절연층내에 접촉창(contact window)을 형성하는 단계 절연층위 및 반도체장치 기판위 접촉창내에 내화성금속과 실리콘으로 구성된 막(film)을 증착(deposit)하는 단계, 상기 막의 규화물화를 확실히 하기위해 단기간동안 내화성금속과 실리콘으로 구성된 상기 막을 빔어닐링(beam annealing)하는 단계, 상기 내화성 금속규화물막에 알루미늄 또는 알루미늄 합금충을 증착하여 상기 알루미늄 또는 알루미늄 합금층과 상기 접촉창내 상기 반도체기판사이에 전기적 또는 옴적(ohmic)접촉을 이루는 단계로 구성되어 있는 것을 특징으로 하는 반도체 장치 제조방법.
  2. 제1항에 있어서, 반도체기판은 실리콘으로 되어 있는 것을 특징으로 하는 반도체 장치 제조방법.
  3. 제1항에 있어서, 상기 반도체기판은 접촉창 아래 n형인 것을 특징으로 하는 반도체장치 제조방법.
  4. 제1항에 있어서, 상기 반도체기판은 접촉창 아래 n형 도오프(dope) 영역을 갖고 있는 것을 특징으로 하는 반도체장치 제조방법.
  5. 제1항에 있어서, 상기 접촉창은 정사각형(2㎛ 2㎛)보다 저 작은 크기를 갖고 있는 것을 특징으로 하는 반도체장치 제조방법.
  6. 제1항에 있어서, 상기 내화물 금속은 Mo,W,Ta 및 Ti에서 선정되는 것을 특징으로 하는 반도체장치 제조방법.
  7. 제6항에 있어서, 상기 내화물 금속은 Mo인 것을 특징으로 하는 반도체장치 제조방법.
  8. 제1항에 있어서, 내화물금속 및 실리콘으로 구성되는 막의 상기 증착단계는 공통분사(co-sputtering) 또는 열압착 표적부사(hot press-target-sputtering)에 의해 실행되는 것을 특징으로 하는 반도체장치 제조방법.
  9. 제1항에 있어서, 내화성금속 및 실리콘으로 구성되는 상기 막이 10nm내지 50nm 범위내의 두께로 증착되는 것을 특징으로 하는 반도체장치 제조방법.
  10. 제9항에 있어서, 상기 두께는 대략 30mm인 것을 특징으로 하는 반도체장치 제조방법.
  11. 제1항에 있어서, 상기 빔어닐링단계는 램프어닐링, 레이저어닐링 또는 전자빔어닐링에 의해 실행되는 것을 특징으로 하는 반도체장치 제조방법.
  12. 제11항에 있어서, 상기 빔어닐링 단계는 할로겐 램프어닐링에 의해 실행되는 것을 특징으로 하는 반도체장치 제조방법.
  13. 제1항에 있어서, 내화성금속 및 실리콘으로 구성되는 막의 상기 빔어닐링단계는 60초이내의 시각기간내에 700℃부터 1100℃의 범위 온도에서 실행되는 것을 특징으로 하는 반도체장치 제조방법.
  14. 제13항에 있어서, 상기 시각기간은 20초이내인 것을 특징으로 하는 반도체장치 제조방법.
  15. 제14항에 있어서, 상기 시각기간은 10초이내인 것을 특징으로 하는 반도체장치 제조방법.
  16. 제15항에 있어서, 상기 시각기간은 5초이내인 것을 특징으로 하는 반도체장치 제조방법.
  17. 제13항에 있어서, 상기 내화성금속은 Mo,W,Ta 및 Ti의 그룹으로부터 선정되는 빔어닐링온도는 900℃부터 1050℃범위내에 있는 것을 특징으로 하는 반도체장치 제조방법.
  18. 제13항에 있어서, 상기 내화성금속은 Ti이며 빔어닐링 온도는 800℃부터 1000℃범위내에 있는 것을 특징으로 하는 반도체장치 제조방법.
  19. 제7항에 있어서, 상기 합성몰리브덴규화물은 본질적으로 MoSi2인 것을 특징으로 하는 반도체장치 제조방법.
  20. 제1항에 있어서, 상기 알루미늄합금은 알루미늄 실리콘 또는 알루미늄-구리인 것을 특징으로 하는 반도체장치 제조방법.
  21. 제20항에 있어서, 상기 알루미늄-실리콘 1% 실리콘 알루미늄인 것을 특징으로 하는 반도체장치 제조방법.
  22. 제1항에 있어서, 더우기 배선패턴을 얻기위한 상기 알루미늄 또는 알루미늄-합금층 및 상기 내화성 규화물막으로 구성되어 있는 것을 특징으로 하는 반도체장치 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019840005363A 1983-08-31 1984-08-31 반도체장치 제조방법 KR890003144B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP58159536A JPS6063926A (ja) 1983-08-31 1983-08-31 半導体装置の製造方法
JP58-159536 1983-08-31
JP???58-159536 1983-08-31

Publications (2)

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KR850002172A true KR850002172A (ko) 1985-05-06
KR890003144B1 KR890003144B1 (ko) 1989-08-23

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ID=15695910

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US (1) US4672740A (ko)
EP (1) EP0137701B1 (ko)
JP (1) JPS6063926A (ko)
KR (1) KR890003144B1 (ko)
DE (1) DE3480308D1 (ko)

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Publication number Publication date
KR890003144B1 (ko) 1989-08-23
DE3480308D1 (en) 1989-11-30
JPS6063926A (ja) 1985-04-12
US4672740A (en) 1987-06-16
EP0137701B1 (en) 1989-10-25
EP0137701A1 (en) 1985-04-17

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