KR940007985A - 반도체장치의 배선층 형성방법 - Google Patents

반도체장치의 배선층 형성방법 Download PDF

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KR940007985A
KR940007985A KR1019920016301A KR920016301A KR940007985A KR 940007985 A KR940007985 A KR 940007985A KR 1019920016301 A KR1019920016301 A KR 1019920016301A KR 920016301 A KR920016301 A KR 920016301A KR 940007985 A KR940007985 A KR 940007985A
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layer
wiring layer
metal
diffusion barrier
forming
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KR950009934B1 (ko
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이상인
최길현
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김광호
삼성전자 주식회사
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Priority to JP24594093A priority patent/JP3435194B2/ja
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    • H—ELECTRICITY
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
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    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
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    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
    • H01L21/76856—After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
    • H01L21/76858—After-treatment introducing at least one additional element into the layer by diffusing alloying elements
    • H—ELECTRICITY
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes

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Abstract

절연막 또는 확산방지막의 특성을 개량하여 알루미늄원자의 이동도를 향상시켜 접촉구에 대한 배선층의 단차도포성을 증가시키거나, 접촉구의 매몰을 용이하게 하는 방법이 개시되어 있다. 티타늄, 질화티타늄, 텅스텐티타늄 합금등으로 구성된 확산방지막 또는 절연막을 표면처리한 후, 알루미늄 합금을 증착하면 알루미늄층의 단차 도포성이 향상되는데, 이를 이용하여 저온에서 알루미늄 또는 알루미늄합금 증착하고 열처리하면, 알루미늄원자가 보다 용이하게 접촉구내로 이동하여 접촉구의 매몰도가 향상된다. 또한 상기 표면처리한후 고온 스퍼터링하여 접촉구를 매립할수 있다. 확산방지막을 사용하여 금고 배선층을 형성하는 경우에 확산방지특성은 종래의 확산방지막에 비하여 그대로 유지되면서 접촉구의 금속매몰도는 향상된다.

Description

반도체장치의 배선층 형성방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제11도 내지 제13도는 본 발명의 방법에 의한 반도체장치의 배선층 형성방법의 일 실시예를 나타내기 위한 개략도이고,
제14도 내지 제16도는 본 발명에 의한 개구부 매몰방법의 일실시예를 나타내기 위한 개략도이다.

Claims (26)

  1. 반도체 웨이퍼상에 하지막을 형성하고, 상기 하지막의 표면을 수소처리하여 수소종단(H-termination)시켜 상기 하지막의 표면특성을 개선한 후 금속을 증착하여 배선층을 형성함을 특징으로 하는 반도체장치의 배선층 형성방법.
  2. 제1항에 있어서, 상기 하지막이 개구부를 포함하는 절연막임을 특징으로 하는 반도체장치의 배선층 형성방법.
  3. 제2항에 있어서, 상기 절연막은 반도체 기판상에 형성된 하부 배선층상에 형성됨을 특징으로 하는 반도체장치의 배선층 형성방법.
  4. 제1항에 있어서, 상기 하지막이 확산 방지막임을 특징으로 하는 반도체장치의 배선층 형성방법.
  5. 제4항에 있어서, 상기 확산방지막은 반도체 웨이퍼상에 개구부를 포함하는 절연막을 형성하고, 상기 절연막, 상기 개구부의 내면 및 상기 개구부에 의해 노출된 하부 구조물의 표면상에 상기 확산방지막을 형성함을 특징으로 하는 반도체장치의 배선층 형성방법.
  6. 제5항에 있어서, 상기 하부 구조물이 반도체기판이고, 상기 개구부는 상부도전층과 상기 반도체기판의 불순물이 도핑된 영역을 접촉시키기 위한 접촉구(contact hole)임을 특징으로 하는 반도체장치의 배선층 형성방법.
  7. 제5항에 있어서, 상기 하부 구조물이 하부 배선층이고, 상기 개구부는 상부도전층과 상기 하부 배선층을 접촉시키기 위한 비아홀(via hole)임을 특징으로 하는 반도체장치의 배선층 형성방법.
  8. 제4항에 있어서, 상기 확산방지막은 천이금속, 천이금속합금 및 천이금속화합물로 구성된 군에서 선택된 어느 하나이상으로 이루어짐을 특징으로 하는 반도체장치의 배선층 형성방법.
  9. 제8항에 있어서, 상기 확산방지막은 천이금속으로 구성된 제1확산방지막과 상기 제1확산방지막상에 형성된 천이금속화합물 또는 천이금속합금으로 구성된 제2확산방지막으로 구성됨을 특징으로 하는 반도체장치의 배선층 형성방법.
  10. 제8항 또는 제9항에 있어서, 상기 천이금속이 Ti이고 상기 천이금속 화합물은 TiN이고, 상기 천이금속 합금은 TiW 임을 특징으로 하는 반도체장치의 배선층 형성방법.
  11. 제1항에 있어서, 상기 수소처리공정을 수소 플라즈마 또는 수소라디칼에 상기 확산방지막을 노출시켜 수행함을 특징으로 하는 반도체장치의 배선층 형성방법.
  12. 제2항 또는 제5항에 있어서, 상기 배선층 형성공정은, 수소처리 공정후, 진공을 깨지 않고 제1금속층을 저온에서 증착한 후 열처리하여 개구부를 금속으로 매몰시키는 공정을 포함함을 특징으로 하는 반도체장치의 배선층 형성방법.
  13. 제12항에 있어서, 상기 열처리 공정은 0.8Tm~Tm(Tm은 상기 제1금속층의 금속의 용융점이다)의 온도에서 수행함을 특징으로 하는 반도체장치의 배선층 형성방법.
  14. 제12항에 있어서, 상기 제1금속층의 두께는 상기 배선층두께의 10~80%임을 특징으로 하는 반도체장치의 배선층 형성방법.
  15. 제12항에 있어서, 상기 제1금속층은 Si을 함유하는 알루미늄 합금층과 Si를 함유하지 않는 알루미늄합금층 또는 순수알루미늄층으로 구성된 복합층임을 특징으로 하는 반도체장치의 배선층 형성방법.
  16. 제12항에 있어서, 상기 제1금속층은 Si을 함유하는 알루미늄 합금으로 구성됨을 특징으로 하는 반도체장치의 배선층 형성방법.
  17. 제12항에 있어서, 상기 제1금속층은 Si을 함유하지 않는 알루미늄 합금 또는 알루미늄으로 구성됨을 특징으로 하는 반도체장치의 배선층 형성방법.
  18. 제12항에 있어서, 상기 제1금속층을 150℃이하의 온도에서 증착시킴을 특징으로 하는 반도체장치의 배선층 형성방법.
  19. 제12항에 있어서, 상기 제1금속층을 열처리한 후 제2금속층을 증착하는 공정을 더 포함함을 특징으로 하는 반도체장치의 배선층 형성방법.
  20. 제12항에 있어서, 상기 제2금속층을 350℃이하의 온도에서 증착함을 특징으로 하는 반도체장치의 배선층 형성방법.
  21. 제15항 또는 제16항에 있어서, 상기 제1금속층을 열처리한 후, 순수알루미늄 또는 Si를 함유하지 않는 알루미늄을 증착하여 제2금속층을 형성함을 특징으로 하는 반도체장치의 배선층 형성방법.
  22. 제17항에 있어서, 상기 제1금속층을 열처리한 후 Si을 함유하는 알루미늄 합금을 증착하여 제2금속층을 형성함을 특징으로 하는 반도체장치의 배선층 형성방법.
  23. 제19항에 있어서, 상기 제2금속층을 증착한후 열처리하여 표면을 평탄화시킴을 특징으로 하는 반도체장치의 배선층 형성방법.
  24. 제23항에 있어서, 상기 제2금속층의 열처리는 제2금속층을 0.8Tm~Tm(Tm은 제2금속층을 구성하는 금속의 용융점)의 온도에서 수행함을 특징으로 하는 반도체장치의 배선층 형성방법.
  25. 제3항 또는 제5항에 있어서, 상기 배선층 형성공정은 공온에서 스퍼터링법에 의해 알루미늄 또는 알루미늄합금을 증착하여 형성함을 특징으로 하는 반도체장치의 배선층 형성방법.
  26. 제25항에 있어서, 상기 고온은 0.8Tm 내지 Tm의 범위 내임을 특징으로 하는 반도체장치의 배선층 형성방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019920016301A 1992-09-07 1992-09-07 반도체 장치의 배선층 형성방법 KR950009934B1 (ko)

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KR1019920016301A KR950009934B1 (ko) 1992-09-07 1992-09-07 반도체 장치의 배선층 형성방법
JP24594093A JP3435194B2 (ja) 1992-09-07 1993-09-06 半導体装置の配線層形成方法及び半導体装置
US08/743,916 US5843843A (en) 1992-09-07 1996-11-05 Method for forming a wiring layer a semiconductor device

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990026626A (ko) * 1997-09-25 1999-04-15 윤종용 반도체 공정의 금속배선 형성방법
KR100414306B1 (ko) * 1996-12-30 2004-03-30 주식회사 하이닉스반도체 반도체장치의금속콘택방법
KR100681155B1 (ko) * 2000-06-15 2007-02-09 주성엔지니어링(주) 질화티타늄막 형성방법

Families Citing this family (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6051490A (en) * 1991-11-29 2000-04-18 Sony Corporation Method of forming wirings
KR100413890B1 (ko) * 1995-03-02 2004-03-19 동경 엘렉트론 주식회사 반도체장치의제조방법및제조장치
JPH09275142A (ja) * 1995-12-12 1997-10-21 Texas Instr Inc <Ti> 半導体の空隙を低温低圧で充填を行う処理方法
US6225218B1 (en) 1995-12-20 2001-05-01 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and its manufacturing method
US5909637A (en) * 1996-09-20 1999-06-01 Sharp Microelectronics Technology, Inc. Copper adhesion to a diffusion barrier surface and method for same
JP3725266B2 (ja) 1996-11-07 2005-12-07 株式会社半導体エネルギー研究所 配線形成方法
GB2319532B (en) * 1996-11-22 2001-01-31 Trikon Equip Ltd Method and apparatus for treating a semiconductor wafer
TW408359B (en) * 1997-08-29 2000-10-11 Seiko Epson Corp Semiconductor device and manufacture thereof
US6303505B1 (en) * 1998-07-09 2001-10-16 Advanced Micro Devices, Inc. Copper interconnect with improved electromigration resistance
JP2000133712A (ja) * 1998-08-18 2000-05-12 Seiko Epson Corp 半導体装置の製造方法
US6187673B1 (en) * 1998-09-03 2001-02-13 Micron Technology, Inc. Small grain size, conformal aluminum interconnects and method for their formation
JP3528665B2 (ja) 1998-10-20 2004-05-17 セイコーエプソン株式会社 半導体装置の製造方法
US6303972B1 (en) 1998-11-25 2001-10-16 Micron Technology, Inc. Device including a conductive layer protected against oxidation
US7067861B1 (en) * 1998-11-25 2006-06-27 Micron Technology, Inc. Device and method for protecting against oxidation of a conductive layer in said device
JP3533968B2 (ja) 1998-12-22 2004-06-07 セイコーエプソン株式会社 半導体装置の製造方法
GB2349392B (en) * 1999-04-20 2003-10-22 Trikon Holdings Ltd A method of depositing a layer
TW455961B (en) * 2000-04-25 2001-09-21 Cts Comp Technology System Cor Method for enabling semiconductor wafer to use liquid conductive material
DE10040465A1 (de) * 2000-08-18 2002-03-07 Infineon Technologies Ag Prozessführung für eine Metall/Metall-Kontaktherstellung
US6500757B1 (en) * 2000-11-03 2002-12-31 Advanced Micro Devices, Inc. Method and apparatus for controlling grain growth roughening in conductive stacks
US20020106881A1 (en) * 2000-12-07 2002-08-08 Jain Manoj K. Prevention of contact failure by hydrogen treatment
US7084070B1 (en) 2001-03-30 2006-08-01 Lam Research Corporation Treatment for corrosion in substrate processing
JP4038485B2 (ja) 2003-03-12 2008-01-23 三星エスディアイ株式会社 薄膜トランジスタを備えた平板表示素子
US7211502B2 (en) * 2003-03-26 2007-05-01 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US20040219795A1 (en) * 2003-05-01 2004-11-04 Taiwan Semiconductor Manufacturing Co. Method to improve breakdown voltage by H2 plasma treat
US6881437B2 (en) * 2003-06-16 2005-04-19 Blue29 Llc Methods and system for processing a microelectronic topography
US6860944B2 (en) * 2003-06-16 2005-03-01 Blue29 Llc Microelectronic fabrication system components and method for processing a wafer using such components
US7883739B2 (en) * 2003-06-16 2011-02-08 Lam Research Corporation Method for strengthening adhesion between dielectric layers formed adjacent to metal layers
WO2004114386A2 (en) * 2003-06-16 2004-12-29 Blue29 Corporation Methods and system for processing a microelectronic topography
US20050020061A1 (en) * 2003-07-21 2005-01-27 Jui-Hua Fang Method of modifying conductive wiring
US20070243708A1 (en) * 2006-04-12 2007-10-18 Jens Hahn Manufacturing method for an integrated semiconductor contact structure having an improved aluminum fill
US8541115B2 (en) * 2009-01-30 2013-09-24 United Technologies Corporation Oxide coating foundation for promoting TBC adherence
US8841211B2 (en) * 2010-06-09 2014-09-23 Applied Materials, Inc. Methods for forming interconnect structures
KR20150057148A (ko) * 2013-11-18 2015-05-28 삼성전자주식회사 반도체 장치
JP6772495B2 (ja) * 2016-03-16 2020-10-21 富士電機株式会社 炭化珪素半導体装置および炭化珪素半導体装置の製造方法
US11101128B1 (en) * 2020-03-12 2021-08-24 Applied Materials, Inc. Methods for gapfill in substrates
US20220108914A1 (en) * 2020-10-01 2022-04-07 Applied Materials, Inc. Treatment methods for titanium nitride films
CN113725147B (zh) * 2021-09-02 2023-10-10 长鑫存储技术有限公司 半导体结构制作方法及半导体结构
US12014955B2 (en) * 2022-01-12 2024-06-18 Nanya Technology Corporation Method for fabricating conductive layer stack and method for fabricating semiconductor device with gate contact

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6068614A (ja) * 1983-09-26 1985-04-19 Fujitsu Ltd 半導体装置の製造方法
US4766006A (en) * 1986-05-15 1988-08-23 Varian Associates, Inc. Low pressure chemical vapor deposition of metal silicide
US4783248A (en) * 1987-02-10 1988-11-08 Siemens Aktiengesellschaft Method for the production of a titanium/titanium nitride double layer
US4853347A (en) * 1988-10-03 1989-08-01 Motorola, Inc. Selective metal deposition process
US4994162A (en) * 1989-09-29 1991-02-19 Materials Research Corporation Planarization method
US4970176A (en) * 1989-09-29 1990-11-13 Motorola, Inc. Multiple step metallization process
US5108951A (en) * 1990-11-05 1992-04-28 Sgs-Thomson Microelectronics, Inc. Method for forming a metal contact
DE4028776C2 (de) * 1990-07-03 1994-03-10 Samsung Electronics Co Ltd Verfahren zur Bildung einer metallischen Verdrahtungsschicht und Füllen einer Kontaktöffnung in einem Halbleiterbauelement
KR100228259B1 (ko) * 1990-10-24 1999-11-01 고지마 마따오 박막의 형성방법 및 반도체장치
US5175126A (en) * 1990-12-27 1992-12-29 Intel Corporation Process of making titanium nitride barrier layer
JPH04259242A (ja) * 1991-02-14 1992-09-14 Fujitsu Ltd 半導体装置の製造方法
JPH04280425A (ja) * 1991-03-07 1992-10-06 Sony Corp 配線形成方法
DE4200809C2 (de) * 1991-03-20 1996-12-12 Samsung Electronics Co Ltd Verfahren zur Bildung einer metallischen Verdrahtungsschicht in einem Halbleiterbauelement
US5175125A (en) * 1991-04-03 1992-12-29 Chartered Semiconductor Manufacturing Ltd. Pte Method for making electrical contacts

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100414306B1 (ko) * 1996-12-30 2004-03-30 주식회사 하이닉스반도체 반도체장치의금속콘택방법
KR19990026626A (ko) * 1997-09-25 1999-04-15 윤종용 반도체 공정의 금속배선 형성방법
KR100681155B1 (ko) * 2000-06-15 2007-02-09 주성엔지니어링(주) 질화티타늄막 형성방법

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JP3435194B2 (ja) 2003-08-11
JPH06216263A (ja) 1994-08-05
KR950009934B1 (ko) 1995-09-01

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