KR20210134817A - Semiconductor device - Google Patents

Abstract

An object of the present invention is to provide a semiconductor device capable of retaining the contents of storage even when power is not supplied, and also having no limit on the number of writes.
It has a first wiring, a second wiring, a third wiring, a fourth wiring, a first transistor 160, and a second transistor 162, the first transistor 160 being provided on a substrate including a semiconductor material, The second transistor 162 includes an oxide semiconductor layer, the gate electrode of the first transistor 160 and the source/drain electrode of the second transistor 162 are electrically connected, and the first wiring and the first transistor ( The source electrode of 160 is electrically connected, the second wiring and the drain electrode of the first transistor 160 are electrically connected, and the other of the third wiring and the source/drain electrode of the second transistor 162 is electrically connected. and the fourth wiring and the gate electrode of the second transistor 162 are electrically connected.

Description

semiconductor device {SEMICONDUCTOR DEVICE}

The disclosed invention relates to a semiconductor device using a semiconductor element and a method for manufacturing the same.

A memory device using a semiconductor element is broadly classified into a volatile memory device in which memory contents are lost when power supply is cut off, and a nonvolatile memory device in which memory content is retained even when power supply is cut off.

A typical example of a volatile memory device is a DRAM (Dynamic Random Access Memory). DRAM stores information by selecting transistors constituting a storage element and accumulating electric charges in a capacitor.

From the above principle, in DRAM, since the charge of the capacitor is lost when information is read, a write operation is required again every time data is read. In addition, since a leakage current exists in the transistors constituting the memory element, and charges flow out or flow even when the transistor is not selected, the data retention period is short. Therefore, the write operation (refresh operation) is required again at a predetermined period, and it is difficult to sufficiently reduce the power consumption. In addition, since the contents of the memory disappear when the power supply is cut off, another storage device using a magnetic material or an optical material is required for long-term storage of the memory.

Another example of a volatile memory device is SRAM (Static Random Access Memory). Since the SRAM holds the storage contents using a circuit such as a flip-flop, a refresh operation is unnecessary, and in this respect, it is advantageous over the DRAM. However, since a circuit such as a flip-flop is used, there is a problem that the unit cost per storage capacity becomes high. In addition, there is no difference from DRAM in that the contents of the memory disappear when the power supply is cut off.

A representative example of a nonvolatile memory device is a flash memory. The flash memory has a floating gate between the gate electrode of the transistor and the channel formation region, and the data retention period is very long (semi-permanent) because storage is performed by holding electric charges in the floating gate, and the refresh required for the volatile memory device is It has the advantage that an operation|movement is unnecessary (for example, refer patent document 1).

However, since the gate insulating layer constituting the memory element deteriorates due to the tunnel current generated at the time of writing, there arises a problem that the memory element ceases to function by repeating writing many times. In order to avoid this problem, for example, a method of equalizing the number of writes in each storage element is adopted, but in order to realize this, a complicated peripheral circuit is required. And, even if such a method is adopted, the fundamental problem of life is not solved. That is, the flash memory is not suitable for a use in which the frequency of rewriting information is high.

In addition, a high voltage is required to inject or remove an electric charge into the floating gate. In addition, there is a problem in that a relatively long time is required for the injection or removal of charges, and it is not easy to increase the speed of writing and erasing.

Japanese Patent Application Laid-Open No. 57-105889

In view of the above problems, in one aspect of the disclosed invention, one object is to provide a semiconductor device having a novel structure in which storage contents can be retained even when power is not supplied and the number of writes is not limited.

One aspect of the present invention is a semiconductor device related to a stacked structure of a transistor formed using an oxide semiconductor and a transistor formed using a material other than that. For example, the following configuration can be employed.

One aspect of the present invention provides a first wiring (source line), a second wiring (bit line), a third wiring (first signal line), a fourth wiring (second signal line), a first gate electrode; A substrate comprising: a first transistor having a first source electrode and a first drain electrode; and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode, the first transistor comprising a semiconductor material. is provided, the second transistor includes an oxide semiconductor layer, one of the first gate electrode and the second source electrode or the second drain electrode is electrically connected, and the first wiring (source line) and the first source The electrode is electrically connected, the second wiring (bit line) and the first drain electrode are electrically connected, and the third wiring (first signal line) and the other of the second source electrode or the second drain electrode are electrically connected. and the fourth wiring (second signal line) and the second gate electrode are electrically connected to each other.

In the above, the first transistor has a channel forming region formed in a substrate including a semiconductor material, an impurity region formed to sandwich the channel forming region, a first gate insulating layer over the channel forming region, and a first gate insulating layer over the first gate insulating layer. has a first gate electrode, a first source electrode and a first drain electrode electrically connected to the impurity region.

Further, in the above, the second transistor comprises a second gate electrode over a substrate comprising a semiconductor material, a second gate insulating layer over the second gate electrode, an oxide semiconductor layer over the second gate insulating layer, and an oxide It has a second source electrode and a second drain electrode electrically connected to the semiconductor layer.

Moreover, in the above, it is suitable to employ|adopt a single crystal semiconductor substrate or an SOI substrate as a board|substrate containing a semiconductor material. In particular, it is preferable that the semiconductor material be silicon.

Moreover, in the above, it is preferable that an oxide semiconductor layer contains the oxide semiconductor material of an In-Ga-Zn-O type|system|group. In particular, it is suitable for the _{oxide semiconductor layer to include a crystal of In 2} Ga ₂ ZnO _{7 .} In addition, it is preferable that the hydrogen concentration of the oxide semiconductor layer be 5×10 ¹⁹ atoms/cm ^{3 or less.} Further, off-state current of the second transistor is 1 × 10 ^- is suitable not more than ¹³ A. Further, off-state current of the second transistor is 1 × 10 ^- it is more suitable if less than ²⁰ A.

Further, in the above, the second transistor may be provided in a region overlapping the first transistor.

In addition, the terms "above" and "below" in the present specification do not limit that the positional relationship of the components is "just above" or "just below". For example, in the expression "the first gate electrode on the gate insulating layer", it does not exclude that another component is included between the gate insulating layer and the gate electrode. In addition, the terms "above" and "below" are merely expressions used for the convenience of explanation, and except where specifically mentioned, includes those interchanged above and below.

In addition, the terms "electrode" and "line" in this specification do not functionally limit these components. For example, an "electrode" may be used as a part of a "wiring", and vice versa. In addition, the terms "electrode" and "wiring" include a case where a plurality of "electrodes" and "wiring" are integrally formed.

In addition, the functions of "source" and "drain" may change when transistors of different polarities are employed, when the direction of current changes in circuit operation, and the like. Therefore, in this specification, the terms "source" and "drain" are used interchangeably.

In addition, in this specification, "electrically connected" includes a case in which components are connected through "something having an electrical action". Here, "having a certain electrical action" is not particularly limited as long as it enables transmission and reception of electrical signals between connection objects.

For example, "thing having a certain electrical action" includes not only electrodes and wiring, but also switching elements such as transistors, resistance elements, inductors, capacitors, and elements having various other functions.

In addition, in general, "SOI substrate" refers to a substrate having a configuration in which a silicon semiconductor layer is formed on an insulating surface, but in this specification, a substrate having a configuration in which a semiconductor layer made of a material other than silicon is formed on an insulating surface is also included in its category. use it as That is, the semiconductor layer which the "SOI substrate" has is not limited to a silicon semiconductor layer. In addition, the substrate in "SOI substrate" is not limited to semiconductor substrates, such as a silicon wafer, Non-semiconductor substrates, such as a glass substrate, a quartz substrate, a sapphire substrate, and a metal substrate, are also included. That is, those having a layer made of a semiconductor material on a conductor substrate having an insulating surface or an insulator substrate are also broadly included in the "SOI substrate". In addition, in this specification, a "semiconductor substrate" shall not only refer to the board|substrate which consists only of a semiconductor material, but shall represent the board|substrate which consists of a semiconductor material in general. That is, in this specification, "SOI substrate" is also broadly included in "semiconductor substrate".

In one aspect of the present invention, there is provided a semiconductor device having a transistor using a material other than an oxide semiconductor in a lower portion and a transistor using an oxide semiconductor in an upper portion.

Since the transistor using an oxide semiconductor has a very small off current, it is possible to retain the storage contents for a very long time by using this. That is, since the refresh operation becomes unnecessary or the frequency of the refresh operation can be made extremely low, power consumption can be sufficiently reduced. In addition, even when there is no power supply, it is possible to retain the storage contents over a long period of time.

Further, a high voltage is not required to write information, and there is no problem of device deterioration. In addition, since information is written by switching the on state and off state of the transistor, high-speed operation can be easily realized. In addition, since information can be rewritten by controlling the potential input to the transistor, there is also an advantage that an operation for erasing information is unnecessary.

In addition, since a transistor using a material other than an oxide semiconductor can operate at a new high speed compared to a transistor using an oxide semiconductor, it is possible to read the stored contents at a high speed by using this transistor.

In this way, by integrally providing a transistor using a material other than an oxide semiconductor and a transistor using an oxide semiconductor, it is possible to realize a semiconductor device having an unprecedented characteristic.

1 is a circuit diagram for explaining a semiconductor device;
2 is a cross-sectional view and a plan view for explaining a semiconductor device;
3 is a cross-sectional view for explaining a manufacturing process of a semiconductor device;
4 is a cross-sectional view for explaining a manufacturing process of a semiconductor device;
5 is a cross-sectional view for explaining a manufacturing process of a semiconductor device;
6 is a cross-sectional view for explaining a semiconductor device;
7 is a cross-sectional view for explaining a semiconductor device;
8 is a cross-sectional view for explaining a semiconductor device;
9 is a cross-sectional view for explaining a semiconductor device;
10 is a view for explaining an electronic device using a semiconductor device;
11 is a longitudinal cross-sectional view of an inverted staggered transistor using an oxide semiconductor.
Fig. 12 is an energy band diagram (schematic view) taken along section AA' in Fig. 11;
Fig. 13A shows a state in which a positive potential (+V _G ) is applied to the gate GE1, and Fig. 13B shows a negative potential (-V) to the gate GE1. _G ) A diagram showing the state in which it is assigned.
14 is a diagram showing the relationship between a vacuum level, a work function (φ _M ) of a metal, and an electron affinity (χ) of an oxide semiconductor.
15 is a circuit diagram for explaining a semiconductor device;
16 is a circuit diagram for explaining a semiconductor device;
17 is a circuit diagram for explaining a semiconductor device;
18 is a circuit diagram for explaining a semiconductor device;
19 is a circuit diagram for explaining a semiconductor device;
Fig. 20 is a timing chart showing the relationship between potentials;
21 is a circuit diagram for explaining a semiconductor device;
22 is a cross-sectional view and a plan view for explaining a semiconductor device;
23 is a cross-sectional view for explaining a semiconductor device;
24 is a cross-sectional view for explaining a semiconductor device;
25 is a diagram showing characteristics of a transistor using an oxide semiconductor.
Fig. 26 is a circuit diagram for evaluating characteristics of a transistor using an oxide semiconductor;
Fig. 27 is a timing chart for characteristic evaluation of a transistor using an oxide semiconductor.
Fig. 28 is a diagram showing characteristics of a transistor using an oxide semiconductor;
29 is a diagram showing characteristics of a transistor using an oxide semiconductor;
30 is a diagram showing characteristics of a transistor using an oxide semiconductor.
Fig. 31 is a diagram showing the results of investigation of the memory window width;

An example of embodiment of this invention is demonstrated below using drawings. However, the present invention is not limited to the following description, and it can be easily understood by those skilled in the art that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, this invention is limited to the description of embodiment shown below and is not interpreted.

In addition, in order to facilitate understanding, the position, size, range, etc. of each component shown in the drawings may not show the actual position, size, range, etc. in some cases. Accordingly, the embodiments of the present invention are not necessarily limited to the positions, sizes, ranges, etc. disclosed in the drawings.

It should be noted that, in the present specification, ordinal numbers such as "first", "second", and "third" are added to avoid confusion of components, and are not limited to numbers.

(Embodiment 1)

In this embodiment, the structure and manufacturing method of the semiconductor device which concerns on one aspect|mode of the invention disclosed are demonstrated with reference to FIGS.

<Circuit configuration of semiconductor device>

Fig. 1 shows an example of a circuit configuration of a semiconductor device. This semiconductor device is constituted by a transistor 160 using a material other than an oxide semiconductor (eg, silicon) and a transistor 162 using an oxide semiconductor. Hereinafter, the semiconductor device shown in FIG. 1 may be referred to as a memory cell.

Here, the gate electrode of the transistor 160 and one of the source electrode or the drain electrode of the transistor 162 are electrically connected. In addition, the first wiring (1st Line: also called a source line SL) and the source electrode of the transistor 160 are electrically connected, and the second wiring (2nd Line: also called a bit line BL) and the transistor 160 ) is electrically connected to the drain electrode. Then, the third wiring (3rd line: also referred to as the first signal line S1) and the other one of the source electrode or the drain electrode of the transistor 162 are electrically connected, and the fourth wiring (4th line: second signal line S2) is electrically connected. ) and the gate electrode of the transistor 162 are electrically connected.

Since the transistor 160 using a material other than an oxide semiconductor can perform a new high-speed operation compared to a transistor using an oxide semiconductor, it is possible to read the contents of a memory at a high speed by using the transistor 160 . In addition, the transistor 162 using an oxide semiconductor has a characteristic that an off current is very small. Therefore, by turning off the transistor 162, it is possible to hold the potential of the gate electrode of the transistor 160 for a very long time. In addition, the transistor 162 using an oxide semiconductor has a merit that the short channel effect is difficult to appear.

By taking advantage of the feature that the potential of the gate electrode can be held, it is possible to write, hold, and read information as follows.

First, writing and retention of information will be described. First, the potential of the fourth wiring is set to the potential at which the transistor 162 is turned on, and the transistor 162 is turned on. As a result, the potential of the third wiring is applied to the gate electrode of the transistor 160 (writing). Thereafter, the potential of the fourth wiring is set to the potential at which the transistor 162 is turned off, and the transistor 162 is turned off, so that the potential of the gate electrode of the transistor 160 is retained (retained).

Since the off current of the transistor 162 is very small, the potential of the gate electrode of the transistor 160 is held for a long time. For example, if the potential of the gate electrode of the transistor 160 turns on the transistor 160 , the on state of the transistor 160 is maintained for a long time. Further, if the potential of the gate electrode of the transistor 160 is the potential for turning off the transistor 160 , the off state of the transistor 160 is maintained for a long time.

Next, the reading of information will be described. As described above, when a predetermined potential (low potential) is applied to the first wiring while the on state or off state of the transistor 160 is retained, the first wiring according to the on state or off state of the transistor 160 , The potentials of the 2 wires take different values. For example, when the transistor 160 is in the on state, the potential of the first wiring is affected and the potential of the second wiring is lowered. Conversely, when the transistor 160 is in the off state, the potential of the second wiring does not change.

In the state where the information is held in this way, information can be read by comparing the potential of the second wiring with a predetermined potential.

Next, rewriting of information will be described. Rewriting of information is performed similarly to writing and holding of the above information. That is, the potential of the fourth wiring is set to the potential at which the transistor 162 is turned on, and the transistor 162 is turned on. As a result, the potential of the third wiring (potential relating to new information) is applied to the gate electrode of the transistor 160 . Thereafter, the potential of the fourth wiring is set to the potential at which the transistor 162 is turned off, and the transistor 162 is turned off, so that new information is stored.

In this way, in the semiconductor device according to the disclosed invention, information can be directly rewritten by writing the information again. Therefore, an erase operation required for a flash memory or the like is unnecessary, and a decrease in the operation speed due to the erase operation can be suppressed. That is, high-speed operation of the semiconductor device is realized.

The off current of the write transistor 162 using the oxide semiconductor is very small, and the potential of the gate electrode of the transistor 160 is held for a long time. Accordingly, for example, it is possible to make the refresh operation necessary in the conventional DRAM unnecessary, or to make the frequency of the refresh operation very low (eg, about once a month to once a year). In this way, the semiconductor device of the disclosed invention has characteristics as a practical nonvolatile memory device.

In addition, in the semiconductor device of the disclosed invention, unlike conventional DRAM, information does not disappear upon reading, so there is no need to rewrite information every time it is read. In this way, since the frequency of writing information can be significantly reduced compared with DRAM, it is possible to sufficiently suppress power consumption.

Further, in the semiconductor device of the disclosed invention, it is possible to directly rewrite information by writing the information back to the semiconductor device. Therefore, an erase operation required for a flash memory or the like is unnecessary, and a decrease in the operation speed due to the erase operation can be suppressed. That is, high-speed operation of the semiconductor device is realized. In addition, since the high voltage required for writing or erasing information in the conventional floating gate transistor is not required, the power consumption of the semiconductor device can be further reduced.

In addition, the semiconductor device according to the disclosed invention only needs to include at least a write transistor and a read transistor, and it is possible to make the area per memory cell sufficiently small as compared to an SRAM or the like requiring six transistors per memory cell. . Accordingly, semiconductor devices can be arranged at high density.

In addition, in the conventional floating gate transistor, since electric charges move through the gate insulating film (tunnel insulating film) during writing, deterioration of the gate insulating film (tunnel insulating film) is inevitable. However, in the memory cell according to one aspect of the present invention, since information is written by the switching operation of the write transistor, the deterioration of the gate insulating film, which has been a problem in the past, can be eliminated. This means that, in principle, there is no limit on the number of writes, and the rewrite resistance is very high. For example, no deterioration is seen in the current-voltage characteristic even after writing ^{1×10 9 times (one billion times) or more.}

In addition, the field effect mobility of the write transistor 162 using the oxide semiconductor is 3 cm ² /Vs or more and 250 cm ² /Vs or less, and preferably 5 cm ² /Vs or more and 200 cm ² /Vs or less. , More preferably, 10 cm ² /Vs or more and 150 cm ² /Vs or less. In addition, a transistor using an oxide semiconductor has a subthreshold swing value (S value) of 0.1 V/dec. to be below. By using such a transistor, the time required for writing information can be sufficiently shortened.

In addition, it is preferable that the channel length L of the write transistor 162 using the oxide semiconductor be 10 nm or more and 400 nm or less. By setting such a channel size, various effects such as high-speed operation of the transistor, low power consumption, and high integration can be obtained.

In addition, it is preferable to apply a transistor using crystalline silicon to the read transistor 160 . In particular, from the viewpoint of speeding up the read operation, it is preferable to use an n-channel transistor using single crystal silicon. Such a single crystal silicon transistor can be formed using, for example, bulk silicon (so-called silicon wafer).

In addition, although the above description is for the case of using an n-type transistor (n-channel transistor), it cannot be overemphasized that a p-type transistor can be used instead of the n-type transistor.

<Semiconductor device planar configuration and cross-sectional configuration>

2 is an example of the configuration of the semiconductor device. FIG. 2A shows a cross section of the semiconductor device, and FIG. 2B shows a plane of the semiconductor device. Here, FIG.2(A) corresponds to the cross section along the line A1-A2 and the line B1-B2 of FIG.2(B). The semiconductor device shown in FIGS. 2A and 2B has a transistor 160 using a material other than an oxide semiconductor at a lower portion and a transistor 162 using an oxide semiconductor at an upper portion. In addition, although the transistor 160 and the transistor 162 are both described as an n-type transistor, a p-type transistor may be employ|adopted. In particular, it is easy to make the transistor 160 a p-type.

The transistor 160 includes a channel forming region 116 formed on a substrate 100 including a semiconductor material, an impurity region 114 formed to sandwich the channel forming region 116 and a high-concentration impurity region 120 (in addition to these, simply Also referred to as an impurity region), a gate insulating layer 108 formed over the channel forming region 116 , a gate electrode 110 formed over the gate insulating layer 108 , and a source electrode electrically connected to the impurity region 114 . Alternatively, it has a drain electrode 130a, a source electrode, or a drain electrode 130b.

Here, a sidewall insulating layer 118 is formed on a side surface of the gate electrode 110 . In addition, as shown in the cross-sectional view of the substrate 100 , the high-concentration impurity region 120 is provided in a region that does not overlap the sidewall insulating layer 118 , and the metal compound region 124 is present on the high-concentration impurity region 120 . . In addition, a device isolation insulating layer 106 is formed on the substrate 100 to surround the transistor 160 , and an interlayer insulating layer 126 and an interlayer insulating layer 128 are formed to cover the transistor 160 . have. The source electrode or drain electrode 130a and the source electrode or drain electrode 130b are electrically connected to the metal compound region 124 through openings formed in the interlayer insulating layer 126 and the interlayer insulating layer 128 . That is, the source electrode or drain electrode 130a and the source electrode or drain electrode 130b are electrically connected to the high concentration impurity region 120 and the impurity region 114 through the metal compound region 124 . In addition, the gate electrode 110 is electrically connected to a source electrode or drain electrode 130a or an electrode 130c formed similarly to the source electrode or drain electrode 130b.

The transistor 162 includes a gate electrode 136d formed on the interlayer insulating layer 128 , a gate insulating layer 138 formed on the gate electrode 136d , an oxide semiconductor layer 140 formed on the gate insulating layer 138 , and , a source electrode or drain electrode 142a and a source electrode or drain electrode 142b formed on the oxide semiconductor layer 140 and electrically connected to the oxide semiconductor layer 140 .

Here, the gate electrode 136d is formed to be buried in the insulating layer 132 formed on the interlayer insulating layer 128 . Further, similarly to the gate electrode 136d, the electrode 136a is in contact with the source electrode or drain electrode 130a, the electrode 136b is in contact with the source electrode or drain electrode 130b, and the electrode 136b is in contact with the electrode 130c. 136c) are respectively formed.

In addition, a protective insulating layer 144 is formed on the transistor 162 so as to be in contact with a part of the oxide semiconductor layer 140 , and an interlayer insulating layer 146 is formed on the protective insulating layer 144 . Here, in the protective insulating layer 144 and the interlayer insulating layer 146 , openings reaching the source electrode or drain electrode 142a and the source electrode or drain electrode 142b are formed, and through the opening, the electrode 150d is formed. , the electrode 150e is formed in contact with the source electrode or drain electrode 142a and the source electrode or drain electrode 142b. Further, similarly to the electrodes 150d and 150e, through the openings formed in the gate insulating layer 138, the protective insulating layer 144, and the interlayer insulating layer 146, the electrodes 136a, 136b, An electrode 150a, an electrode 150b, and an electrode 150c in contact with the electrode 136c are formed.

Here, it is preferable that the oxide semiconductor layer 140 is highly purified by sufficiently removing impurities such as hydrogen. Specifically, the hydrogen concentration of the oxide semiconductor layer 140 is 5×10 ¹⁹ atoms/cm ³ or less, preferably 5×10 ¹⁸ atoms/cm ³ or less, and more preferably 5×10 ¹⁷ atoms/cm ³ or less. do it with ^{Thereby, compared with the carrier concentration (about 1×10 14} /cm ³ ) in a general silicon wafer (a silicon wafer to which an impurity element such as phosphorus or boron is added in a trace amount), a value of a sufficiently small carrier concentration (for example, For example, ^{less than 1×10 12} /cm ³ or less than 1.45×10 ¹⁰ /cm ³ ). As described above, by using an oxide semiconductor that has been sufficiently reduced in hydrogen concentration and has been highly purified, intrinsic (i-type) or substantially intrinsic (i-type), the transistor 162 having very excellent off-current characteristics can be obtained. For example, the off current of the transistor 162 at room temperature (25° C.) (here, the value per unit channel width (1 μm)) is 10 zA/μm (1 zA (Zepto Ampere) is 1×10 ^{- 21} A) ) or less, preferably 1 zA/μm or less. In addition, the off current of the transistor 162 at 85 ℃ is, 100 zA / μm (1 × 10 - 19 A / μm) - is less than or less, preferably ^{10 zA / μm (20 A /} μm 1 × 10) . As described above, by applying the oxide semiconductor layer 140 intrinsic or substantially intrinsic with the hydrogen concentration sufficiently reduced to reduce the off-state current of the transistor 162, a semiconductor device having a new configuration can be realized. In addition, the hydrogen concentration in the oxide semiconductor layer 140 mentioned above is measured by secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry).

In addition, an insulating layer 152 is formed on the interlayer insulating layer 146 , and electrodes 154a , 154b , 154c , and 154d are formed so as to be buried in the insulating layer 152 . has been Here, the electrode 154a is in contact with the electrode 150a, the electrode 154b is in contact with the electrode 150b, the electrode 154c is in contact with the electrode 150c and the electrode 150d, and the electrode 154d is in contact with the electrode 150c and the electrode 150d. It is in contact with the silver electrode 150e.

That is, in the semiconductor device shown in FIG. 2 , the gate electrode 110 of the transistor 160 and the source electrode or drain electrode 142a of the transistor 162 are the electrode 130c, the electrode 136c, and the electrode 150c. , are electrically connected through an electrode 154c and an electrode 150d.

<Method for manufacturing semiconductor device>

Next, an example of the manufacturing method of the said semiconductor device is demonstrated. Hereinafter, a method of manufacturing the lower transistor 160 will be described with reference to FIG. 3 , and then, a method of manufacturing the upper transistor 162 will be described with reference to FIGS. 4 and 5 .

<Manufacturing method of lower transistor>

First, a substrate 100 including a semiconductor material is prepared (see FIG. 3A ). As the substrate 100 made of a semiconductor material, a single crystal semiconductor substrate such as silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, or the like can be applied. Here, an example in the case of using a single crystal silicon substrate as the substrate 100 made of a semiconductor material is shown.

A protective layer 102 serving as a mask for forming an element isolation insulating layer is formed on the substrate 100 (see FIG. 3A ). As the protective layer 102, an insulating layer made of, for example, silicon oxide, silicon nitride, silicon nitride oxide or the like can be used. In addition, before and after this step, in order to control the threshold voltage of the transistor, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity may be added to the substrate 100 . When the semiconductor is silicon, phosphorus, arsenic, or the like can be used as the impurity imparting n-type conductivity. Moreover, as an impurity which imparts p-type conductivity, boron, aluminum, gallium, etc. can be used, for example.

Next, etching is performed using the protective layer 102 as a mask, and a part of the substrate 100 in the region not covered with the protective layer 102 (exposed region) is removed. Thereby, an isolated semiconductor region 104 is formed (refer to FIG. 3B). Dry etching is suitable for this etching, but wet etching may be used. The etching gas and the etching liquid can be appropriately selected according to the material to be etched.

Next, an insulating layer is formed so as to cover the semiconductor region 104, and the insulating layer in the region overlapping the semiconductor region 104 is selectively removed to form the element isolation insulating layer 106 (Fig. B) see). This insulating layer is formed using silicon oxide, silicon nitride, silicon nitride oxide, or the like. As a method for removing the insulating layer, there are a polishing treatment such as CMP, an etching treatment, and the like, but any of them may be used. In addition, after the formation of the semiconductor region 104 or after the formation of the element isolation insulating layer 106 , the protective layer 102 is removed.

Next, an insulating layer is formed over the semiconductor region 104, and a layer containing a conductive material is formed over the insulating layer.

The insulating layer is a later gate insulating layer, and has a single-layer structure or a laminated structure of a film containing silicon oxide, silicon nitride oxide, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, etc. obtained by CVD or sputtering. good to do Alternatively, the insulating layer may be formed by oxidizing and nitriding the surface of the semiconductor region 104 by high-density plasma treatment or thermal oxidation treatment. The high-density plasma treatment can be performed using, for example, a rare gas such as He, Ar, Kr, or Xe, and a mixed gas such as oxygen, nitrogen oxide, ammonia, nitrogen or hydrogen. In addition, although the thickness of an insulating layer is not specifically limited, For example, it can be set as 1 nm or more and 100 nm or less.

The layer containing the conductive material can be formed using a metal material such as aluminum, copper, titanium, tantalum, or tungsten. Moreover, you may form the layer containing an electrically-conductive material using semiconductor materials, such as polycrystalline silicon containing an electrically-conductive material. The formation method is not specifically limited, either, Various film-forming methods, such as a vapor deposition method, a CVD method, a sputtering method, and a spin coating method, can be used. In addition, in this embodiment, it shall show about the example in the case of forming the layer containing an electrically-conductive material using a metal material.

Thereafter, the insulating layer and the layer including the conductive material are selectively etched to form the gate insulating layer 108 and the gate electrode 110 (see FIG. 3C ).

Next, an insulating layer 112 covering the gate electrode 110 is formed (see FIG. 3C ). Then, phosphorus (P), arsenic (As), or the like is added to the semiconductor region 104 to form an impurity region 114 having a shallow junction depth with the substrate 100 (see FIG. 3C ). In addition, although phosphorus and arsenic are added here to form an n-type transistor, when forming a p-type transistor, impurity elements, such as boron (B) and aluminum (Al), may be added. Further, a channel formation region 116 is formed under the gate insulating layer 108 of the semiconductor region 104 by the formation of the impurity region 114 (see FIG. 3C ). Here, the concentration of the impurity to be added can be appropriately set, but when the semiconductor element is highly miniaturized, it is preferable to increase the concentration. In addition, although the process of forming the impurity region 114 after forming the insulating layer 112 is employ|adopted here, it is good also as a process of forming the insulating layer 112 after forming the impurity region 114.

Next, the sidewall insulating layer 118 is formed (refer to FIG. 3D). The sidewall insulating layer 118 can be formed in a self-aligning manner by forming an insulating layer to cover the insulating layer 112 and then applying an etching process with high anisotropy to the insulating layer. In this case, the insulating layer 112 may be partially etched to expose the upper surface of the gate electrode 110 and the upper surface of the impurity region 114 .

Next, an insulating layer is formed so as to cover the gate electrode 110 , the impurity region 114 , the sidewall insulating layer 118 , and the like. Then, phosphorus (P), arsenic (As), or the like is added to a region in which the insulating layer is in contact with the impurity region 114 to form a high-concentration impurity region 120 (see Fig. 3E). Thereafter, the insulating layer is removed, and a metal layer 122 is formed to cover the gate electrode 110 , the sidewall insulating layer 118 , the high concentration impurity region 120 , and the like (see FIG. 3E ). . The metal layer 122 can be formed using various film forming methods such as vacuum deposition, sputtering, and spin coating. The metal layer 122 is preferably formed using a metal material that reacts with the semiconductor material constituting the semiconductor region 104 to form a low-resistance metal compound. Examples of such metal materials include titanium, tantalum, tungsten, nickel, cobalt, and platinum.

Next, heat treatment is performed to react the metal layer 122 with the semiconductor material. Thereby, the metal compound region 124 in contact with the high-concentration impurity region 120 is formed (refer to Fig. 3(F)). In addition, when polycrystalline silicon or the like is used as the gate electrode 110 , a metal compound region is also formed in a portion of the gate electrode 110 in contact with the metal layer 122 .

As the heat treatment, for example, heat treatment by irradiation with a flash lamp can be used. Of course, other heat treatment methods may be used, but in order to improve the controllability of the chemical reaction related to the formation of the metal compound, it is preferable to use a method capable of realizing heat treatment in an extremely short time. In addition, the above-mentioned metal compound region is a region formed by a reaction between a metal material and a semiconductor material, and has sufficiently increased conductivity. By forming this metal compound region, the electrical resistance can be sufficiently reduced and device characteristics can be improved. Also, after the metal compound region 124 is formed, the metal layer 122 is removed.

Next, the interlayer insulating layer 126 and the interlayer insulating layer 128 are formed so as to cover the respective structures formed by the above-described steps (see Fig. 3G). The interlayer insulating layer 126 or the interlayer insulating layer 128 may be formed using a material including an inorganic insulating material such as silicon oxide, silicon nitride oxide, silicon nitride, hafnium oxide, aluminum oxide, or tantalum oxide. Moreover, it is also possible to form using organic insulating materials, such as a polyimide and an acrylic resin. In addition, although it is set as the two-layer structure of the interlayer insulating layer 126 and the interlayer insulating layer 128 here, the structure of the interlayer insulating layer is not limited to this. After formation of the interlayer insulating layer 128, it is preferable to planarize the surface by CMP, etching, or the like.

Thereafter, an opening reaching the metal compound region 124 is formed in the interlayer insulating layers 126 and 128, and a source electrode or a drain electrode 130a, a source electrode or a drain electrode 130b are formed in this opening ( 3 (H)). For the source electrode or drain electrode 130a or the source electrode or drain electrode 130b, a conductive layer is formed in a region including an opening by using a PVD method or a CVD method, for example, followed by etching or CMP. It can be formed by removing a part of the said conductive layer using a method.

In addition, when the source electrode or drain electrode 130a or the source electrode or drain electrode 130b is formed by removing a part of the conductive layer, it is preferable to process it so that the surface thereof is flat. For example, when a titanium film or a titanium nitride film is thinly formed in the region including the opening and then the tungsten film is formed so as to be buried in the opening, unnecessary tungsten film, titanium film, titanium nitride film, etc. are removed by subsequent CMP. At the same time as removal, the flatness of the surface can be improved. In this way, by planarizing the surface including the source electrode or drain electrode 130a and the source electrode or drain electrode 130b, it becomes possible to form a good electrode, wiring, insulating layer, semiconductor layer, etc. in a subsequent step. .

In addition, although only the source electrode or drain electrode 130a and the source electrode or drain electrode 130b in contact with the metal compound region 124 are shown here, in this process, the electrode in contact with the gate electrode 110 (eg, For example, the electrode 130c in FIG. 2) and the like can be formed together. There is no particular limitation on the material that can be used as the source electrode or drain electrode 130a, the source electrode or the drain electrode 130b, and various conductive materials can be used. For example, conductive materials such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, and scandium can be used.

As described above, the transistor 160 using the substrate 100 including the semiconductor material is formed. In addition, after the said process, you may form an electrode, wiring, an insulating layer, etc. further. A highly integrated semiconductor device can be provided by employing a multilayer wiring structure comprising a laminated structure of an interlayer insulating layer and a conductive layer as the wiring structure.

<Manufacturing method of upper transistor>

Next, a process for fabricating the transistor 162 on the interlayer insulating layer 128 will be described with reference to FIGS. 4 and 5 . In addition, since FIGS. 4 and 5 show the manufacturing process of various electrodes on the interlayer insulating layer 128, the transistor 162, etc., the transistor 160, etc. existing under the transistor 162 are omitted. .

First, an insulating layer 132 is formed on the interlayer insulating layer 128 , the source or drain electrode 130a , the source or drain electrode 130b , and the electrode 130c (see FIG. 4A ). The insulating layer 132 may be formed using a PVD method, a CVD method, or the like. Further, it can be formed using a material containing an inorganic insulating material such as silicon oxide, silicon nitride oxide, silicon nitride, hafnium oxide, aluminum oxide, or tantalum oxide.

Next, with respect to the insulating layer 132, openings reaching the source electrode or drain electrode 130a, the source electrode or drain electrode 130b, and the electrode 130c are formed. At this time, an opening is also formed in the region where the gate electrode 136d is to be formed later. Then, a conductive layer 134 is formed so as to be buried in the opening (refer to FIG. 4B). The opening may be formed by etching using a mask or the like. This mask can be formed by a method such as exposure using a photomask. As the etching, either wet etching or dry etching may be used, but from the viewpoint of microfabrication, dry etching is preferably used. The conductive layer 134 can be formed by using a film forming method such as a PVD method or a CVD method. Materials that can be used for forming the conductive layer 134 include conductive materials such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, and scandium, alloys thereof, and compounds (eg, nitride). can be heard

More specifically, for example, a method of forming a thin titanium film by a PVD method in a region including an opening, forming a thin titanium nitride film by a CVD method, and then forming a tungsten film so as to be buried in the opening can be applied. have. Here, the titanium film formed by the PVD method reduces the oxide film on the surface of the lower electrode (here, the source electrode or drain electrode 130a, the source electrode or drain electrode 130b, the electrode 130c, etc.), It has the function of reducing the contact resistance of Further, the titanium nitride film formed thereafter has a barrier function for suppressing diffusion of the conductive material. In addition, after forming a barrier film of titanium, titanium nitride, etc., you may form a copper film by a plating method.

After the conductive layer 134 is formed, a part of the conductive layer 134 is removed using an etching process or a method such as CMP to expose the insulating layer 132 , and the electrodes 136a and 136b are removed. , an electrode 136c and a gate electrode 136d are formed (see FIG. 4C ). In addition, when removing a part of the conductive layer 134 to form the electrode 136a, the electrode 136b, the electrode 136c, and the gate electrode 136d, it is preferable to process the surface to be flat. In this way, by planarizing the surfaces of the insulating layer 132, the electrode 136a, the electrode 136b, the electrode 136c, and the gate electrode 136d, a good electrode, wiring, insulating layer, semiconductor layer, etc. It becomes possible to form

Next, a gate insulating layer 138 is formed so as to cover the insulating layer 132 , the electrode 136a , the electrode 136b , the electrode 136c , and the gate electrode 136d (see FIG. 4D ). ). The gate insulating layer 138 may be formed using a CVD method, a sputtering method, or the like. In addition, the gate insulating layer 138 is preferably formed to include silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, or the like. In addition, the gate insulating layer 138 may have a single-layer structure or may have a laminated structure. For example, the gate insulating layer 138 made of silicon oxynitride can be formed by plasma CVD using _{silane (SiH 4 ), oxygen, and nitrogen as source gases.} Although the thickness of the gate insulating layer 138 is not specifically limited, For example, it can be 10 nm or more and 500 nm or less. In the case of a laminated structure, for example, a first gate insulating layer having a film thickness of 50 nm or more and 200 nm or less and a second gate insulating layer having a film thickness of 5 nm or more and 300 nm or less on the first gate insulating layer are laminated. it is suitable if

In addition, since an oxide semiconductor (a highly purified oxide semiconductor) converted into i-type or substantially i-type by removing impurities is very sensitive to an interface state or an interface charge, when using such an oxide semiconductor for an oxide semiconductor layer, the gate The interface with the insulating layer is important. That is, the high quality of the gate insulating layer 138 in contact with the highly purified oxide semiconductor layer is required.

For example, a high-density plasma CVD method using mu wave (2.45 GHz) is suitable in that it can form the high-quality gate insulating layer 138 that is dense and has a high dielectric breakdown voltage. This is because, when the highly purified oxide semiconductor layer and the high-quality gate insulating layer are in contact, the interface level can be reduced and the interface characteristics can be improved.

Of course, as long as a high-quality insulating layer can be formed as the gate insulating layer, other methods such as sputtering or plasma CVD can be applied even when a highly purified oxide semiconductor layer is used. Moreover, you may apply the insulating layer whose film quality and the interface characteristic with an oxide semiconductor layer are modified by the heat processing after formation. In any case, what is necessary is just to form the film quality as the gate insulating layer 138 which is favorable and can form a favorable interface by reducing the density of interface states with an oxide semiconductor layer.

When an impurity is contained in the oxide semiconductor, the bond between the impurity and the main component of the oxide semiconductor is cut by stress such as a strong electric field or high temperature, and the resulting unbonded loss causes a shift in the threshold voltage (Vth). .

By removing as much as possible impurities of the oxide semiconductor, especially impurities such as hydrogen and water, and improving the interface characteristics with the gate insulating layer as described above, it is possible to obtain a transistor that is stable even against stress such as a strong electric field or high temperature. .

Next, an oxide semiconductor layer is formed on the gate insulating layer 138, and the oxide semiconductor layer is processed by etching using a mask or the like to form an island-shaped oxide semiconductor layer 140 (FIG. 4). of (E)).

Examples of the oxide semiconductor layer include In-Ga-Zn-O-based, In-Sn-Zn-O-based, In-Al-Zn-O-based, Sn-Ga-Zn-O-based, Al-Ga-Zn-O-based, Sn-Al-Zn-O-based, In-Zn-O-based, Sn-Zn-O-based, Al-Zn-O-based, In-O-based, Sn-O-based, and Zn-O-based oxide semiconductor layers, especially It is suitable to use an amorphous oxide semiconductor layer. In the present embodiment, an amorphous oxide semiconductor layer is formed by sputtering using an In-Ga-Zn-O-based oxide semiconductor film-forming target as the oxide semiconductor layer. In addition, since the crystallization of the amorphous oxide semiconductor layer can be suppressed by adding silicon to the amorphous oxide semiconductor layer, for example, an oxide semiconductor using a target containing 2 wt% or more and 10 wt% or less of _{SiO 2} You may form a layer.

As a target for producing an oxide semiconductor layer by the sputtering method, the target for oxide semiconductor film-forming which has zinc oxide as a main component, for example can be used. In addition, In, Ga, and (a composition ratio of _{In 2 O 3: Ga 2 O} 3: ZnO = 1: 1: 1 [mol ratio]) for the oxide semiconductor film-forming target containing Zn may be used and the like. Further, as a target for forming an oxide semiconductor film containing In, Ga, and Zn, In ₂ O ₃ :Ga ₂ O ₃ :ZnO = 1:1:2 [mol ratio], or In ₂ O ₃ :Ga ₂ O ₃ A target or the like having a composition ratio of :ZnO = 1:1:4 [mol ratio] may be used. The filling factor of the target for oxide semiconductor film formation is 90 % or more and 100 % or less, Preferably they are 95 % or more (for example, 99.9 %). A dense oxide semiconductor layer is formed by using the target for oxide semiconductor film-forming with a high filling factor.

The atmosphere for forming the oxide semiconductor layer is preferably a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere of a rare gas (typically argon) and oxygen. Specifically, for example, it is preferable to use a high-purity gas in which the concentration of impurities such as hydrogen, water, a compound having a hydroxyl group, or hydride has been removed to about several ppm (preferably about several ppb).

In the formation of the oxide semiconductor layer, the substrate is held in a processing chamber held under reduced pressure, and the substrate temperature is preferably set to 100°C or higher and 600°C or lower, preferably 200°C or higher and 400°C or lower. By forming the oxide semiconductor layer while heating the substrate, the concentration of impurities contained in the oxide semiconductor layer can be reduced. Further, damage to the oxide semiconductor layer due to sputtering is reduced. Then, while removing residual moisture in the processing chamber, a sputtering gas from which hydrogen and water have been removed is introduced to form an oxide semiconductor layer with a metal oxide as a target. In order to remove residual moisture in the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. Further, the exhaust means may be one in which a cold trap is added to the turbo pump. The deposition chamber evacuated using a cryopump exhausts, for example, compounds containing hydrogen atoms, such as hydrogen atoms _{and water (H 2 O), in addition to compounds containing carbon atoms.} The concentration of impurities contained in the oxide semiconductor layer can be reduced.

As conditions for forming the oxide semiconductor layer, for example, the distance between the substrate and the target is 100 mm, the pressure is 0.6 Pa, the direct current (DC) power is 0.5 kW, and the atmosphere is oxygen (oxygen flow rate 100%) atmosphere. conditions may apply. In addition, the use of a pulsed direct current (DC) power supply is preferable because powdery substances (also referred to as particles and dust) generated during film formation can be reduced and the film thickness distribution is also reduced. The thickness of the oxide semiconductor layer is 2 nm or more and 200 nm or less, and preferably 5 nm or more and 30 nm or less. In addition, since the appropriate thickness differs according to the oxide semiconductor material to be applied, what is necessary is just to select the thickness suitably according to the material to be used.

In addition, before forming the oxide semiconductor layer by the sputtering method, it is preferable to perform reverse sputtering to generate plasma by introducing argon gas to remove dust adhering to the surface of the gate insulating layer 138 . Here, reverse sputtering refers to a method in which ions collide with a sputtering target in normal sputtering, but on the contrary, the surface is modified by making ions collide with the treated surface. As a method of making ions collide with the treatment surface, there is a method of generating plasma in the vicinity of the substrate by applying a high-frequency voltage to the treatment surface side in an argon atmosphere. In addition, a nitrogen atmosphere, a helium atmosphere, an oxygen atmosphere, etc. may be used instead of the argon atmosphere.

For the etching of the oxide semiconductor layer, either dry etching or wet etching may be used. Of course, it is also possible to use both in combination. In order to etch into a desired shape, etching conditions (etching gas, etching liquid, etching time, temperature, etc.) are suitably set according to a material.

The etching gas used for dry etching includes, for example, a chlorine-containing gas (chlorine-based gas such as chlorine (Cl ₂ ), boron chloride (BCl ₃ ), silicon chloride (SiCl ₄ ), carbon tetrachloride (CCl ₄ ), etc. ), etc. In addition, gas containing fluorine (fluorine-based gas, for example, carbon _{tetrafluoride (CF 4} ), sulfur fluoride (SF ₆ ), nitrogen fluoride (NF ₃ ), trifluoromethane (CHF ₃ ), etc.), hydrogen bromide (HBr) ), oxygen (O ₂ ), a gas obtained by adding a rare gas such as helium (He) or argon (Ar) to these gases, etc. may be used.

As the dry etching method, a parallel plate RIE (Reactive ion Etching) method or an ICP (Inductively Coupled Plasma: Inductively Coupled Plasma) etching method can be used. The etching conditions (the amount of electric power applied to the coil-type electrode, the amount of electric power applied to the electrode on the substrate side, the temperature of the electrode on the substrate side, etc.) are appropriately set so that the desired shape can be etched.

As an etchant used for wet etching, a solution or the like in which phosphoric acid, acetic acid, and nitric acid are mixed can be used. Further, ITO07N (manufactured by KANTO CHEMICAL CO., INC.) or the like may be used.

Next, the oxide semiconductor layer is preferably subjected to a first heat treatment. By this first heat treatment, the oxide semiconductor layer can be dehydrated or dehydrogenated. The temperature of the first heat treatment is 300°C or higher and 750°C or lower, preferably 400°C or higher and less than the strain point of the substrate. For example, the substrate is introduced into an electric furnace using a resistance heating element or the like, and the oxide semiconductor layer 140 is subjected to heat treatment at 450° C. under a nitrogen atmosphere for 1 hour. During this time, the oxide semiconductor layer 140 does not come into contact with the atmosphere, so that water or hydrogen is not re-mixed.

In addition, the heat treatment apparatus is not limited to an electric furnace, The apparatus which heats a to-be-processed object by heat conduction from media, such as a heated gas, or thermal radiation, may be sufficient. For example, RTA (Rapid Thermal Anneal) devices, such as a GRTA (Gas 　 Rapid 　 Thermal Anneal) device, and an LRTA (Lamp 　 Rapid Thermal Anneal) device, can be used. An LRTA apparatus is an apparatus which heats a to-be-processed object by radiation of light (electromagnetic waves) emitted from lamps, such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, and a high pressure mercury lamp. The GRTA apparatus is an apparatus that performs heat treatment using a high-temperature gas. As the gas, a noble gas such as argon or an inert gas that does not react with the object to be treated by heat treatment such as nitrogen is used.

For example, as the first heat treatment, the substrate may be put into an inert gas heated to a high temperature of 650° C. to 700° C., heated for several minutes, and then the GRTA treatment in which the substrate is taken out from the inert gas may be performed. If the GRTA treatment is used, high-temperature heat treatment in a short time becomes possible. Moreover, since it is a short-time heat treatment, it becomes possible to apply also in the temperature condition exceeding the strain point of a board|substrate.

In addition, the 1st heat treatment is an atmosphere mainly containing nitrogen or a noble gas (helium, neon, argon, etc.), and it is preferable to perform it in the atmosphere which water, hydrogen, etc. are not contained. For example, the purity of nitrogen or a rare gas such as helium, neon, or argon introduced into the heat treatment apparatus is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less).

Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer may crystallize to become microcrystal or polycrystal. For example, the crystallization rate may be 90% or more or 80% or more of a microcrystalline oxide semiconductor layer. In addition, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, an amorphous oxide semiconductor layer containing no crystalline component may be formed.

Also, there is a case where an oxide semiconductor layer in which microcrystals (particle diameters of 1 nm or more and 20 nm or less (typically 2 nm or more and 4 nm or less)) are mixed in an amorphous oxide semiconductor (for example, the surface of the oxide semiconductor layer) .

It is also possible to change the electrical properties of the oxide semiconductor layer by arranging the microcrystals in the amorphous region of the oxide semiconductor layer. For example, when an oxide semiconductor layer is formed using an In-Ga-Zn-O-based target for oxide semiconductor film formation, by forming a microcrystal portion in which crystal grains of _{In 2} Ga ₂ ZnO _{7 having electrical anisotropy are oriented,} , it is possible to change the electrical properties of the oxide semiconductor layer.

More specifically, for example, _{by orienting the crystal grains so that the c-axis of In 2} Ga ₂ ZnO ₇ takes a direction perpendicular to the surface of the oxide semiconductor layer, the conductivity in the direction parallel to the surface of the oxide semiconductor layer is improved. , it is possible to improve insulation in a direction perpendicular to the surface of the oxide semiconductor layer. In addition, the microcrystal portion has a function of suppressing penetration of impurities such as water and hydrogen into the oxide semiconductor layer.

In addition, the oxide semiconductor layer which has the above-mentioned microcrystal part can be formed by heating the oxide semiconductor layer by GRTA process. Moreover, it is possible to form more suitably by using the sputtering target whose content of Zn is smaller than content of In or Ga.

The first heat treatment for the oxide semiconductor layer 140 may be performed on the oxide semiconductor layer before processing on the island-shaped oxide semiconductor layer 140 . In that case, after the first heat treatment, the substrate is taken out from the heating device and a photolithography step is performed.

In addition, since the first heat treatment has an effect of dehydration and dehydrogenation on the oxide semiconductor layer 140 , it may be referred to as a dehydration treatment or a dehydrogenation treatment. These dehydration and dehydrogenation treatments are performed at timings such as after the oxide semiconductor layer is formed, after the source electrode or the drain electrode is stacked on the oxide semiconductor layer 140 , and after the protective insulating layer is formed on the source electrode or the drain electrode. it is possible to do In addition, such dehydration treatment and dehydrogenation treatment are not limited to once, but may be performed multiple times.

Next, a source electrode or a drain electrode 142a and a source electrode or a drain electrode 142b are formed so as to be in contact with the oxide semiconductor layer 140 (see FIG. 4F). The source electrode or drain electrode 142a and the source electrode or drain electrode 142b may be formed by forming a conductive layer to cover the oxide semiconductor layer 140 and then selectively etching the conductive layer.

The conductive layer can be formed using a PVD method including a sputtering method or a CVD method such as a plasma CVD method. In addition, as the material of the conductive layer, an element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten, an alloy containing the above elements as a component, or the like can be used. Any one or a plurality of materials selected from manganese, magnesium, zirconium, beryllium and thorium may be used. Moreover, you may use the material which combined the element selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium with aluminum singly or plural. A single layer structure may be sufficient as a conductive layer, and it is good also as a laminated structure of two or more layers. Examples thereof include a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is laminated on an aluminum film, and a three-layer structure in which a titanium film, an aluminum film, and a titanium film are laminated.

Here, it is suitable to use an ultraviolet-ray, KrF laser beam, or ArF laser beam for exposure at the time of mask formation used for etching.

The channel length L of the transistor is determined by the distance between the lower end of the source or drain electrode 142a and the lower end of the source or drain electrode 142b. Moreover, when exposure is performed with the channel length L of less than 25 nm, mask formation exposure is performed using ultra-ultraviolet (Extreme and Ultraviolet) which has a very short wavelength of several nm - several tens of nm. Ultraviolet exposure has a high resolution and a large depth of focus. Accordingly, the channel length L of the transistor to be formed later can be set to 10 nm or more and 1000 nm or less, and the operation speed of the circuit can be increased. Moreover, since the off current value is very small, power consumption does not need to be large.

In addition, each material and etching conditions are suitably adjusted so that the oxide semiconductor layer 140 may not be removed at the time of the etching of a conductive layer. In addition, depending on the material and etching conditions, in this process, a part of the oxide semiconductor layer 140 may be etched to become an oxide semiconductor layer having a groove portion (concave portion).

An oxide conductive layer may be formed between the oxide semiconductor layer 140 and the source electrode or drain electrode 142a or between the oxide semiconductor layer 140 and the source electrode or drain electrode 142b. The oxide conductive layer and the metal layer for forming the source electrode or drain electrode 142a or the source electrode or drain electrode 142b can be formed continuously (continuous film formation). The oxide conductive layer may function as a source region or a drain region. By forming such an oxide conductive layer, the resistance of the source region or the drain region can be reduced, so that high-speed operation of the transistor is realized.

In addition, in order to reduce the number of masks used and the number of steps, a resist mask may be formed using a multi-gradation mask which is an exposure mask in which transmitted light has a plurality of intensities, and the etching process may be performed using this. A resist mask formed using a multi-gradation mask has a shape (step-like) having a plurality of thicknesses, and since the shape can be further deformed by ashing, it can be used in a plurality of etching steps to be processed into different patterns. That is, a resist mask corresponding to at least two or more types of different patterns can be formed with a single multi-gradation mask. Therefore, since the number of exposure masks can be reduced and the number of corresponding photolithography steps can be reduced, the simplification of the process can be achieved.

In addition, after the above-described process, it is preferable to perform plasma treatment using a gas such as _{N 2} O, N _{2 , or Ar.} By this plasma treatment, water or the like adhering to the exposed surface of the oxide semiconductor layer is removed. Alternatively, the plasma treatment may be performed using a mixed gas of oxygen and argon.

Next, the protective insulating layer 144 is formed in contact with a part of the oxide semiconductor layer 140 without being brought into contact with the atmosphere (see Fig. 4(G)).

The protective insulating layer 144 may be formed by appropriately using a method that does not mix impurities such as water or hydrogen into the protective insulating layer 144 , such as a sputtering method. In addition, the thickness shall be 1 nm or more. Materials that can be used for the protective insulating layer 144 include silicon oxide, silicon nitride, silicon oxynitride, and silicon nitride oxide. In addition, the structure is good also as a single-layer structure, and it is good also as a laminated structure. When forming the protective insulating layer 144, the substrate temperature is preferably set to room temperature or more and 300° C. or less, and the atmosphere is a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a mixture of a rare gas (typically argon) and oxygen. It is suitable to set it as a mixed atmosphere.

When hydrogen is contained in the protective insulating layer 144, the hydrogen penetrates into the oxide semiconductor layer, the extraction of oxygen in the oxide semiconductor layer by hydrogen, etc. occur, so that the back channel side of the oxide semiconductor layer is reduced in resistance. As a result, there is a risk that a parasitic channel may be formed. Therefore, it is important that hydrogen is not used in the formation method so that the protective insulating layer 144 does not contain hydrogen as much as possible.

In addition, it is preferable to form the protective insulating layer 144 while removing residual moisture in the processing chamber. This is to prevent hydrogen, hydroxyl groups, or water from being contained in the oxide semiconductor layer 140 and the protective insulating layer 144 .

In order to remove residual moisture in the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, it is preferable to use a cryopump, an ion pump, or a titanium sublimation pump. Moreover, as an exhaust means, what added the cold trap to a turbo pump may be sufficient. _{Since, for example, a compound containing hydrogen atoms such as hydrogen atoms or water (H 2} O) is removed from the film formation chamber evacuated using the cryopump, the protective insulating layer 144 formed in the film formation chamber is removed. It is possible to reduce the concentration of impurities contained in the

As the sputtering gas used to form the protective insulating layer 144 , a high-purity gas in which the concentration of impurities such as hydrogen, water, a compound containing a hydroxyl group, or hydride is removed to about several ppm (preferably about several ppb). It is preferable to use

Next, it is preferable to perform the second heat treatment (preferably 200°C or more and 400°C or less, for example, 250°C or more and 350°C or less) in an inert gas atmosphere or oxygen gas atmosphere. For example, the second heat treatment is performed at 250 DEG C for 1 hour in a nitrogen atmosphere. By performing the second heat treatment, variations in the electrical characteristics of the transistor can be reduced.

Moreover, you may heat-process 100 degreeC or more and 200 degrees C or less, 1 hour or more and 30 hours or less in air|atmosphere. This heat treatment may be performed while maintaining a constant heating temperature, or may be performed by repeating the temperature increase from room temperature to a heating temperature of 100°C or more and 200°C or less and temperature decrease from the heating temperature to room temperature several times. In addition, you may perform this heat processing under reduced pressure before formation of a protective insulating layer. If the heat treatment is performed under reduced pressure, the heating time can be shortened. Note that this heat treatment under reduced pressure may be performed instead of the second heat treatment, or may be performed before or after the second heat treatment or the like.

Next, an interlayer insulating layer 146 is formed on the protective insulating layer 144 (see Fig. 5(A)). The interlayer insulating layer 146 may be formed using a PVD method, a CVD method, or the like. Further, it can be formed using a material containing an inorganic insulating material such as silicon oxide, silicon nitride oxide, silicon nitride, hafnium oxide, aluminum oxide, or tantalum oxide. After the interlayer insulating layer 146 is formed, it is preferable to planarize the surface thereof by a method such as CMP or etching.

Next, with respect to the interlayer insulating layer 146 , the protective insulating layer 144 , and the gate insulating layer 138 , the electrode 136a , the electrode 136b , the electrode 136c , the source electrode or the drain electrode 142a . , an opening extending to the source electrode or drain electrode 142b is formed, and the conductive layer 148 is formed so as to be buried in this opening (refer to FIG. 5B). The opening can be formed by a method such as etching using a mask. This mask can be formed by methods, such as exposure using a photomask. As the etching, either wet etching or dry etching may be used, but from the viewpoint of microfabrication, dry etching is preferably used. The conductive layer 148 can be formed using a film forming method such as a PVD method or a CVD method. Materials that can be used for forming the conductive layer 148 include conductive materials such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, and scandium, alloys thereof, and compounds (eg, nitride). can be heard

Specifically, for example, a method of forming a thin titanium film by a PVD method in a region including an opening, forming a thin titanium nitride film by a CVD method, and then forming a tungsten film so as to be buried in the opening can be applied. . Here, the titanium film formed by the PVD method is the lower electrode (here, the electrode 136a, the electrode 136b, the electrode 136c, the source or drain electrode 142a, the source electrode or the drain electrode 142b). It has a function of reducing the oxide film formed on the surface and reducing the contact resistance with the lower electrode. Further, the titanium nitride film formed thereafter has a barrier function for suppressing diffusion of the conductive material. In addition, after forming a barrier film of titanium, titanium nitride, etc., you may form a copper film by a plating method.

After the conductive layer 148 is formed, a part of the conductive layer 148 is removed using a method such as etching or CMP, and the interlayer insulating layer 146 is exposed to expose the electrodes 150a and 150b. , an electrode 150c, an electrode 150d, and an electrode 150e are formed (refer to FIG. 5C). In addition, when removing a part of the conductive layer 148 to form the electrode 150a, the electrode 150b, the electrode 150c, the electrode 150d, and the electrode 150e, it is better to process the surface to be flat. desirable. In this way, by planarizing the surfaces of the interlayer insulating layer 146, the electrode 150a, the electrode 150b, the electrode 150c, the electrode 150d, and the electrode 150e, good electrodes, wiring, and insulation are performed in subsequent steps. It becomes possible to form a layer and the like.

Further, the insulating layer 152 is formed, and an opening reaching the electrode 150a, the electrode 150b, the electrode 150c, the electrode 150d, and the electrode 150e is formed in the insulating layer 152, and the opening is formed. After forming the conductive layer so as to be buried in the , an electrode 154d is formed (refer to FIG. 5D). Since this process is the same as the case of forming the electrode 150a, etc., the detail is abbreviate|omitted.

When the transistor 162 is fabricated by the method described above, the hydrogen concentration of the oxide semiconductor layer 140 is 5×10 ¹⁹ atoms/cm ³ or less, and the off current of the transistor 162 is 100 zA/ m or less. By applying the highly purified oxide semiconductor layer 140 with sufficiently reduced hydrogen concentration, the transistor 162 having excellent characteristics can be obtained. In addition, a semiconductor device having excellent characteristics can be fabricated, including the transistor 160 using a material other than an oxide semiconductor at the bottom and the transistor 162 using the oxide semiconductor at the top.

Further, as a semiconductor material that can be compared with an oxide semiconductor, there is silicon carbide (eg, 4H-SiC). Oxide semiconductors and 4H-SiC have several things in common. Carrier density is an example of that. The density of the intrinsic carriers of the oxide semiconductor at room temperature is estimated to be about ^{10 -7} /cm ³ , but this is a very low value like ^{6.7×10 -11} /cm ^{3 in 4H-SiC.} Compared with the intrinsic carrier density of silicon (on the order of 1.4×10 ¹⁰ /cm ³ ), it is well understood that the intrinsic carrier density of oxide semiconductors is very low.

Moreover, since the energy band gap of an oxide semiconductor is 3.0-3.5 eV, and since the energy band gap of 4H-SiC is 3.26 eV, also in a point that both are wide gap semiconductors, an oxide semiconductor and silicon carbide are common.

On the other hand, there is a very large difference between the oxide semiconductor and silicon carbide. It is the process temperature. Since silicon carbide generally requires heat treatment at 1500°C to 2000°C, it is difficult to form a laminated structure with a semiconductor element formed using a semiconductor material other than silicon carbide. It is because a semiconductor substrate, a semiconductor element, etc. will be destroyed at such a high temperature. On the other hand, oxide semiconductors can be manufactured by heat treatment at 300°C to 500°C (below the glass transition temperature, up to about 700°C). It becomes possible to form a semiconductor device by

In addition, unlike the case of silicon carbide, it has the advantage that it is possible to use a substrate having low heat resistance, such as a glass substrate. In addition, the oxide semiconductor has an advantage that energy cost can be sufficiently low compared to silicon carbide in that heat treatment at a high temperature is unnecessary.

Further, in the oxide semiconductor, although many studies have been made on physical properties, the idea of sufficiently reducing the localized level itself in the energy gap is not included. In one aspect of the disclosed invention, a highly purified oxide semiconductor is manufactured by removing water or hydrogen, which may cause localized level formation, from the oxide semiconductor. This is based on the idea of sufficiently reducing the local level itself in the energy gap. In addition, it is possible to manufacture extremely excellent industrial products with highly purified oxide semiconductors.

In addition, it is possible to form a further highly purified (i-type) oxide semiconductor by supplying oxygen to the unbonded loss of the metal caused by oxygen deficiency and reducing the local level caused by the oxygen defect. For example, it is possible to form an oxygen-excessive oxide film in contact with the channel formation region, and supply oxygen from the oxide film to the channel formation region, thereby reducing the local level due to oxygen defects.

Defects in the oxide semiconductor are attributed to a shallow level under the conduction band due to excess hydrogen, a deep level due to a lack of oxygen, or the like. In order to eliminate these defects, hydrogen is thoroughly removed and oxygen is sufficiently supplied.

<Conducting Mechanism of Transistor Using Oxide Semiconductor>

Next, the conduction mechanism of the transistor using the oxide semiconductor will be described with reference to FIGS. 11 to 14 . In addition, in the following description, an ideal situation is assumed for easy understanding.

11 is a cross-sectional view of an inverted staggered transistor using an oxide semiconductor. The oxide semiconductor layer OS is formed on the gate electrode layer GE1 through the gate insulating layer GI, and the source electrode S and the drain electrode D are formed thereon.

Fig. 12(A) and Fig. 12(B) show schematic diagrams of the energy band structure on AA' in Fig. 11 . 12A shows a case in which no voltage is applied to the gate electrode layer (V _G = 0), and no voltage is applied to either the drain electrode or the source electrode, or the same voltage is applied (V G = 0). _S = V _D = 0, or V _S = V _D ). 12B shows a case where a positive voltage (V _D > 0) is applied to the drain electrode and no voltage is applied to the gate electrode layer (V _G = 0) (shown by a broken line), and a positive voltage is applied to the drain electrode A case in which (V _D > 0) is applied and a positive voltage (V _G > 0) is applied to the gate electrode layer (shown by a solid line) is shown. When no voltage is applied to the gate electrode layer, carriers (electrons) are not injected from the source electrode to the oxide semiconductor side due to the high potential barrier, indicating an OFF state in which no current flows. On the other hand, when a positive voltage is applied to the gate electrode layer, the potential barrier is lowered, indicating an ON state in which current flows.

Fig. 13(A) and Fig. 13(B) show energy band diagrams (schematic diagrams) in the cross section of BB' in Fig. 11 . 13A shows an ON state in which a positive potential V _G (V _G > 0) is applied to the gate electrode layer GE1 and carriers (electrons) flow between the source electrode and the drain electrode. . 13B shows a state in which a negative potential (-V _G ) (V _G > 0) is applied to the gate electrode layer GE1 and is in an off state (a state in which minority carriers do not flow).

14 shows the relationship between the vacuum level, the work function (φ _M ) of the metal, and the electron affinity (χ) of the oxide semiconductor.

The metal is degenerating, and the Fermi level lies within the conduction band. On the other hand, the conventional oxide semiconductor is n-type, and its Fermi level (E _f ) is located near the conduction band away from _{the intrinsic Fermi level (E i} ) located at the center of the band gap. Moreover, it is known that a part of hydrogen becomes a donor in an oxide semiconductor and is one of the factors for n-type formation. In addition, it is known that oxygen vacancies are also a factor for n-type formation.

On the other hand, the oxide semiconductor according to one aspect of the disclosed invention removes hydrogen, which is a factor of n-type formation, from the oxide semiconductor, purifies it as much as possible so that elements (impurity elements) other than the main components of the oxide semiconductor are not included, and oxygen It is an oxide semiconductor that is made intrinsic (i-type) or approached intrinsic by removing vacancies. That is, a feature of one aspect of the invention is not to add an impurity element to form i-type, but to remove impurities such as hydrogen and water and oxygen vacancies as much as possible to obtain a highly purified i-type (intrinsic semiconductor) or approach it. Thereby, the Fermi level (E _f ) can be made to the same degree as the intrinsic Fermi level (E _{i ).}

It is known that the band gap (Eg) of the oxide semiconductor is 3.15 eV and the electron affinity (χ) is 4.3 eV. The work function of titanium (Ti) constituting the source electrode and the drain electrode is almost equal to the electron affinity (χ) of the oxide semiconductor. In this case, in the metal-oxide semiconductor interface, a Schottky-type barrier to electrons is not formed.

When the work function (φ _M ) of the metal and the electron affinity (χ) of the oxide semiconductor are the same, when they come into contact, an energy band diagram (schematic diagram) as shown in FIG. 12A can be obtained.

A black circle (●) in FIG. 12(B) represents the former. When a positive potential is applied to the drain electrode, electrons are injected into the oxide semiconductor across the barrier h, and flow toward the drain electrode. The height of the barrier h _{varies depending on the gate voltage V G} , but when a positive drain voltage is applied to the drain electrode, the height of the barrier in FIG. 12A without voltage application, that is, the band gap E _g ) is lower than 1/2.

At this time, as shown in FIG. 13A, electrons move in the vicinity of the interface between the gate insulating layer and the highly purified oxide semiconductor (the lowest energetically stable part of the oxide semiconductor).

Further, as shown in FIG. 13B, when a negative potential is applied to the gate electrode GE1, the minority carrier holes are substantially zero, so that the current becomes infinitely close to zero.

For example, the off current at room temperature (25 ℃) 10 zA / μm (1 × 10 - 20 A / μm) or less, or 1 zA / μm (1 × 10 - 21 A / μm) or less, and because , a transistor having a subthreshold swing value (S value) of 0.1 V/dec. can be obtained.

In this way, by purifying the oxide semiconductor so that impurities other than the main component of the oxide semiconductor are not contained as much as possible, the operation of the transistor can be improved.

<Modified example>

6 to 9 show modified examples of the configuration of the semiconductor device. Hereinafter, as a modified example, a configuration of the transistor 162 different from the above will be described. That is, the configuration of the transistor 160 is as described above.

In FIG. 6 , a gate electrode 136d is provided under the oxide semiconductor layer 140 , and a source electrode or a drain electrode 142a or a source electrode or a drain electrode 142b is an oxide on the lower surface of the oxide semiconductor layer 140 . An example of a semiconductor device having a transistor 162 in contact with the semiconductor layer 140 is shown. In addition, since the structure of a plane may just change suitably corresponding to a cross section, it will show only about a cross section here.

The major difference between the configuration shown in FIG. 6 and the configuration shown in FIG. 2A is the position of the source electrode or drain electrode 142a or the connection between the source electrode or drain electrode 142b and the oxide semiconductor layer 140 . there is That is, in the configuration shown in FIG. 2A , the upper surface of the oxide semiconductor layer 140 is in contact with the source electrode or drain electrode 142a or the source electrode or drain electrode 142b, compared to that in FIG. 6 . In the illustrated configuration, on the lower surface of the oxide semiconductor layer 140 , the source electrode or the drain electrode 142a or the source electrode or the drain electrode 142b is in contact. And the arrangement|positioning of another electrode, an insulating layer, etc. originates in this difference in contact position is different. The details of each component are as shown in FIG. 2 .

Specifically, the semiconductor device shown in FIG. 6 has a gate electrode 136d formed over the interlayer insulating layer 128, a gate insulating layer 138 formed over the gate electrode 136d, and a gate insulating layer 138 formed over the gate electrode 136d. It has a source electrode or drain electrode 142a, a source electrode or drain electrode 142b, and an oxide semiconductor layer 140 in contact with the upper surface of the source electrode or drain electrode 142a and the source electrode or drain electrode 142b.

Here, the gate electrode 136d is formed to be buried in the insulating layer 132 formed on the interlayer insulating layer 128 . Further, similarly to the gate electrode 136d, the electrode 136a is in contact with the source electrode or drain electrode 130a, the electrode 136b is in contact with the source electrode or drain electrode 130b, and the electrode 136b is in contact with the electrode 130c. 136c) are respectively formed.

In addition, a protective insulating layer 144 is formed on the transistor 162 so as to be in contact with a part of the oxide semiconductor layer 140 , and an interlayer insulating layer 146 is formed on the protective insulating layer 144 . Here, in the protective insulating layer 144 and the interlayer insulating layer 146 , openings reaching the source electrode or drain electrode 142a and the source electrode or drain electrode 142b are formed, and through the opening, the electrode 150d is formed. , the electrode 150e is formed in contact with the source electrode or drain electrode 142a and the source electrode or drain electrode 142b. Further, similarly to the electrodes 150d and 150e, through the openings formed in the gate insulating layer 138, the protective insulating layer 144, and the interlayer insulating layer 146, the electrodes 136a, 136b, An electrode 150a, an electrode 150b, and an electrode 150c in contact with the electrode 136c are formed.

In addition, an insulating layer 152 is formed on the interlayer insulating layer 146 , and electrodes 154a , 154b , 154c , and 154d are formed so as to be buried in the insulating layer 152 . has been Here, the electrode 154a is in contact with the electrode 150a, the electrode 154b is in contact with the electrode 150b, the electrode 154c is in contact with the electrode 150c and the electrode 150d, and the electrode 154d is in contact with the electrode 150c and the electrode 150d. It is in contact with the silver electrode 150e.

7 is an example of a configuration of a semiconductor device having a gate electrode 136d on the oxide semiconductor layer 140 . Here, FIG. 7A is an example of a configuration in which the source electrode or drain electrode 142a or the source electrode or drain electrode 142b is in contact with the oxide semiconductor layer 140 on the lower surface of the oxide semiconductor layer 140, , FIG. 7B is an example of a configuration in which the source electrode or drain electrode 142a or the source electrode or drain electrode 142b is in contact with the oxide semiconductor layer 140 on the upper surface of the oxide semiconductor layer 140. .

A major difference between the configuration shown in FIG. 2A or FIG. 6 and the configuration shown in FIG. 7 is that the gate electrode 136d is provided on the oxide semiconductor layer 140 . In addition, the major difference between the configuration shown in FIG. 7A and the configuration shown in FIG. 7B is that the source electrode or drain electrode 142a, or the source electrode or drain electrode 142b, is the oxide semiconductor layer 140 . The point of contact is on either the lower surface or the upper surface of And due to such a difference, arrangement|positioning of other electrodes, an insulating layer, etc. is different. Details of each component are the same as in FIG. 2 .

Specifically, the semiconductor device illustrated in FIG. 7A includes a source electrode or drain electrode 142a, a source electrode or drain electrode 142b formed on the interlayer insulating layer 128, and a source electrode or drain electrode ( 142a), an oxide semiconductor layer 140 in contact with the upper surface of the source electrode or drain electrode 142b, a gate insulating layer 138 formed on the oxide semiconductor layer 140, and an oxide semiconductor on the gate insulating layer 138 The gate electrode 136d has a region overlapping the layer 140 .

In addition, in FIG. 7B , the oxide semiconductor layer 140 formed on the interlayer insulating layer 128 , the source electrode or drain electrode 142a formed so as to be in contact with the upper surface of the oxide semiconductor layer 140 , the source electrode Alternatively, the drain electrode 142b, the oxide semiconductor layer 140, the source electrode or drain electrode 142a, and the gate insulating layer 138 formed on the source electrode or drain electrode 142b, and the gate insulating layer 138 The gate electrode 136d has a region overlapping the oxide semiconductor layer 140 above.

Moreover, in the structure shown in FIG. 7, compared with the structure etc. shown in FIG. 2, a component may be abbreviate|omitted (for example, the electrode 150a, the electrode 154a, etc.). In this case, a secondary effect of simplification of the manufacturing process can also be obtained. Of course, it goes without saying that even in the configuration shown in Fig. 2, non-essential components can be omitted.

8 is a case in which the device has a relatively large size, and is an example of a configuration in which the gate electrode 136d is provided under the oxide semiconductor layer 140 . In this case, since the requirements for surface flatness and coverage are relatively gentle, it is not necessary to form wirings, electrodes, etc. so as to be buried in the insulating layer. For example, it is possible to form the gate electrode 136d or the like by patterning after the formation of the conductive layer. In addition, although not shown here, the transistor 160 can also be manufactured similarly.

A major difference between the configuration shown in FIG. 8A and the configuration shown in FIG. 8B is that the source electrode or drain electrode 142a or the source electrode or drain electrode 142b is formed in the oxide semiconductor layer 140 . The point of contact is on the lower surface or upper surface of And due to such a difference, arrangement|positioning of other electrodes, an insulating layer, etc. is different. The details of each component are the same as in FIG. 2 .

Specifically, the semiconductor device in FIG. 8A has a gate electrode 136d formed over the interlayer insulating layer 128 , a gate insulating layer 138 formed over the gate electrode 136d, and a gate insulating layer ( The oxide semiconductor layer 140 formed on the 138 and in contact with the upper surface of the source electrode or drain electrode 142a, the source electrode or drain electrode 142b and the source electrode or drain electrode 142a, the source electrode or the drain electrode 142b ) has

Further, in the semiconductor device in FIG. 8B , a gate electrode 136d formed over the interlayer insulating layer 128 , a gate insulating layer 138 formed over the gate electrode 136d , and a gate insulating layer 138 . The oxide semiconductor layer 140 formed in a region overlapping the gate electrode 136d, the source electrode or drain electrode 142a, and the source electrode or drain electrode 142b formed to be in contact with the upper surface of the oxide semiconductor layer 140 ) has

In addition, even in the structure shown in FIG. 8, compared with the structure etc. shown in FIG. 2, a component may be abbreviate|omitted. Also in this case, the effect of simplification of a manufacturing process can be acquired.

9 is a case in which the device has a relatively large size, and is an example of a configuration in which the gate electrode 136d is disposed on the oxide semiconductor layer 140 . Also in this case, since the requirements for surface flatness and coverage are relatively gentle, it is not necessary to form wirings, electrodes, etc. so as to be buried in the insulating layer. For example, it is possible to form the gate electrode 136d or the like by patterning after the formation of the conductive layer. In addition, although not shown here, the transistor 160 can also be manufactured similarly.

The major difference between the configuration shown in FIG. 9A and the configuration shown in FIG. 9B is that the source electrode or drain electrode 142a, or the source electrode or drain electrode 142b, is located below the oxide semiconductor layer 140 . The point is where the surface or the upper surface is in contact. And due to such a difference, arrangement|positioning of other electrodes, an insulating layer, etc. is different. Details of each component are the same as in FIG. 2 .

Specifically, in the semiconductor device of FIG. 9A , a source electrode or drain electrode 142a, a source electrode or drain electrode 142b, and a source electrode or drain electrode 142a formed on the interlayer insulating layer 128 are , the oxide semiconductor layer 140 in contact with the upper surface of the source electrode or drain electrode 142b, the source electrode or drain electrode 142a, the source electrode or drain electrode 142b, and the gate insulation formed on the oxide semiconductor layer 140 It has a layer 138 and a gate electrode 136d formed in a region overlapping the oxide semiconductor layer 140 on the gate insulating layer 138 .

Further, in the semiconductor device of FIG. 9B , the oxide semiconductor layer 140 formed on the interlayer insulating layer 128 and the source electrode or drain electrode 142a formed so as to be in contact with the upper surface of the oxide semiconductor layer 140 . , the source electrode or drain electrode 142b, the source electrode or drain electrode 142a, the source electrode or drain electrode 142b, the gate insulating layer 138 formed on the oxide semiconductor layer 140, and the gate insulating layer 138 ) and a gate electrode 136d formed in a region overlapping the oxide semiconductor layer 140 thereon.

Moreover, also in the structure shown in FIG. 9, compared with the structure etc. shown in FIG. 2, a component may be abbreviate|omitted in some cases. Also in this case, the effect of simplification of a manufacturing process can be acquired.

As described above, according to one aspect of the disclosed invention, a semiconductor device having a new configuration is realized. Although the example in which the transistor 160 and the transistor 162 are laminated|stacked and formed is demonstrated in this embodiment, the structure of a semiconductor device is not limited to this. In the present embodiment, an example has been described in which the channel length directions of the transistor 160 and the transistor 162 are perpendicular to each other, but the positional relationship between the transistor 160 and the transistor 162 is not limited thereto. . In addition, the transistor 160 and the transistor 162 may be provided overlapping each other.

In addition, in this embodiment, in order to simplify understanding, although the semiconductor device of the minimum storage unit (1 bit) was demonstrated, the structure of a semiconductor device is not limited to this. A more advanced semiconductor device can also be configured by appropriately connecting a plurality of semiconductor devices. For example, it is possible to construct a NAND type or NOR type semiconductor device by using a plurality of the above semiconductor devices. The configuration of the wiring is also not limited to FIG. 1 and can be appropriately changed.

The semiconductor device according to the present embodiment can retain information for a very long time due to the low off-current characteristic of the transistor 162 . That is, the refresh operation required for DRAM or the like is unnecessary, and power consumption can be suppressed. Moreover, it can be used as a substantially nonvolatile semiconductor device.

Further, since information is written or the like by the switching operation of the transistor 162, a high voltage is not required and there is no problem of device deterioration. In addition, since information is written or erased by the on and off states of the transistors, high-speed operation can be easily realized. Further, since information can be directly rewritten by controlling the potential input to the transistor, there is also an advantage that an operation for erasing information required for a flash memory or the like is unnecessary.

In addition, since a transistor using a material other than an oxide semiconductor can operate at a new high speed compared to a transistor using an oxide semiconductor, it is possible to read the stored contents at a high speed by using this transistor.

The structure, method, etc. shown in this embodiment can be used combining the structure, method, etc. which are shown in another embodiment suitably.

(Embodiment 2)

In this embodiment, the configuration and manufacturing method of a semiconductor device according to another aspect of the disclosed invention will be described with reference to FIG. 15 .

Fig. 15A shows an example of a circuit configuration of a semiconductor device. The difference from FIG. 1 is the presence or absence of the capacitor 164 . That is, in FIG. 15A , one of the source electrode or the drain electrode of the transistor 162 , one of the electrodes of the capacitor 164 , and the gate electrode of the transistor 160 are electrically connected. Further, the first wiring (1st Line: also called a source line BL) and the source electrode of the transistor 160 are electrically connected, and the second wiring (2nd Line: also called a bit line BL) and the transistor 160 ) is electrically connected to the drain electrode. Further, the third wiring (3rd line: also called the first signal line S1) and the other one of the source electrode or the drain electrode of the transistor 162 are electrically connected, and the fourth wiring (4th line: second signal line S2) is electrically connected. ) and the gate electrode of the transistor 162 are electrically connected. Then, the fifth wiring (5th Line: also referred to as a word line WL) and the other electrode of the capacitor 164 are electrically connected. In addition, in FIG. 15, in order to show that it is a transistor using an oxide semiconductor, the code|symbol of OS is attached together.

Here, the transistor using the oxide semiconductor described above is applied to the transistor 162 . A transistor using an oxide semiconductor has a characteristic that an off current is very small. Therefore, by turning off the transistor 162, it is possible to hold the potential of the gate electrode of the transistor 160 for a very long time. And, by having the capacitor 164, the charge applied to the gate electrode of the transistor 160 can be easily held, and the held information can be read easily.

Also, the transistor 160 is not particularly limited. From the viewpoint of improving the reading speed of information, it is preferable to apply a transistor having a high switching speed, such as a transistor using single crystal silicon.

In the semiconductor device shown in FIG. 15A, by taking advantage of the feature that the potential of the gate electrode of the transistor 160 can be held, writing, holding, and reading of information are possible as follows.

First, writing and retention of information will be described. First, the potential of the fourth wiring is set to the potential at which the transistor 162 is turned on, and the transistor 162 is turned on. As a result, the potential of the third wiring is applied to the gate electrode of the transistor 160 and the capacitor 164 . That is, a predetermined charge is applied to the gate electrode of the transistor 160 (write). Here, the transistor 160 is selected from one of the two different electric potentials (hereinafter, a charge imparting a low potential is referred to as a charge (Q _L ) and a charge imparting a high potential is referred to as a charge (Q _{H )).} It is assumed that the gate electrode of In addition, the storage capacity may be improved by applying electric charges that impart three or more different potentials. Thereafter, the potential of the fourth wiring is set to the potential at which the transistor 162 is turned off, and the transistor 162 is turned off, so that the charge applied to the gate electrode of the transistor 160 is retained (retained).

Since the off current of the transistor 162 is very small, the electric charge of the gate electrode of the transistor 160 is retained for a long time.

Next, the reading of information will be described. When a predetermined potential (positive potential) is applied to the first wiring and an appropriate potential (read potential) is applied to the fifth wiring, the second wiring will have a different potential depending on the amount of charge held in the gate electrode of the transistor 160 . take In general, when the transistor 160 is of the n-channel type, the apparent threshold value (V _{th_H ) when Q H is applied to the gate electrode of the transistor 160 is obtained when Q L} is applied to the gate electrode of the transistor 160 . This is because it is lower than the apparent threshold value (V _{th_L ) of the case.} Here, it is assumed that the apparent threshold voltage refers to the potential of the fifth wiring necessary to turn the transistor 160 into an “on state”. Accordingly, by the potential of the fifth wiring to an intermediate potential (V ₀₎ of the V _th and V _{th_L _H,} it is possible to determine the charge applied to the gate electrode of the transistor 160. For example, in writing, in the case that Q is _H is given, when the potential of the fifth wiring _{V 0 (> V th _H)} , transistor 160 is an "on-state". If there were Q _L is added, the potential of the fifth wiring V ₀ may be a (> V _{th _L),} the transistor 160 is less than the "off state". Therefore, by looking at the potential of the second wiring, the stored information can be read out.

Further, when the memory cells are arranged and used in an array shape, it is required that only the information of a desired memory cell can be read out. In this way, when information of a predetermined memory cell is read and information of other memory cells is not read, the transistor 160 irrespective of the state of the gate electrode for the fifth wiring of the memory cell that is not the target of reading. It may be the potential that the "off-state", that is, given the small potential than V _{th _H.} Or, the potential, the transistor 160 regardless of the gate electrode state is "turned on", i.e., may be given a greater potential than V _{th _L} to the fifth wiring.

Next, rewriting of information will be described. Rewriting of information is performed similarly to writing and holding of the information. That is, the potential of the fourth wiring is set to the potential at which the transistor 162 is turned on, and the transistor 162 is turned on. As a result, a potential of the third wiring (a potential related to new information) is applied to the gate electrode of the transistor 160 and the capacitor 164 . Thereafter, the potential of the fourth wiring is set to the potential at which the transistor 162 is turned off, and the transistor 162 is turned off. do.

In this way, in the semiconductor device according to the disclosed invention, information can be directly rewritten by writing the information again. Therefore, it is unnecessary to extract the electric charge from the floating gate using a high voltage required for a flash memory or the like, and it is possible to suppress a decrease in the operation speed due to the erase operation. That is, high-speed operation of the semiconductor device is realized.

Further, the source electrode or the drain electrode of the transistor 162 is electrically connected to the gate electrode of the transistor 160 , thereby obtaining an action equivalent to that of a floating gate of a floating gate transistor used as a nonvolatile memory element. Accordingly, in the drawing, a portion where the source electrode or drain electrode of the transistor 162 and the gate electrode of the transistor 160 are electrically connected is sometimes referred to as a floating gate portion FG. When the transistor 162 is off, it can be considered that the floating gate portion FG is buried in an insulator, and electric charges are held in the floating gate portion FG. Since the amount of the off current of the transistor 162 using the oxide semiconductor is 1/100,000 or less of the amount of the off current of a transistor formed of a silicon semiconductor or the like, the leakage of the transistor 162 causes the floating gate portion FG It is possible to ignore the dissipation of the charge accumulated in the That is, by the transistor 162 using an oxide semiconductor, it is possible to realize a nonvolatile memory device capable of retaining information even without power supply.

For example, the off current at room temperature (25 ℃) of the transistor (162) 10 zA (1 zA ( jepto amps) is 1 × 10 ^{- 21} A) or less, the capacitance of the capacitor element (164) 10 fF In this case, it is possible to retain data for ^{at least 10 4 seconds.} It goes without saying that this retention time varies depending on transistor characteristics and capacitance values.

Further, in this case, there is no problem of deterioration of the gate insulating film (tunnel insulating film) pointed out in the conventional floating gate transistor. That is, the deterioration of the gate insulating film when electrons are injected into the floating gate, which has been a conventional problem, can be ignored. This means that, in principle, there is no limit on the number of writes. Also, the high voltage required for writing or erasing in the conventional floating gate transistor is unnecessary.

In the semiconductor device shown in FIG. 15A, elements such as a transistor constituting the semiconductor device include resistors and capacitors, and can be thought of as in FIG. 15B. That is, in FIG. 15B , it is considered that the transistor 160 and the capacitor 164 each include a resistor and a capacitor. R1 and C1 are the resistance value and capacitance value of the capacitor 164 , respectively, and the resistance value R1 corresponds to the resistance value of the insulating layer constituting the capacitor element 164 . In addition, R2 and C2 are the resistance value and capacitance value of the transistor 160, respectively, and the resistance value R2 corresponds to the resistance value of the gate insulating layer when the transistor 160 is in an on state, and the capacitance value ( C2) corresponds to the capacitance value of the so-called gate capacitance (capacitance formed between the gate electrode and the source electrode or drain electrode, and the capacitance formed between the gate electrode and the channel formation region).

If the resistance value (also called effective resistance) between the source electrode and the drain electrode when the transistor 162 is in the OFF state is ROS, under the condition that the gate leakage of the transistor 162 is sufficiently small, R1 and R2 are R1 In the case of satisfying ≥ ROS and R2 ≥ ROS, the charge retention period (which may also be referred to as information retention period) is mainly determined by the OFF current of the transistor 162 .

Conversely, if this condition is not satisfied, it becomes difficult to sufficiently ensure the retention period even if the off current of the transistor 162 is sufficiently small. This is because the leakage current (for example, the leakage current generated between the source electrode and the gate electrode, etc.) other than the off current of the transistor 162 is large. From this, it can be said that it is preferable that the semiconductor device disclosed in this embodiment satisfies the above-mentioned relationship.

On the other hand, it is preferable that C1 and C2 satisfy the relationship of C1≥C2. This is because, by increasing C1, when the potential of the floating gate portion FG is controlled by the fifth wiring (eg, at the time of reading), fluctuations in the potential of the fifth wiring can be suppressed to a low level.

By satisfying the above relationship, it is possible to realize a more suitable semiconductor device. Further, R1 and R2 are controlled by the gate insulating layer of the transistor 160 or the insulating layer of the capacitor 164 . The same is true for C1 and C2. Therefore, it is preferable to set the material, thickness, etc. of the gate insulating layer appropriately so as to satisfy the above-mentioned relationship.

In the semiconductor device shown in the present embodiment, the floating gate portion FG has the same function as the floating gate of a floating gate type transistor such as a flash memory. It has essentially different characteristics from the gate. In the flash memory, since the voltage applied to the control gate is high, it is necessary to maintain a certain distance between the cell and the cell in order to prevent the influence of the potential from being exerted on the floating gate of an adjacent cell. This is one of the factors hindering the high integration of the semiconductor device. And, this factor is due to the fundamental principle of the flash memory in which a tunneling current is generated by applying a high electric field.

In addition, due to the above principle of the flash memory, deterioration of the insulating film proceeds, and another problem arises, such as ^{a limit of the number of times of rewriting (about 10 4} to 10 ^{5 times).}

The semiconductor device according to the disclosed invention operates by switching a transistor using an oxide semiconductor, and does not use the principle of charge injection by a tunneling current as described above. That is, a high electric field for injecting electric charges like a flash memory is unnecessary. Thereby, since it is not necessary to consider the influence of the high electric field by the control gate on the adjacent cell, high integration becomes easy.

Further, since the injection of electric charge by the tunneling current is not used, there is no cause of deterioration of the memory cell. That is, the disclosed semiconductor device according to the present invention has high durability and reliability compared to a flash memory.

In addition, a high electric field is unnecessary and a large peripheral circuit (such as a step-up circuit) is unnecessary, which is an advantage over the flash memory.

Further, when the relative dielectric constant εr1 of the insulating layer constituting C1 and the dielectric constant εr2 of the insulating layer constituting C2 are different, the area S1 of C1 and the area S2 of C2 are 2· It is easy to realize C1≧C2 while satisfying S2≧S1 (preferably S2≧S1). Specifically, for example, in C1, a layered structure of a film made of a high-k material such as hafnium oxide or a film made of a high-k material such as hafnium oxide and a film made of an oxide semiconductor is adopted to obtain εr1. It is 10 or more, preferably 15 or more, and in C2, silicon oxide is employ|adopted and it can be set as (epsilon)r2=3-4. By using such a configuration together, it is possible to achieve high integration of the semiconductor device according to the disclosed invention.

In addition, although the above description is for the case of using an n-type transistor (n-channel transistor), it cannot be overemphasized that a p-type transistor can be used instead of the n-type transistor.

As described above, a semiconductor device according to an aspect of the disclosed invention includes a write transistor with a small leakage current (off current) between the source and drain in the off state, a read transistor using a semiconductor material different from the write transistor, and It has a nonvolatile memory cell containing a capacitive element.

OFF current of the write transistor is, at room temperature (e.g., 25 ℃) 100 zA (1 × 10 -19 A) or less, preferably 10 zA ^- is the (1 × 10 ²⁰ A) or less, more preferably, 1 zA (1×10 ⁻²¹ A) or less. In a normal silicon semiconductor, it is difficult to obtain a low off-state current as described above, but it can be achieved in a transistor obtained by processing an oxide semiconductor under appropriate conditions. Therefore, it is preferable to use a transistor including an oxide semiconductor as the write transistor.

In addition, since the transistor using the oxide semiconductor has a small subthreshold swing value (S value), it is possible to sufficiently increase the switching speed even if the mobility is relatively low. Therefore, by using this transistor as a write transistor, the rise of the write pulse applied to the floating gate portion FG can be made very steep. Further, since the off current is small, it is possible to reduce the amount of electric charge held in the floating gate portion FG. That is, by using a transistor using an oxide semiconductor as a writing transistor, it is possible to rewrite information at high speed.

As the read transistor, it is preferable to use a transistor that operates at a high speed in order to increase the read speed. For example, it is preferable to use a transistor having a switching speed of 1 nanosecond or less as the read transistor.

In writing information into the memory cell, by turning on the write transistor, one of the source electrode or the drain electrode of the write transistor, one electrode of the capacitor element, and the gate electrode of the read transistor are electrically connected. This is performed by supplying a potential to the gate portion FG and then turning off the write transistor to retain a predetermined amount of charge in the floating gate portion FG. Here, since the off current of the write transistor is very small, the electric charge supplied to the floating gate portion FG is retained for a long time. If the off current is, for example, substantially zero, the refresh operation required in the conventional DRAM becomes unnecessary, or it is possible to make the frequency of the refresh operation very low (for example, about once a month to once a year). Accordingly, power consumption of the semiconductor device can be sufficiently reduced.

Further, it is possible to directly rewrite the information by writing the information to the memory cell again. Accordingly, an erase operation required for a flash memory or the like is unnecessary, and a decrease in the operation speed due to the erase operation can be suppressed. That is, high-speed operation of the semiconductor device is realized. Further, since the high voltage required for writing or erasing by the conventional floating gate transistor is not required, the power consumption of the semiconductor device can be further reduced. The maximum value of the voltage (the difference between the maximum and the minimum of the potentials simultaneously applied to each terminal of the memory cell) applied to the memory cell according to the present embodiment is one when writing information in two steps (one bit). In the memory cell, it can be 5 V or less, or 3 V or less.

Since the memory cell disposed in the semiconductor device according to the disclosed invention only needs to include at least a write transistor and a read transistor, for example, compared to SRAM, which requires six transistors per memory cell, the It is possible to make the area sufficiently small. That is, memory cells can be arranged at a high density in the semiconductor device.

In addition, in the conventional floating gate transistor, since electric charges move through the gate insulating film (tunnel insulating film) during writing, deterioration of the gate insulating film (tunnel insulating film) is inevitable. However, in the memory cell according to one aspect of the present invention, since information is written by the switching operation of the write transistor, there is no problem of deterioration of the gate insulating film. This means that, in principle, there is no limit on the number of writes, and the rewrite resistance is very high. For example, in the memory cell according to one aspect of the present invention, no deterioration is seen in the current-voltage characteristic even after writing ^{1×10 9 times (one billion times) or more.}

In addition, when a transistor using an oxide semiconductor is used as a write transistor in a memory cell, the oxide semiconductor generally has a large energy gap (for example, 3.0 to 3.5 eV in the case of In-Ga-Zn-O) and thermal excitation carriers. is very small, and no deterioration is seen in the current-voltage characteristic of the memory cell even under a high-temperature environment of, for example, 150°C.

By applying the transistor having excellent characteristics as described above as a writing transistor in a memory cell, it is possible to provide a semiconductor device having a characteristic not previously available.

As mentioned above, the structure, method, etc. which are shown in this embodiment can be used combining the structure, method, etc. which are shown in another embodiment suitably.

(Embodiment 3)

In the present embodiment, an application example of a semiconductor device according to an aspect of the disclosed invention will be described with reference to FIGS. 16 to 21 .

Fig. 16 schematically shows a semiconductor device according to the present embodiment.

FIG. 16 is an example of a circuit diagram of a semiconductor device formed by using a plurality of the semiconductor device shown in FIG. 1 or FIG. 15A (hereinafter, also referred to as a memory cell 1200 ).

The semiconductor device shown in FIG. 16 includes a memory cell array in which a plurality of memory cells 1200 are arranged in a matrix, a first driving circuit 1211 , a second driving circuit 1212 , and a third driving circuit 1213 . ), the fourth driving circuit 1214 , a plurality of wirings L1 electrically connected to the first driving circuit 1211 , and a plurality of wirings L2 electrically connected to the second driving circuit 1212 ) and a plurality of wirings L3 electrically connected to the third driving circuit 1213 and a plurality of wirings L4 electrically connected to the fourth driving circuit 1214 .

As shown in FIG. 16 , a wiring L1 , a wiring L2 , a wiring L3 , and a wiring L4 are electrically connected to each memory cell 1200 . Thereby, each memory cell 1200 is operated by using the first driving circuit 1211 , the second driving circuit 1212 , the third driving circuit 1213 , and the fourth driving circuit 1214 . can be controlled. In addition, by arranging each memory cell 1200 in a matrix shape and forming each wiring L1 , L2 , L3 , and L4 in a row or column lattice shape, a write operation and a read operation of the semiconductor device are performed in the memory cell (1200) may be performed per row or per column.

In addition, in the memory cell 1200 shown in Fig. 16, one wiring is electrically connected from the first driving circuit 1211 to the fourth driving circuit 1214, respectively, but the disclosed invention is not limited to this. A plurality of wirings may be electrically connected to the memory cell 1200 from any one or a plurality of driving circuits. Moreover, it is good also as a structure in which wiring of any one or a plurality of driving circuits is not electrically connected to any one or a plurality of memory cells 1200 .

Further, in the semiconductor device shown in Fig. 16, the first driving circuit 1211, the second driving circuit 1212, the third driving circuit 1213, and the fourth driving circuit 1214 are provided independently, respectively. The invention is not limited to this. Any one or a driving circuit having a plurality of functions may be used. Further, in order to ensure a sufficient operating speed, the driving circuit is preferably formed using a single crystal type semiconductor material. For example, it is good to use bulk silicon (so-called silicon wafer).

Next, a more specific structural example will be described.

17A and 17B are examples of circuit diagrams of semiconductor devices formed by using a plurality of the semiconductor devices shown in FIG. 15A (hereinafter, also referred to as memory cells 400 ). . Fig. 17A is a circuit diagram of a so-called NAND type semiconductor device in which memory cells 400 are connected in series, and Fig. 17B is a so-called NOR type semiconductor device in which memory cells 400 are connected in parallel. It is a circuit diagram of a semiconductor device.

The semiconductor device shown in FIG. 17A has a source line SL, a bit line BL, a first signal line S1, a plurality of second signal lines S2, a plurality of word lines WL, and a plurality of It has a memory cell 400 . In Fig. 17(A) , the structure is configured to have one source line SL and one bit line BL, but the configuration is not limited thereto, and the structure includes a plurality of source lines SL and bit lines BL. can be done with

In each memory cell 400 , the gate electrode of the transistor 160 , one of the source or drain electrodes of the transistor 162 , and one electrode of the capacitor 164 are electrically connected. Further, the first signal line S1 and the other of the source electrode or the drain electrode of the transistor 162 are electrically connected, and the second signal line S2 and the gate electrode of the transistor 162 are electrically connected. Then, the word line WL and the other electrode of the capacitor 164 are electrically connected.

In addition, the source electrode of the transistor 160 included in the memory cell 400 is electrically connected to the drain electrode of the transistor 160 of the adjacent memory cell 400 , and The drain electrode is electrically connected to the source electrode of the transistor 160 of the adjacent memory cell 400 . However, among the plurality of serially connected memory cells, the drain electrode of the transistor 160 included in the memory cell 400 provided at one end is electrically connected to the bit line BL. In addition, among the plurality of memory cells connected in series, the source electrode of the transistor 160 included in the memory cell 400 provided at the other end is electrically connected to the source line SL.

In the semiconductor device shown in Fig. 17A, a write operation and a read operation are performed for each row. The write operation is performed as follows. A potential at which the transistor 162 is turned on is applied to the second signal line S2 in the row for writing, and the transistor 162 in the row for writing is turned on. As a result, the potential of the first signal line S1 is applied to the gate electrode of the transistor 160 in the designated row, and a predetermined charge is applied to the gate electrode. In this way, data can be written into the memory cells of the specified row.

Further, the read operation is performed as follows. First, a potential at which the transistor 160 is turned on regardless of the charge applied to the gate electrode of the transistor 160 is applied to the word line WL other than the row from which the read is performed, and The transistor 160 is turned on. Then, a potential at which the on or off state of the transistor 160 is selected (read potential) is applied to the word line WL of the row to be read by the charge of the gate electrode of the transistor 160 . Then, a positive potential is applied to the source line SL, and a read circuit (not shown) connected to the bit line BL is put into an operating state. Here, since the plurality of transistors 160 between the source line SL and the bit line BL are in the on state except for the row in which the read is performed, the conductance between the source line SL and the bit line BL is read. It is determined according to the state (on state or off state) of the transistor 160 of the row in which ? Since the conductance of the transistor differs depending on the electric charge of the gate electrode of the transistor 160 in the row to be read out, the potential of the bit line BL takes a different value accordingly. By reading the potential of the bit line BL by the read circuit, information can be read out from the memory cells in the specified row.

The semiconductor device shown in FIG. 17B has a plurality of source lines SL, bit lines BL, a first signal line S1, a second signal line S2, and a word line WL, respectively. has a memory cell 400 of The gate electrode of each transistor 160, one of the source electrode or the drain electrode of the transistor 162, and one electrode of the capacitor 164 are electrically connected. In addition, the source line SL and the source electrode of the transistor 160 are electrically connected, and the bit line BL and the drain electrode of the transistor 160 are electrically connected. Further, the first signal line S1 and the other of the source electrode or the drain electrode of the transistor 162 are electrically connected, and the second signal line S2 and the gate electrode of the transistor 162 are electrically connected. Then, the word line WL and the other electrode of the capacitor 164 are electrically connected.

In the semiconductor device shown in FIG. 17B, a write operation and a read operation are performed for each row. The write operation is performed in the same manner as in the semiconductor device shown in FIG. 17A described above. The read operation is performed as follows. First, a potential at which the transistor 160 is turned off is applied to a word line WL other than a row for reading, regardless of the charge applied to the gate electrode of the transistor 160, and a transistor other than the row for reading is performed. (160) is turned off. Then, a potential at which the on or off state of the transistor 160 is selected (read potential) is applied to the word line WL of the row to be read by the charge of the gate electrode of the transistor 160 . Then, a positive potential is applied to the source line SL, and a read circuit (not shown) connected to the bit line BL is put into an operating state. Here, the conductance between the source line SL and the bit line BL is determined depending on the state (on state or off state) of the transistor 160 in the row in which readout is performed. That is, the potential of the bit line BL takes on a different value depending on the charge of the gate electrode of the transistor 160 in the row to be read out. By reading the potential of the bit line BL by the read circuit, information can be read out from the memory cells in the specified row.

Incidentally, although the amount of information held in each memory cell 400 is 1 bit in the above, the configuration of the storage device shown in the present embodiment is not limited to this. By providing three or more potentials to be applied to the gate electrode of the transistor 160 , the amount of information held by each memory cell 400 may be increased. For example, when four types of potentials are applied to the gate electrode of the transistor 160, two bits of information can be held in each memory cell.

Next, an example of a read circuit that can be used for the semiconductor device and the like shown in FIG. 17 will be described with reference to FIG. 18 .

Fig. 18A schematically shows a read circuit. This read circuit has a transistor and a sense amplifier circuit.

At the time of reading, the terminal A is connected to the bit line BL to which the memory cell to be read is connected. In addition, a bias potential Vbias is applied to the gate electrode of the transistor to control the potential of the terminal A.

The memory cell 400 exhibits different resistance values according to stored data. Specifically, when the transistor 160 of the selected memory cell 400 is in an on state, it is in a low resistance state, and when the transistor 160 of the selected memory cell 400 is in an off state, it is in a high resistance state.

When the memory cell is in a high resistance state, the potential of the terminal A becomes higher than the reference potential Vref, and the sense amplifier outputs a potential corresponding to the potential of the terminal A. On the other hand, when the memory cell is in the low resistance state, the potential of the terminal A becomes lower than the reference potential Vref, and the sense amplifier circuit outputs a potential corresponding to the potential of the terminal A.

In this way, by using the read circuit, data can be read from the memory cell. In addition, the read circuit of this embodiment is an example. Other circuits may be used. Further, the read circuit may include a precharge circuit. It is good also as a structure in which the bit line BL for reference is connected instead of the reference potential Vref.

Fig. 18B shows a differential sense amplifier as an example of a sense amplifier circuit. The differential sense amplifier has an input terminal (Vin(+)), an input terminal (Vin(-)), and an output terminal (Vout), and amplifies the difference in potential between Vin(+) and Vin(-). When the potential of Vin(+) is higher than the potential of Vin(-), Vout outputs a high signal, and when the potential of Vin(+) is lower than Vin(-), Vout outputs a low signal. When this differential sense amplifier is used for a read circuit, one of Vin(+) and Vin(-) is connected to the terminal (A), and the other of Vin(+) and Vin(-) is connected to a reference potential (Vref). give

Fig. 18C shows a latch-type sense amplifier that is an example of a sense amplifier circuit. The latch type sense amplifier has input/output terminals V1 and V2 and input terminals of control signals Sp and Sn. First, the signal Sp is made high and the signal Sn is made low, and the power supply potential Vdd is cut off. Then, a potential V1in and a potential V2in for comparison are applied to V1 and V2, respectively. After that, when the signal Sp is made Low and the signal Sn is made High, and the power source potential Vdd is supplied, the potential V1in and the potential V2in to be compared are in the relationship V1in > V2in, then V1 The output of is High, the output of V2 becomes Low, and if V1in < V2in, the output of V1 becomes Low and the output of V2 becomes High. Using this relationship, the difference between V1in and V2in can be amplified. When this latch-type sense amplifier is used for a read circuit, one of V1 and V2 is connected to the terminal A and the output terminal through a switch, and a reference potential Vref is applied to the other of V1 and V2.

19 is an example of a circuit diagram of a semiconductor device formed by using a plurality of the semiconductor devices shown in FIG. 15A. The semiconductor device shown in Fig. 19 has a storage capacity of m x n bits.

The semiconductor device of FIG. 19 has m word lines WL, m second signal lines S2, n bit lines BL, n source lines SL, and n first signal lines S2. S1), a memory cell array in which a plurality of memory cells 1100 are arranged in a matrix of m vertical (row) × n horizontal (column) (m and n are natural numbers), and a first driving circuit 1111 , the second driving circuit 1112 , the third driving circuit 1113 , and the fourth driving circuit 1114 are constituted by peripheral circuits. Here, as the memory cell 1100, the configuration described in the previous embodiment (for example, the configuration shown in Fig. 15A) is applied.

That is, each memory cell 1100 includes a first transistor 160 , a second transistor 162 , and a capacitor 164 , respectively. The gate electrode of the first transistor 160, one of the source electrode or the drain electrode of the second transistor 162, and one electrode of the capacitor 164 are connected, and the source line SL and the first transistor ( The source electrode of 160 is connected, the bit line BL and the drain electrode of the first transistor 160 are connected, and the first signal line S1 and the other one of the source electrode or the drain electrode of the second transistor 162 are connected. is connected, the second signal line S2 and the gate electrode of the second transistor 162 are connected, and the word line WL and the other electrode of the capacitor 164 are connected.

Further, the memory cell 1100 is connected in parallel between the source line SL and the bit line BL. For example, the memory cell 1100 (i, j) of row i and column j (i is an integer 1 or more and m or less, j is an integer 1 or more and n or less) is a source line SL(j), a bit line ( BL(j)), a first signal line S1(j), a word line WL(i), and a second signal line S2(i), respectively.

The source line SL and the bit line BL are connected to the first driving circuit 1111 , the first signal line S1 is connected to the second driving circuit 1112 , and the second signal line S2 is It is connected to the third driving circuit 1113 , and the word line WL is connected to the fourth driving circuit 1114 . Note that here, the first driving circuit 1111, the second driving circuit 1112, the third driving circuit 1113, and the fourth driving circuit 1114 are formed independently, respectively, but the disclosed invention does not provide for this. not limited Either one or a decoder having a plurality of functions may be used.

Next, a write operation and a read operation of the semiconductor device shown in FIG. 19 will be described using the timing chart shown in FIG. 20 .

Here, for the sake of simplicity, the operation of the semiconductor device of 2 rows x 2 columns will be described, but the disclosed invention is not limited to this.

FIG. 20 is a diagram for explaining the operation of the semiconductor device shown in FIG. 19 . In Fig. 20, S1(1) and S1(2) are the potentials of the first signal line S1, respectively, S2(1) and S2(2) are the potentials of the second signal line S2, respectively, BL(1) and BL (2) is the potential of the bit line BL, WL(1) and WL(2) are the potentials of the word line WL, respectively, and SL(1) and SL(2) are the potentials of the source line SL, respectively. considerable

First, writing to the memory cells 1 and 1 and the memory cells 1 and 2 in the first row, and reading from the memory cells 1 and 1 and the memory cells 1 and 2 in the first row are performed. A case will be described. Hereinafter, a case in which data to be written into the memory cells 1 and 1 is set to "1" and data written to the memory cells 1, 2 is set to "0" will be described.

First, writing will be described. In the first row writing period, the potential VH is applied to the second signal line S2(1) in the first row, and the second transistor 162 in the first row is turned on. Further, 0 V is applied to the second signal line S2(2) in the second row, and the second transistor 162 in the second row is turned off.

Next, a potential V2 is applied to the first signal line S1(1) in the first column, and a potential 0 V is applied to the first signal line S1(2) in the second column.

As a result, a potential V2 is applied to the floating gate portion FG of the memory cells 1 and 1 and 0 V is applied to the floating gate portion FG of the memory cells 1 and 2 . Here, the potential V2 is set to be higher than the threshold voltage of the first transistor 160 . Then, the potential of the second signal line S2(1) in the first row is set to 0 V, and the second transistor 162 in the first row is turned off to complete writing.

In addition, the word lines WL(1) and WL(2) are set to 0V. Also, before changing the potential of the first signal line S1(1) in the first column, the second signal line S2(1) in the first row is set to 0 V. Threshold of the storage element after writing, in which the terminal connected to the word line WL is regarded as the control gate electrode, the source electrode of the first transistor 160 as the source electrode, and the drain electrode of the second transistor 162 as the drain electrode, respectively. The value is Vw0 for data "0" and Vw1 for data "1". Here, it is assumed that the threshold value of the memory cell refers to the voltage of the terminal connected to the word line WL, at which the resistance between the source electrode and the drain electrode of the first transistor 160 changes. Further, Vw0>0>Vw1.

Next, reading will be described. In the read period of the first row, 0 V is applied to the word line WL(1) of the first row, and the potential VL is applied to the word line WL(2) of the second row. The potential VL is set to be lower than the threshold value Vw1. When WL(1) is set to 0 V, in the first row, the first transistor 160 of the memory cells 1 and 2 holding data "0" The first transistor 160 of the cells 1 and 1 is turned on. When WL(2) is set to the potential VL, in the second row, the first transistor 160 is turned off even in a memory cell in which either data "0" or "1" is held.

Next, a potential of 0 V is applied to the first source line SL( 1 ) and the second source line SL( 2 ).

As a result, the resistance between the bit line BL(1) and the source line SL(1) is low because the first transistor of the memory cells 1 and 1 is on, and the bit line BL(2) ) - the source line SL(2), the resistance becomes high because the first transistor 160 of the memory cells 1 and 2 is in the off state. A read circuit connected to the bit line BL(1) and the bit line BL(2) can read data from the difference in resistance of the bit line.

Further, 0 V is applied to the second signal line S2(1) and a potential VL is applied to the second signal line S2(2), and the second transistor 162 is all turned off. Since the potential of the floating gate portion FG in the first row is 0 V or V2, all the second transistors 162 in the first row are turned off by setting the second signal line S2(1) to 0 V. can On the other hand, the potential of the floating gate portion FG in the second row becomes lower than the potential immediately after writing when the potential VL is applied to the word line WL(2). Accordingly, in order to prevent the second transistor 162 from turning on, the second signal line S2(2) is set to the same potential as the word line WL(2). As described above, all of the second transistors 162 can be turned off.

Next, the output potential in the case of using the circuit shown in Fig. 21 as the read circuit will be described. Since there is a low resistance between the bit line BL(1) and the source line SL(1), a low potential is input to the closed inverter, and the output D(1) goes high. Since there is a high resistance between the bit line BL(2) and the source line SL(2), a high potential is input to the closed inverter, and the output D(2) goes low.

The operating voltage may be, for example, VDD = 2 V, V2 = 1.5 V, VH = 2 V, and VL = -2 V.

As described above, by forming a plurality of memory cells as shown in the present embodiment, the storage capacity of the semiconductor device can be increased. In addition, since the number and arrangement|positioning of memory cells, the number and arrangement|positioning of wiring, the number and arrangement|positioning of a drive circuit, etc. can be designed suitably, it is not limited to the structure mentioned above.

As mentioned above, the structure, method, etc. which are shown in this embodiment can be used combining the structure, method, etc. which are shown in another embodiment suitably.

(Embodiment 4)

In the present embodiment, a configuration of a semiconductor device according to an aspect of the disclosed invention, which is different from the first and second embodiments, and a method for manufacturing the same will be described with reference to FIGS. 22 to 24 . The transistor 260 described in this embodiment is the transistor 160 in the circuit diagram in the previous embodiment, and the transistor 262 is the transistor 162 in the circuit diagram in the previous embodiment, and the capacitor element ( 264 can be used as the capacitor 164 in the circuit diagram in the previous embodiment.

<Cross-sectional configuration and planar configuration of semiconductor device>

22 is an example of the configuration of the semiconductor device. Fig. 22A shows a cross section of the semiconductor device, and Fig. 22B shows a plane of the semiconductor device, respectively. Here, Fig. 22(A) corresponds to the cross sections at C1-C2 and D1-D2 of Fig. 22(B). In the plan view of FIG. 22B , in order to avoid complication, some components such as the source electrode or drain electrode 254 and the wiring 256 are omitted. The semiconductor device shown in FIGS. 22A and 22B has a transistor 260 using a semiconductor material other than an oxide semiconductor at a lower portion and a transistor 262 using an oxide semiconductor at an upper portion. Transistors using semiconductor materials other than oxide semiconductors are easy to operate at high speed. On the other hand, a transistor using an oxide semiconductor enables long-term charge retention due to its characteristics.

Note that all of the above transistors are described as being n-channel transistors, but it goes without saying that p-channel transistors can be used. In addition, since the technical essence of the disclosed invention lies in using an oxide semiconductor for the transistor 262 to hold information, it is not necessary to limit the specific configuration of the semiconductor device to that shown here.

In the semiconductor device shown in FIG. 22 , the transistor 262 and the capacitor 264 are provided so as to overlap the transistor 260 . By employing a planar layout as shown in Fig. 22B, high integration is possible. For example, it is possible to set the minimum processing dimension to F, and to set the area occupied by the memory cell to 15F ^{2 to} 25F ^{2 .}

One of the differences between the semiconductor device shown in FIG. 22 and the semiconductor device shown in the previous embodiment is the presence or absence of a sidewall insulating layer in the transistor 260 . That is, the semiconductor device shown in FIG. 22 does not have a sidewall insulating layer. In addition, since the sidewall insulating layer is not formed, the impurity region 114 (see, for example, FIG. 2 ) is not formed. In this way, when the sidewall insulating layer is not formed, integration is easier compared to the case where the sidewall insulating layer is formed. Moreover, compared with the case where a sidewall insulating layer is formed, it is possible to simplify a manufacturing process.

Another difference between the semiconductor device shown in FIG. 22 and the semiconductor device shown in the previous embodiment is the interlayer insulating layer in the transistor 260 . That is, in the semiconductor device shown in FIG. 22 , the interlayer insulating layer 225 containing hydrogen is in contact with the metal compound region 224 of the transistor 260 . By forming the interlayer insulating layer 225 including hydrogen in contact with the metal compound region 224 , it is possible to supply hydrogen to the transistor 260 to improve the characteristics of the transistor 260 . The interlayer insulating layer 225 includes, for example, a silicon nitride layer containing hydrogen formed by plasma CVD. In addition, by applying an insulating layer having a low hydrogen concentration as the interlayer insulating layer 226 , it is possible to prevent mixing of hydrogen into the transistor 262 , which may deteriorate the characteristics of the transistor 262 . The interlayer insulating layer 226 includes, for example, a silicon nitride layer formed by sputtering in the absence of hydrogen. By adopting such a configuration, it may be possible to sufficiently increase the characteristics of the transistor 260 and the transistor 262 . 22, the substrate 200 is the substrate 100 of Embodiment 1, the element isolation insulating layer 206 is the element isolation insulating layer 106 of Embodiment 1, and the gate insulating layer 208 is the embodiment In the gate insulating layer 108 of Embodiment 1, the gate electrode 210 in the gate electrode 110 of Embodiment 1, the channel formation region 216 in the channel formation region 116 of Embodiment 1, and a high concentration impurity region Reference numeral 220 corresponds to the high concentration impurity region 120 of the first embodiment, and the metal compound region 224 corresponds to the metal compound region 124 of the first embodiment, respectively.

Another difference between the semiconductor device shown in Fig. 22 and the semiconductor device shown in the previous embodiment is that, in the transistor 262, the insulating layer 243a and the insulating layer 243b are formed between the oxide semiconductor layer 244 and the source electrode or This point is formed between the drain electrode 242a and between the oxide semiconductor layer 244 and the source electrode or drain electrode 242b. By forming the insulating layer 243a and the insulating layer 243b in this way, the gate electrode 248a, the source electrode or drain electrode 242a (or the gate electrode 248a, and the source electrode or drain electrode 242b) are formed. )) formed by reducing the so-called gate capacitance, the operating speed of the transistor 262 can be improved.

Also, as in the first embodiment, the lower transistor 260 and the upper transistor 262 are electrically connected by directly forming a source electrode or a drain electrode 242a on the gate electrode 210 . By setting it as such a structure, the integration degree improves compared with the case where an electrode and wiring are formed separately. Also, the manufacturing process is simplified.

In addition, although the structure which has the above-mentioned difference integrally is shown in this embodiment, you may employ|adopt the structure which has only any one of these differences.

<Method for manufacturing semiconductor device>

Next, an example of the manufacturing method of the said semiconductor device is demonstrated. Hereinafter, a process after forming the lower transistor 260 and a method of manufacturing the upper transistor 262 will be described with reference to FIGS. 23 and 24 . The lower transistor 260 can be fabricated in the same manner as in the first embodiment. For details, description of Embodiment 1 can be considered. In this embodiment, it is assumed that the capacitor 264 is formed. In this embodiment, it is assumed that three types of interlayer insulating layers are formed so as to cover the transistor 260 , the interlayer insulating layer 225 , the interlayer insulating layer 226 , and the interlayer insulating layer 228 . In addition, in the present embodiment, in the manufacturing process of the transistor 260, the source electrode or drain electrode 130a, the source electrode, or the drain electrode 130b in Embodiment 1 are not formed, but the source electrode or drain electrode ( 130a) and a state in which the source electrode or drain electrode 130b are not formed, for convenience, it will be referred to as a transistor 260 .

First, the lower transistor 260 is formed by the method shown in Embodiment 1, and then the upper part is removed from the upper surface of the gate electrode 210 of the transistor 260 . A polishing treatment such as CMP (chemical mechanical polishing) may be applied to this removal step. Thereby, the interlayer insulating layer 225 , the interlayer insulating layer 226 , and the interlayer insulating layer 228 above the upper surface of the gate electrode 210 are removed. In addition, by sufficiently planarizing the surface for the polishing treatment, it becomes possible to form good electrodes, wirings, insulating layers, semiconductor layers, and the like in subsequent steps.

Next, a conductive layer is formed on the gate electrode 210, the interlayer insulating layer 225, the interlayer insulating layer 226, and the interlayer insulating layer 228, and the conductive layer is selectively etched to form a source electrode or a drain electrode. 242a, a source electrode or a drain electrode 242b is formed (refer to FIG. 23A). Here, the source electrode or the drain electrode 242a is formed to be directly connected to the gate electrode 210 .

The conductive layer for forming the source electrode or drain electrode 242a, the source electrode or the drain electrode 242b is the same as the material of the source electrode or drain electrode 142a, the source electrode or the drain electrode 142b shown in Embodiment 1 It can be formed using materials. In addition, the etching of a conductive layer can also be performed using the method similar to the method shown in Embodiment 1. For details, description of Embodiment 1 can be considered.

Next, an insulating layer is formed so as to cover the source electrode or drain electrode 242a and the source electrode or drain electrode 242b, this insulating layer is selectively etched, and the insulating layer ( 243a), an insulating layer 243b is formed on the source electrode or drain electrode 242b, respectively (refer to FIG. 23B).

Between the gate electrode 248a formed later, the source electrode or drain electrode 242a, and the source electrode or drain electrode 242b by forming this insulating layer 243a and the insulating layer 243b. It is possible to reduce the parasitic capacitance of

Next, an oxide semiconductor layer 244 is formed to cover the source electrode or drain electrode 242a and the source electrode or drain electrode 242b, and a gate insulating layer 246 is formed on the oxide semiconductor layer 244 ( 23 (C)).

The oxide semiconductor layer 244 can be formed by the material and method of the oxide semiconductor layer 140 shown in the first embodiment. In addition, it is preferable to perform heat treatment (first heat treatment) on the oxide semiconductor layer 244 . For details, description of Embodiment 1 can be considered.

The gate insulating layer 246 can be formed by the material and method of the gate insulating layer 138 shown in Embodiment 1. In addition, after formation of the gate insulating layer 246, it is preferable to perform heat treatment (second heat treatment) under an inert gas atmosphere or an oxygen atmosphere. For details, description of Embodiment 1 can be considered.

Next, on the gate insulating layer 246 , a gate electrode 248a is formed in a region overlapping with a region serving as a channel formation region of the transistor 262 , and an electrode is formed in a region overlapping with the source electrode or drain electrode 242a . (248b) is formed (refer to (D) of FIG. 23).

The gate electrode 248a and the electrode 248b can be formed by forming a conductive layer on the gate insulating layer 246 and then selectively etching the conductive layer. The conductive layers used as the gate electrode 248a and the electrode 248b can be formed using a PVD method including a sputtering method or a CVD method such as a plasma CVD method. The details are the same as in the case of the source electrode or the drain electrode 242a, and the description thereof can be taken into consideration.

Next, an interlayer insulating layer 250 and an interlayer insulating layer 252 are formed over the gate insulating layer 246, the gate electrode 248a, and the electrode 248b (refer to FIG. 24A). The interlayer insulating layer 250 and the interlayer insulating layer 252 can be formed by the materials and methods of the protective insulating layer 144 and the interlayer insulating layer 146 shown in the first embodiment. For details, description of Embodiment 1 can be considered.

In addition, the interlayer insulating layer 252 is preferably formed so that the surface thereof is flat. This is because, by forming the interlayer insulating layer 252 so that the surface thereof is flat, electrodes, wirings, etc. can be suitably formed on the interlayer insulating layer 252 even when a semiconductor device is miniaturized or the like. In addition, planarization of the interlayer insulating layer 252 can be performed using a method, such as CMP (chemical mechanical polishing).

Next, the interlayer insulating layer 225 , the interlayer insulating layer 226 , the interlayer insulating layer 228 , the oxide semiconductor layer 244 , the gate insulating layer 246 , the interlayer insulating layer 250 , and the interlayer insulating layer 252 . ) is selectively etched to form an opening reaching to the metal compound region 224 of the transistor 260 (see FIG. 24(B) ). As the etching, either dry etching or wet etching may be used, but from the viewpoint of miniaturization, dry etching is preferably used.

Then, a source electrode or a drain electrode 254 is formed so as to be buried in the opening. Then, a wiring 256 connected to the source electrode or drain electrode 254 is formed (refer to FIG. 24C).

The source electrode or drain electrode 254 is formed by, for example, forming a conductive layer in a region including the opening by using a PVD method or a CVD method, and then using a method such as etching or CMP to form the conductive layer. It can be formed by removing a part of More specifically, for example, a method of forming a thin titanium film by a PVD method in a region including an opening, forming a thin titanium nitride film by a CVD method, and then forming a tungsten film so as to be buried in the opening can be applied. have. Here, the titanium film formed by the PVD method has a function of reducing the oxide film (natural oxide film, etc.) on the surface to be formed and reducing the contact resistance with the lower electrode or the like (here, the metal compound region 224 ). Further, the titanium nitride film formed thereafter has a barrier function for suppressing diffusion of the conductive material. In addition, after forming a barrier film of titanium, titanium nitride, etc., you may form a copper film by a plating method.

The wiring 256 can be formed by forming a conductive layer in contact with the source electrode or drain electrode 254 and then selectively etching the conductive layer. This conductive layer can be formed using a PVD method including a sputtering method and a CVD method such as a plasma CVD method. The details are the same as in the case of the source electrode or the drain electrode 242a.

As described above, a semiconductor device including the transistor 260 , the transistor 262 , and the capacitor 264 is completed.

In the semiconductor device shown in the present embodiment, the transistor 262 and the capacitor 264 have a configuration overlapping the transistor 260, the transistor 260 does not have a sidewall insulating layer, the gate electrode ( High integration is possible by directly forming the source electrode or the drain electrode 242a on the 210 , or the like. In addition, the manufacturing process is simplified.

In the semiconductor device shown in the present embodiment, an insulating layer containing hydrogen is applied as the interlayer insulating layer 225 and an insulating layer having a low hydrogen concentration is applied as the interlayer insulating layer 226 , so that the transistor 260 and the transistor (262) can be improved. In addition, by having the insulating layer 243a and the insulating layer 243b, the so-called gate capacitance is reduced, and the operating speed of the transistor 262 is improved.

According to the above-described characteristics shown in the present embodiment, it is possible to provide a semiconductor device having very excellent characteristics.

As mentioned above, the structure, method, etc. which are shown in this embodiment can be used combining the structure, method, etc. which are shown in another embodiment suitably.

(Embodiment 5)

In this embodiment, the example of the electronic device in which the semiconductor device obtained by the previous embodiment is mounted is demonstrated using FIG. The semiconductor device obtained in the preceding embodiment can hold information even when there is no power supply. Moreover, deterioration accompanying writing and erasing does not occur. Moreover, its operation is also high-speed. Therefore, it is possible to provide an electronic device of a new configuration using this semiconductor device. In addition, the semiconductor device according to the preceding embodiment is integrated and mounted on a circuit board or the like, and is mounted inside each electronic device.

10A is a notebook-type personal computer including the semiconductor device according to the previous embodiment, and is configured by a main body 301 , a housing 302 , a display unit 303 , a keyboard 304 , and the like.

Fig. 10B is a portable information terminal (PDA) including the semiconductor device according to the preceding embodiment, in which a main body 311 is provided with a display unit 313 , an external interface 315 , an operation button 314 , and the like. has been Also, there is a stylus 312 as an accessory for operation.

Fig. 10C shows an electronic book 320 as an example of an electronic paper including the semiconductor device according to the preceding embodiment. The electronic book 320 is composed of two housings, a housing 321 and a housing 323 . The housing 321 and the housing 323 are integrated by a shaft portion 337 , and opening/closing operation can be performed using the shaft portion 337 as an axis. With this configuration, the electronic book 320 can be used like a paper book.

A display unit 325 is assembled to the housing 321 , and a display unit 327 is assembled to the housing 323 . The display unit 325 and the display unit 327 may be configured to display continuous screens or may be configured to display different screens. By setting another screen to be displayed, for example, text is displayed on the right display unit (display unit 325 in Fig. 10(C)), and text is displayed on the left display unit (display unit 327 in Fig. 10(C)). image can be displayed.

In addition, in FIG.10(C), the example in which the housing 321 was equipped with an operation part etc. is shown. For example, the housing 321 includes a power supply 331 , operation keys 333 , a speaker 335 , and the like. By means of the operation key 333, the page can be sent. Moreover, it is good also as a structure provided with a keyboard, a pointing device, etc. on the same surface as the display part of a housing|casing. Moreover, it is good also as a structure provided with the terminal for external connection (such as an earphone terminal, a USB terminal, or a terminal connectable with various cables, such as an AC adapter and a USB cable), a recording medium insertion part, etc. on the back or side surface of the housing. In addition, the electronic book 320 is good also as a structure which gave the function as an electronic dictionary.

In addition, the electronic book 320 may be configured to be able to transmit and receive information wirelessly. It is also possible to have a configuration in which desired book data or the like is purchased and downloaded from an e-book server by radio.

In addition, electronic paper can be applied to all fields as long as it displays information. For example, in addition to electronic books, it can be applied to posters, advertisements in vehicles such as trains, and display on various cards such as credit cards.

Fig. 10D is a mobile phone including the semiconductor device according to the preceding embodiment. This mobile phone is composed of two housings, a housing 340 and a housing 341 . The housing 341 includes a display panel 342 , a speaker 343 , a microphone 344 , a pointing device 346 , a camera lens 347 , an external connection terminal 348 , and the like. Further, the housing 340 is provided with a solar cell 349 for charging the mobile phone, an external memory slot 350, and the like. In addition, the antenna is built into the housing 341 .

The display panel 342 has a touch panel function, and in FIG. 10D , a plurality of operation keys 345 displayed in images are indicated by dotted lines. In addition, this mobile phone is equipped with a boosting circuit for boosting the voltage output from the solar cell 349 to a voltage required for each circuit. Further, in addition to the above structure, a structure in which a non-contact IC chip, a small recording device, or the like is incorporated may be adopted.

In the display panel 342 , the display direction is appropriately changed according to the type of use. In addition, since the camera lens 347 is provided on the same surface as the display panel 342 , a video call is possible. The speaker 343 and the microphone 344 are not limited to voice calls, and video calls, recordings, and reproductions are possible. In addition, the housing 340 and the housing 341 can be slid from an unfolded state to a state of overlapping each other as shown in FIG.

The external connection terminal 348 can be connected to various cables such as an AC adapter and a USB cable, and charging and data communication are possible. In addition, by inserting a recording medium into the external memory slot 350, it is possible to cope with the storage and movement of a larger amount of data. Moreover, in addition to the said function, the thing provided with an infrared communication function, a television reception function, etc. may be sufficient.

Fig. 10E is a digital camera including the semiconductor device according to the previous embodiment. This digital camera is constituted by a main body 361 , a display portion (A) 367 , an eyepiece portion 363 , an operation switch 364 , a display portion (B) 365 , a battery 366 , and the like.

Fig. 10F is a television device including the semiconductor device according to the previous embodiment. In the television device 370 , a display unit 373 is assembled to a housing 371 . By means of the display unit 373, it is possible to display an image. In addition, here, the structure which supported the housing 371 by the stand 375 is shown.

The television device 370 can be operated by an operation switch provided in the housing 371 or by a remote control operator 380 separate from the housing 371 . With the operation keys 379 provided in the remote control operator 380 , channels and volume can be operated, and the image displayed on the display unit 373 can be operated. Moreover, it is good also as a structure in which the display part 377 which displays the information output from this remote control operation unit 380 on the remote control unit 380 is provided.

In addition, it is preferable that the television apparatus 370 be configured to include a receiver, a modem, or the like. The receiver can receive general television broadcasts. Further, by connecting to a communication network by wire or wireless via a modem, it is possible to perform information communication in one direction (sender to receiver) or bidirectional (between sender and receiver, or between receivers, etc.).

The structure, method, etc. shown in this embodiment can be used combining the structure, method, etc. which are shown in another embodiment suitably.

[Example 1]

In this embodiment, the result of finding the off current of a transistor using a highly purified oxide semiconductor will be described.

First, considering that the off current of a transistor using a highly purified oxide semiconductor is sufficiently small, a sufficiently large transistor with a channel width W of 1 m was prepared and the off current was measured. 25 shows a result of measuring the off current of a transistor having a channel width W of 1 m. In FIG. 25 , the horizontal axis represents the gate voltage VG, and the vertical axis represents the drain current ID. It can be seen that when the drain voltage (VD) is +1 V or +10 V and the gate voltage (VG) is in the range of -5 V to -20 V, the off-state current of the thin film transistor is 1×10 ^-13 A or less, which is the detection limit. there was. In addition, the off current of the transistor (in this case, a unit channel width (1μm) per value) is 1 aA / μm (1 × 10 - 18 A / μm) was found to be the following.

Next, the result of obtaining the off current of the thin film transistor using the highly purified oxide semiconductor more accurately is demonstrated. As described above, the off-current of using a highly purified oxide semiconductor transistor is a 1 × 10 detection limit of the instrument ^- it was found that not more than ¹³ A. Therefore, the result of producing a characteristic evaluation element and obtaining a more accurate value of the off current (a value below the detection limit of the measuring device in the above measurement) will be described.

First, an element for characteristic evaluation used in the current measurement method will be described with reference to FIG. 26 .

In the element for characteristic evaluation shown in Fig. 26, three measuring systems 800 are connected in parallel. The measurement system 800 includes a capacitor 802 , a transistor 804 , a transistor 805 , a transistor 806 , and a transistor 808 . A transistor using a highly purified oxide semiconductor is applied to the transistor 804 , the transistor 805 , and the transistor 806 .

In the measurement system 800 , one of the source and drain terminals of the transistor 804 , one of the terminals of the capacitor 802 , and one of the source and drain terminals of the transistor 805 are supplied with a power supply V2 power supply) is connected. Further, the other of the source terminal and the drain terminal of the transistor 804 , one of the source and drain terminals of the transistor 808 , the other of the terminal of the capacitor 802 , and the gate terminal of the transistor 805 . is connected Further, the other one of the source terminal and the drain terminal of the transistor 808, one of the source terminal and the drain terminal of the transistor 806, and the gate terminal of the transistor 806 are connected to a power supply (a power supply to which V1 is applied), have. Further, the other of the source terminal and the drain terminal of the transistor 805 and the other of the source terminal and the drain terminal of the transistor 806 are connected to form an output terminal.

Further, a potential Vext_b2 for controlling the on state and off state of the transistor 804 is supplied to the gate terminal of the transistor 804 , and the gate terminal of the transistor 808 is supplied with the on state and off state of the transistor 808 . A potential Vext_b1 for controlling the state is supplied. Further, a potential Vout is output from the output terminal.

Next, a current measurement method using the above-described element for characteristic evaluation will be described.

First, an outline of the initial period for applying a potential difference for measuring the off current will be described. In the initial period, a potential Vext_b1 for turning on the transistor 808 is input to the gate terminal of the transistor 808 and a node connected to the other of the source terminal or the drain terminal of the transistor 804 (that is, A potential V1 is applied to a node A, which is a node connected to one of the source terminal and the drain terminal of the transistor 808 , the other terminal of the capacitor 802 , and the gate terminal of the transistor 805 . . Here, the potential V1 is, for example, a high potential. Also, the transistor 804 is turned off.

Thereafter, a potential Vext_b1 for turning off the transistor 808 is input to the gate terminal of the transistor 808 to turn off the transistor 808 . After the transistor 808 is turned off, the potential V1 is set to a low potential. Here too, the transistor 804 is turned off. In addition, the potential V2 is set to the same potential as the potential V1. As a result, the initial period ends. When the initial period is over, a potential difference is generated between the node A and one of the source and drain terminals of the transistor 804 and the node A and the source and drain terminals of the transistor 808 . Since a potential difference is generated between the transistor 804 and the transistor 808 , a small amount of electric charge flows through the transistor 804 and the transistor 808 . That is, an off current is generated.

Next, an outline of the period for measuring the off current will be described. In the measurement period, the potential of one terminal of the source terminal or the drain terminal of the transistor 804 (ie, V2) and the potential of the other terminal of the source terminal or the drain terminal of the transistor 808 (ie, V1) are low. fasten it up On the other hand, during the measurement period, the potential of the node A is not fixed (set to a floating state). As a result, electric charge flows through the transistor 804, and the amount of electric charge held in the node A fluctuates with the passage of time. Then, the potential of the node A fluctuates according to a change in the amount of charge held in the node A. That is, the output potential Vout of the output terminal also fluctuates.

Fig. 27 shows details (timing chart) of the relationship between potentials in the initial period during which the potential difference is applied and in the subsequent measurement period.

In the initial period, first, the potential Vext_b2 is set to the potential at which the transistor 804 is turned on (high potential). Accordingly, the potential of the node A becomes V2, that is, the low potential VSS. Thereafter, the potential (Vext_b2) is set to a potential at which the transistor 804 is turned off (low potential), and the transistor 804 is turned off. Then, the potential Vext_b1 is set to a potential at which the transistor 808 is turned on (high potential). Accordingly, the potential of the node A becomes V1, that is, the high potential VDD. Thereafter, Vext_b1 is set to a potential at which the transistor 808 is turned off. Thereby, the node A enters the floating state, and the initial period ends.

In the subsequent measurement period, the potentials V1 and V2 are the potentials at which charges flow into the node A or flow out of the node A. Here, the potential V1 and the potential V2 are set to the low potential VSS. However, since it is necessary to operate the output circuit at the timing of measuring the output potential Vout, V1 may be temporarily set to the high potential VDD. In addition, the period in which V1 is set to the high potential (VDD) is set to be short enough to not affect the measurement.

When the measurement period is started by applying a potential difference as described above, the amount of charge held in the node A fluctuates with the lapse of time, and the potential of the node A fluctuates accordingly. Since this means that the potential of the gate terminal of the transistor 805 fluctuates, the potential of the output potential Vout of the output terminal also changes with the lapse of time.

A method of calculating the off current from the obtained output potential Vout will be described below.

Prior to the calculation of the off current, the _{relationship between the potential V A} of the node A and the output potential Vout is obtained. Thereby, the potential V _A of the node A can be obtained from the output potential Vout. From the above relationship, the potential V _A of the node A can be expressed as a function of the output potential Vout by the following equation.

[Equation 1]

In addition, using the charge of the _{node A} (Q A) the potential of the node A (the capacitance C _{A connected to the V A} node A) and the constant (const), it is expressed by the following equation. Here, the node The capacitance CA connected to ( _A ) is the sum of the capacitance of the capacitor 802 and the other capacitances.

[Equation 2]

Since the current I _A at node A is the time derivative of the charge flowing into the node A (or the charge flowing out of the node A), the current I _{A at the node A is} is indicated

[Equation 3]

_{In this way, the current I A} of the node A can be obtained _{from the capacitance C A} connected to the node A and the output potential Vout of the output terminal.

By the method shown above, the leakage current (off current) flowing between the source and drain of the transistor in the OFF state can be measured.

In this embodiment, the transistor 804, the transistor 805, the transistor 806, and the transistor 808 are using a highly purified oxide semiconductor having a channel length (L) = 10 µm and a channel width (W) = 50 µm. made Further, in each of the parallel measuring systems 800, the capacitance values of the capacitors 802a to 802c are 100 fF for the capacitor 802a, 1 pF for the capacitor 802b, and 3 for the capacitor 802c. It was set as pF.

In the measurement according to the present example, VDD = 5 V and VSS = 0 V. In the measurement period, in principle, the potential V1 was set as VSS, and every 10 to 300 sec, VDD was measured for a period of 100 msec. In addition, Δt used for calculation of the current I flowing through the device was set to about 30000 sec.

Fig. 28 shows the relationship between the elapsed time (Time) related to the current measurement and the output potential (Vout). 28 , it can be confirmed that the potential is changing with the passage of time.

29 shows the off current at room temperature (25°C) calculated by the current measurement. 29 shows the relationship between the source-drain voltage (V) and the off current (I). From FIG. 29, it was found that, under the condition that the source-drain voltage is 4 V, the off current is about 40 zA/μm. In addition, it was found that, under the condition that the source-drain voltage was 3.1 V, the off current was 10 zA/μm or less. In addition, 1 zA 10 ^{- 21} shows an A.

Fig. 30 shows the off current under a temperature environment of 85 DEG C calculated by the current measurement. Fig. 30 shows the relationship between the source-drain voltage (V) and the off current (I) under a temperature environment of 85°C. From FIG. 30, it was found that, under the condition that the source-drain voltage is 3.1 V, the off current is 100 zA/μm or less.

As described above, it was confirmed that the OFF current was sufficiently small in the transistor using the highly purified oxide semiconductor according to the present embodiment.

[Example 2]

The number of rewritable counts of the semiconductor device according to one aspect of the disclosed invention was investigated. In this embodiment, the results of this investigation will be described with reference to FIG. 31 .

The semiconductor device used for irradiation is a semiconductor device of the circuit structure shown in FIG. 15A. Here, an oxide semiconductor is used as a transistor corresponding to the transistor 162 , and a capacitor having a capacitance value of 0.33 pF is used as a capacitor corresponding to the capacitor 164 .

The investigation was conducted by comparing the initial memory window width with the memory window width after repeating information retention and information writing a predetermined number of times. For holding information and writing information, either 0 V or 5 V is applied to the wiring corresponding to the third wiring in Fig. 15A, and 0 V or 5 V is applied to the wiring corresponding to the fourth wiring in Fig. 15A. This was done by giving any one of V. When the potential of the wiring corresponding to the fourth wiring is 0 V, since the transistor (write transistor) corresponding to the transistor 162 is in an off state, the potential applied to the node FG is retained. When the potential of the wiring corresponding to the fourth wiring is 5 V, since the transistor corresponding to the transistor 162 is in an on state, the potential of the wiring corresponding to the third wiring is applied to the node FG.

The memory window width is one of the indicators indicating the characteristics of the memory device. Here, a curve (Vcg-Id) showing the relationship between the potential (Vcg) of the wiring corresponding to the fifth wiring and the drain current (Id) of the transistor (read transistor) corresponding to the transistor 160 between different storage states curve) of the shift amount (ΔVcg). The other storage states refer to a state in which 0 V is applied to the node FG (hereinafter referred to as a low state) and a state in which 5 V is applied to the node FG (hereinafter referred to as a high state). That is, the width of the memory window can be confirmed by sweeping the potential Vcg in the Low state and the High state.

Fig. 31 shows the results of investigation of the memory window width in the initial state and the memory window width ^{after writing 1×10 9 times.} In Fig. 31, the horizontal axis indicates Vcg(V), and the vertical axis indicates Id(A). From FIG. 31, it can be confirmed that the memory window width does not change before and after writing ^{1×10 9 times.} The fact that the memory window width does not change before and after 1×10 ⁹ writes indicates that the semiconductor device does not deteriorate at least during this period.

As described above, in the semiconductor device according to an aspect of the disclosed invention, the ^{characteristics do not change even when holding and writing are repeated 1×10 9} times or many times, and the rewrite resistance is very high. That is, it can be said that a very reliable semiconductor device can be realized by one aspect of the disclosed invention.

100: substrate 102: protective layer
104: semiconductor region 106: element isolation insulating layer
108: gate insulating layer 110: gate electrode
112: insulating layer 114: impurity region
116: channel forming region 118: sidewall insulating layer
120: high concentration impurity region 122: metal layer
124: metal compound region 126: interlayer insulating layer
128: interlayer insulating layer 130a: source electrode or drain electrode
130b: source electrode or drain electrode 130c: electrode
132: insulating layer 134: conductive layer
136a: electrode 136b: electrode
136c: electrode 136d: gate electrode
138: gate insulating layer 140: oxide semiconductor layer
142a: source electrode or drain electrode 142b: source electrode or drain electrode
144: protective insulating layer 146: interlayer insulating layer
148: conductive layer 150a: electrode
150b: electrode 150c: electrode
150d: Electrode 150e: Electrode
152: insulating layer 154a: electrode
154b: electrode 154c: electrode
154d: Electrode 160: Transistor
162: transistor 164: capacitive element
200: substrate 206: element isolation insulating layer
208: gate insulating layer 210: gate electrode
216: channel formation region 220: high concentration impurity region
224: metal compound region 225: interlayer insulating layer
226: interlayer insulating layer 228: interlayer insulating layer
242a: source electrode or drain electrode 242b: source electrode or drain electrode
243a: insulating layer 243b: insulating layer
244: oxide semiconductor layer 246: gate insulating layer
248a: gate electrode 248b: electrode
250: interlayer insulating layer 252: interlayer insulating layer
254: source electrode or drain electrode 256: wiring
260: transistor 262: transistor
264: capacitive element 301: body
302: Housing 303: Display
304: keyboard 311: body
312: Stylus 313: Display
314: Operation button 315: External interface
320: e-book 321: housing
323: Housing 325: Display
327: Display 331: Power
333: operation key 335: speaker
337: shaft 340: housing
341: Housing 342: Display panel
343: Speaker 344: Microphone
345: operation key 346: pointing device
347: Camera lens 348: External connection terminal
349: solar cell 350: external memory slot
361: body 363: eyepiece
364: Operation switch 365: Display section (B)
366: Battery 367: Display (A)
370: television device 371: housing
373: Display 375: Stand
377: Display 379: Operation keys
380: remote control operator 400: memory cell
800: Measuring system 802: Capacitive element
802a: capacitive element 802b: capacitive element
802c: Capacitive element 804: Transistor
805: transistor 806: transistor
808: transistor 1100: memory cell
1111: first driving circuit 1112: second driving circuit
1113: third driving circuit 1114: fourth driving circuit
1200: memory cell 1211: first driving circuit
1212: second driving circuit 1213: third driving circuit
1214: fourth driving circuit

Claims (4)

A semiconductor device comprising:
Having a plurality of circuits arranged in a matrix shape,
each of the plurality of circuits has a first transistor, a second transistor, and a capacitor;
the first transistor has a first channel formation region;
the second transistor has a second channel forming region;
The first channel forming region has silicon,
The second channel formation region has an oxide semiconductor layer,
The upper surface of the source electrode and the upper surface of the drain electrode are in contact with the oxide semiconductor layer, respectively,
and the gate electrode of the second transistor is positioned on the oxide semiconductor layer with the gate insulating layer of the second transistor interposed therebetween. A semiconductor device comprising:
Having a plurality of circuits arranged in a matrix shape,
each of the plurality of circuits has a first transistor, a second transistor, and a capacitor;
the first transistor has a first channel formation region;
the second transistor has a second channel forming region;
The first channel forming region has silicon,
The second channel formation region has an oxide semiconductor layer,
The top and side surfaces of the source electrode and the top and side surfaces of the drain electrode are in contact with the oxide semiconductor layer, respectively,
and the gate electrode of the second transistor is positioned to overlap the oxide semiconductor layer with the gate insulating layer of the second transistor interposed therebetween. 3. The method according to claim 1 or 2,
and the first channel forming region is formed in a semiconductor layer. 3. The method according to claim 1 or 2,
and the first channel forming region is formed in a single crystal silicon substrate.

Images