JPH05282881A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To read accurate memory content by absorbing a potential variation due to disturbance by sufficient writing amount or erasing amount. CONSTITUTION:A variable potential setter VE1 is connected as pulling-up means of a point B. The setter VE1 has transistors Tr6D, Tr11, and the relationship of driving capacities of the Tr6D, the Tr11 is set so as to satisfy Pb1<Pb2. Pull-up driving capacity of a dummy side is formed so as to be varied in two ways. One is the same driving capacity Pb1 as prior art, and the other is slightly stronger driving capacity Pb2 than that of the prior art. A normal mode, a write/verify mode can be switched by using the Tr6D, the Tr11 and a control signal CE.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a read system of a non-volatile memory, and more particularly to an EPR.
It is used for OM (Electrical Programmable Read Only Memory) and the like.

[0002]

2. Description of the Related Art In recent years, EPROM and E have been used as a peripheral storage device of a microcomputer and also as a built-in storage device.
EPROM (Electricaly Erasable and Programmable R
Ead Only Memory) is being actively developed. Behind this are improvements in development efficiency due to the ease of program control and data retention at power off.
Further development is expected. Programming to non-volatile memories such as EPROM is mainly done by PRO.
On-board by M writer and CPU control (On
(Board) method is used to write data by injecting electrons into the floating gate, and the written data is surely written or the cell just written is read through the read circuit immediately after writing. This is confirmed (this reading is called verify).

Since the operation principle of the EPROM is well known, a detailed description thereof will be omitted. However, the timing chart at the time of writing and the operation of the read circuit will be described to some extent.

FIG. 5 shows a typical timing chart. The write / verify mode is set by setting the high potential terminal VPP to the high potential level. Further, an address is given to select a cell, and write data is supplied.
At this time, the data terminal is normally an I / O (bidirectional terminal), and the signal OE is set to "H" (logic "1") to I / O.
Input O as input. After data is determined, PGM is written as "L" (logic "0"), and after completion, O
When E is set to "L", the data I / O terminal becomes an output, the data is output, and if the data matches the written data, the writing is completed.

A sense amplifier is usually used for the read circuit. This is because high speed is required, and a sense circuit for minute signals is required even at low speed.

FIG. 6 shows a typical circuit example of a differential type sense amplifier.

In the figure, Tr61 is a floating gate holding transistor which constitutes a body cell, Tr62 is a floating gate holding transistor which constitutes a dummy cell, and SA is a differential type which operates according to the state of the body cell with reference to the state of the dummy cell. It is a sense amplifier. The sense amplifier SA includes transistors Tr63 to Tr67, the transistors Tr63 and Tr64 form an input differential pair, the transistors Tr65 and Tr66 form an active load, and the transistor Tr67 forms a constant current source circuit.

The body cell transistor Tr61 is connected to the gate of the transistor Tr64 through the source and drain of the decoder transistor Tr68 and the column selection transistor Tr69 in series. Dummy cell transistor T
The r62 is connected to the gate of the transistor Tr63 through the source and drain of a transistor Tr6A corresponding to the decoder transistor Tr68 and a transistor Tr6B corresponding to the column selection transistor Tr69 in series.

A pull-up transistor Tr6C is connected to the connection point of the drain of the transistor Tr69 and the gate of the transistor Tr64, and a pull-up transistor Tr6D is connected to the connection point of the gate of the transistor Tr63 and the drain of the transistor Tr6B. It is connected.

Here, the dummy cell transistor Tr62
Is the same cell as the main body cell transistor Tr61, but writing is not performed. Therefore, it is always on.

The transistor Tr6A connected to the drain of the dummy cell transistor Tr62 is for making the circuit on the dummy cell side the same state as when the transistor Tr68 is selected.

The pull-up transistors Tr6C (driving capability Pa) and Tr6D (driving capability Pb) are set so that the pull-up driving capabilities Pa and Pb are different between the main body side and the dummy side so that the dummy side is slightly stronger. To do. The potential Vb at the point B at this time becomes the reference potential at the time of reading.

First, the body cell transistor T
When the data of logic "1" is not written in r61, the main cell transistor Tr61 and dummy cell
Both of the transistors Tr62 are turned on, but the potential Va, from the relationship (Pa <Pb) between the driving capabilities Pa and Pb.
The relationship of Vb is Va <Vb, and the output Q is "L".

On the other hand, when the data of logic "1" is written in the body cell transistor Tr61, the output potential Va thereof is pulled up by the transistor Tr6C while the body cell transistor Tr61 is off. Potential V
a2, the reference potential Vb2 on the dummy side is a current drawn because the dummy cell transistor Tr62 is in the ON state,
Va> Vb, and the output Q becomes "H".

Here, when the data of logic "1" is written in the non-volatile memory, the data is written while performing the verify operation. If Vbw is not written, V
If aw> Vbw, it is written. However, even if it is judged that the data has been written, even if Vaw> Vbw, the write amount is insufficient and if Vaw >> Vbw is not satisfied, Vaw <Vbw will be caused by some disturbance when the data is read next time, and the data at the time of writing will be It will be different. Similarly, in the case of erasing, when read immediately after erasing, Vaw <Vbw due to some disturbance, and the data is different from that at the time of writing. Similarly, in the case of erasing, the potential relationship between points A and B is Vae from the above when read immediately after erasing.
Even if <Vbe, the erase amount is insufficient and if Vae << Vbe is not satisfied, Vae> Vbe will occur due to some disturbance when the next reading is performed.
It is determined that it has not been erased.

[0016]

As described above, the conventional EP is used.
In the ROM, accuracy may be impaired in the read operation of the stored contents due to the influence of disturbance.

The present invention has been made in view of the above problems, and provides a semiconductor memory device which constitutes an EPROM capable of accurately reading the stored contents even when a disturbance occurs during the reading operation. To do.

[0018]

A semiconductor memory device according to the present invention comprises a sense amplifier for detecting the stored contents of a body cell as a potential difference between the body cell side input section and the dummy cell side input section, and the body cell side input section. And the dummy cell side input section, and the potential difference setting drive capability between the main body cell side input section and the dummy cell side input section depending on at least one mode of writing / erasing to the main body cell and a read mode from this main body cell. And a variable potential difference setting circuit that is variable.

The variable potential difference setting circuit is connected to one of the main body cell side input section and the dummy cell side input section, and is connected to the other of the main body cell side input section and the dummy cell side input section. It may be configured by a variable potential setting circuit.

The variable potential difference setting circuit is composed of a first variable potential setting circuit connected to the main body cell side input section and a second variable potential setting circuit connected to the dummy cell side input section. It can be configured.

The variable potential setting circuit functions so that the difference in the potential setting drive capability of the main cell side input part with respect to the potential setting drive capability of the dummy cell side input part is larger in the write mode than in the read mode. Can be configured to.

In the variable potential setting circuit, the difference between the potential setting drive capability of the main cell side input part and the potential setting drive capability of the dummy cell side input part is smaller in the erase mode than in the read mode. Can be configured to work.

[0023]

According to the present invention, the potential difference setting drive capability between the body cell side input section and the dummy cell side input section can be varied depending on at least one of the writing / erasing mode to the body cell and the reading mode from the body cell. Therefore, it is necessary to realize a sufficient write amount or erase amount by changing the relative potential setting drive capability difference between the main cell side of the sense amplifier and the dummy cell side input section in the read mode and the write / erase mode. This makes it possible to absorb potential fluctuations due to disturbances and read the stored contents accurately.

[0024]

Embodiments of the present invention will be described below with reference to the drawings. The circuit of each embodiment of the present invention is shown in FIG.
Since it has the same constituent elements as those shown in FIG. 6, the same constituent elements are designated by the same reference numerals as those in FIG. 6, and the description thereof will be omitted, and only different portions will be described.

FIG. 1 shows a circuit configuration of a semiconductor memory device according to the first embodiment of the present invention.

In FIG. 1, here, a variable potential setting circuit VE1 constituting a characteristic part of the present invention is connected as a pull-up means at a point B. This variable potential setting circuit V
E1 is a transistor Tr6D (driving capability Pb shown in FIG.
1) and a transistor Tr11 (driving ability Pb2) having different driving ability. Both transistors Tr6
The relationship between the driving abilities of D and Tr11 is set so that Pb2 is slightly stronger than Pb1, that is, Pb1 <Pb2. Thereby, the pull-up drive capability on the dummy side can be changed in two ways.

Of these two driving abilities, one is the same driving ability Pb1 as in the conventional example, and the other is the driving ability Pb2 which is slightly stronger than the driving ability in the conventional example. The pull-up transistors Tr6D and Tr11 on the dummy side and the pull-up transistor Tr6C on the body cell side are set to be switched between the normal mode and the write / verify mode by using the control signal CE described in the timing chart of FIG.

First, in the normal mode, Tr6D is in the ON state,
The transistor Tr11 is turned off and the same operation as that shown in FIG. 6 is performed. On the other hand, in the write / verify mode, the transistor Tr6D is in the off state and the transistor T6D is in the off state.
r11 turns on.

Writing to EPROM using this circuit
When verification is performed, potentials Va and Vb at points A and B
Since the potential relationship is Va> Vb, the output Q point becomes "H" and the writing is completed.

After that, when reading in the normal mode, the reference potential is set to the transistor Tr6C by the control signal CE.
The potentials Va and Vbpb1 have a relation Va> Vbpb1. However, since the transistor Tr11 having the driving capability relation Pa <Pb1 <Pb2 is used for writing, the potential is higher than the potential Va> Vbpb1. The relationship between Va and Vb is V
a>Vbpb2> Vbpb1 and V in the case of the conventional example
The potential at the point A is higher than that at the point B by at least Vbpb2-Vbpb1 than a> Vb, and sufficient writing is performed. Therefore, even if a disturbance occurs during reading, the stored contents can be accurately read without being affected by the disturbance due to the high write potential.

Further, only the merit can be expected without increasing the pattern area due to the addition of the pull-up transistor.

FIG. 2 shows the circuit configuration of a semiconductor memory device according to the second embodiment of the present invention.

In this figure, VE2 is the variable potential setting circuit of this embodiment, and this circuit VE2 has the transistor Tr6D (driving capability Pb1) shown in FIG. 6 and the transistor Tr21 (driving capability) different from that of the transistor Tr6D. It is composed of the ability Pb3). Drive capacity Pb1, Pb3
The relationship is Pb3 <Pb1.

In the EEPROM, the transistor Tr6 has a potential relationship between points A and B such that Va <Vbpb3 in the erase / verify mode and Va <Vbpb1 in the normal mode.
ON / OFF control of D and Tr21.

As a result, when erasing, the erasing is performed using Pb3 having a drive capability relationship of Pa <Pb3 <Pb1.
The potential relationship between Va and Vbpb1 is Va <Vbpb3 <Vbpb1, and the potential at the point A is lower than that at the point B by at least Vbpb1-Vbpb3 compared with Va <Vbpb1 in the case of the conventional example, and sufficient erasing is performed.

FIG. 3 shows the circuit configuration of a semiconductor memory device according to the third embodiment of the present invention.

In the figure, VE3 is a variable potential setting circuit of this embodiment, and this circuit VE3 corresponds to a combination of the circuits VE1 and VE2 of the first and second embodiments.
It has transistors Tr6D, Tr11, Tr21.

Therefore, these transistors Tr6D and Tr1
The relationship between the driving capacities of 1 and Tr21 is Pa <Pb3 <Pb1 <P
Since it becomes b2, both writing and erasing will be sufficiently performed.

FIG. 4 shows a circuit configuration of a semiconductor memory device according to the fourth embodiment of the present invention.

The feature of the present embodiment is that the driving ability is variable on both the dummy side and the body cell side. VE41 is a variable potential setting circuit provided on the body side, and VE42 is provided on the dummy side. It is a variable potential setting circuit.

These variable potential setting circuits VE41, VE42
Operates so that the potential setting drive capability difference of the main body cell side input part with respect to the potential setting drive capability of the dummy cell side input part becomes larger in the read mode than in the read mode. It is configured so that the difference in the potential setting drive capability of the main body cell side input unit with respect to the potential setting drive capability of the dummy cell side input unit becomes smaller in the erase mode than in the erase mode.

Therefore, considering the read mode as a reference, in the write mode, the variable potential setting circuit VE41 is used.
Reduces the pull-up drive capacity, and the variable potential setting circuit VE
42 increases pull-up drive capability.

Similarly, considering the read mode as a reference, in the erase mode, the variable potential setting circuit VE is used.
41 is a variable potential setting circuit V with increased pull-up drive capability
E42 operates to reduce pull-up drive capability.

Although each of the above embodiments shows an example of a differential type sense amplifier, the present invention can be applied to other sense amplifiers.

[0045]

As described above, according to the present invention, between the main cell side input section and the dummy cell side input section depending on at least one of the writing / erasing mode to the main body cell and the read mode from the main body cell. Since the potential difference setting drive capacity of is changed, a sufficient write capacity can be achieved by changing the relative potential setting drive capacity difference between the main cell side of the sense amplifier and the dummy cell side input section in the read mode and the write / erase mode. Or, it is possible to realize the erase amount, thereby absorbing the potential fluctuation due to the disturbance and reading the stored contents accurately.

Nonvolatile memories such as EPROMs are expected to become more and more developed due to market needs such as ease of program development and data retention when power is cut off. In the conventional example, sufficient writing to EPROM cells is possible. Malfunction due to not being performed, and data change due to secular change occur. However, by using the present invention, by adding only pull-up transistors having different drive capabilities to the conventional example, these added pull-up transistors are selectively used in the write mode, the normal mode, and the erase mode. In comparison, sufficient writing and erasing are possible, and malfunction due to insufficient writing,
Data changes due to aging can be prevented.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an EPROM according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of an EPROM according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram of an EPROM according to a third embodiment of the present invention.

FIG. 4 is a circuit diagram of an EPROM according to a fourth embodiment of the present invention.

FIG. 5 is a time chart illustrating the basic operation of EPROM.

FIG. 6 is a circuit diagram of a conventional EPROM.

[Explanation of symbols]

SA sense amplifier A body cell side input section B dummy cell side input section Q read output VE1 to VE42 variable potential setting circuit Tr6C body cell side pull-up transistor Tr6D, Tr11, Tr21 dummy cell side pull-up
Transistor Pa Main cell side pull-up transistor Tr6C drive capacity Pb1 Dummy cell side pull-up transistor Tr6D
Drive capacity Pb2 Dummy cell side pull-up transistor Tr11
Drive capacity Pb3 Dummy cell side pull-up transistor Tr21
Drive capacity of

Claims (5)

[Claims] 1. A sense amplifier for detecting the stored content of a main body cell as a potential difference between the main body cell side input section and the dummy cell side input section, and the main body cell provided on the main body cell side input section and the dummy cell side input section. And a variable potential difference setting circuit in which the potential difference setting drive capability between the main body cell side input section and the dummy cell side input section is variable in at least one mode of writing / erasing to / from the main body cell and a read mode from the main body cell. Semiconductor memory device. 2. A variable potential difference setting circuit is connected to one of a body cell side input section and a dummy cell side input section, and a fixed potential setting circuit connected to the other of the body cell side input section and a dummy cell side input section. 2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is formed of a variable potential setting circuit. 3. The variable potential difference setting circuit is formed of a first variable potential setting circuit connected to the main body cell side input section and a second variable potential setting circuit connected to the dummy cell side input section. The semiconductor memory device according to claim 1, wherein 4. The variable potential setting circuit is configured such that the difference in potential setting drive capability of the main cell side input unit with respect to the potential setting drive capability of the dummy cell side input unit is greater in the write mode than in the read mode. 4. The semiconductor memory device according to claim 2, wherein the semiconductor memory device functions as described above. 5. The variable potential setting circuit is configured such that the difference in potential setting drive capability of the main cell side input unit with respect to the potential setting drive capability of the dummy cell side input unit is smaller in the erase mode than in the read mode. 4. The semiconductor memory device according to claim 2, wherein the semiconductor memory device operates in accordance with any one of claims 2 and 3.