JP3410976B2 - Combined logic and memory integrated circuit chip combining thin film and bulk silicon transistors and method of forming the same - Google Patents

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates generally to the design and formation of logic circuits and memory arrays that are merged on a single semiconductor integrated circuit (IC) chip, and more particularly, where the logic circuits have two semiconductor levels or thin films. Level and bulk silicon (Si) level, the memory array uses static random access memory (SRA)
M), including "system-on-chip" circuits and methods of forming the same.

[0002]

BACKGROUND OF THE INVENTION Increasing density of logic circuits and memory arrays results in faster circuit performance and smaller integrated circuits (ICs), and thus lower cost per IC. Currently, logic and memory functions are formed on separate ICs, and overall system speed is limited by the communication bandwidth between logic circuits and memory. The performance limit of about 500 MHz is due to communication bandwidth, which is a direct result of logical and memory functions communicating over relatively long distances (several millimeters).

Currently, 16 megabits (Mb), 64
Mb and above static random access memory (SRAM) array densities include four n-type metal oxide semiconductor (NMOS) transistors placed in the Si wafer level and two p-type metal oxides. It is increased by placing oxide semiconductor (PMOS) load transistors in a thin film (TF) polycrystalline Si (p-Si) layer on the Si wafer level. About this, for example A.
"Semiconductor Memories" by K. Sharma, IEEE Pre
ss, New York (1997) and Y. Takao, H. Shimada, N.S.
IEEE Transac by uzuki, Y. Matsukawa and N. Sasaki
See tions on Electron Devices 39 (1992), p. 2147. SRAM cells require a smaller Si wafer area. This is a 3D (3D) approach to achieve higher density and therefore larger scaled SRAM arrays.
D) An example of integration. In particular, as described by AK Sharma, other advantages of the 3D SRAM example include improved noise immunity and low standby current.

One approach beyond the 500 MHz performance limit is to combine logic and memory arrays into a single IC.
It is to integrate on top. These ICs are "merged logic and memory" configurations or "system-on-chip".
Known as composition. System-on-chip configurations can improve performance. Currently, two separate process techniques are used to form separate logic and memory chips.

Solutions for both density scaling and performance improvement, as well as single process techniques for forming logic and memory circuits are desired.

[0006]

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a compact and economical method for designing and manufacturing "system on chip" ICs.

Another object of the present invention is to provide a single process technology and 3D integration method for both logic and memory circuits.

[0008]

According to the present invention, a memory
.Theory of being incorporated in a single IC chip together with an array
Management circuit, from the transistor and a common two semiconductor layers level memory array, i.e. a thin film (TF) level and wafer level, the transistors of the semiconductor layer of
It is configured, merging of logic and memory IC is provided.
The logic circuit is a three-dimensional form of differential cascode voltage switch (DCVS) logic, in which an NMOS transistor is used.
Is formed in the semiconductor substrate at the wafer level, and P
MOS transistor is the NMOS transistor and the O
Wherein in-overlap position is formed in the semiconductor layer of the thin burr bell. Examples of this logic circuit include LG Heller, W.
Diges by R. Griffin, JW Davis and n. G. Thoma
t Tech. Papers, ISSCC 1984, pp. 16-17 and Fang-shi
IEEE Journal of Solid-Stat by Lai and Wei Hwang
e Circuits, 32 (1997), p. 563 logic circuit according to the擧
Gerare Ru. The memory array, one cell 6
Of static random access memory consisting of a transistor (SRAM) and the like, where the SRA
Disposed four NMOS driver transistor Gow Fine level in the semiconductor substrate of the M cell, the NMOS bets two PMOS load transistors in the semiconductor layer of the thin-film level
It is placed in an overlapping relationship with the transistor.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION In the present specification, for example, "A bar"
The inverted form of the signal name or node name is indicated by adding a “bar” to the signal name or the node name.

Referring to FIGS. 1 and 2, a conventional planar static random access memory (SR) is used.
AM) array example is shown. FIG. 1 is a structural circuit diagram showing a standard six-transistor CMOS SRAM cell. NMOS transistors Q1 and Q2 are "accessed"
Devices, NMOS transistors Q3 and Q4 are "driver" transistors, and two PMOS transistors Q5 and Q6 are "load" transistors.

A layout diagram of a standard SRAM cell is shown in FIG.
Shown in. The NMOS transistors of Q1 and Q2 are
It is formed by the overlap of the active n-silicon layer 1 and the polysilicon layers 3 and 4. The source contacts 10 of Q1 and Q2 are contacted to V _ss or ground by the metal layer 6. Similarly, Q3 and Q4 are formed by the overlap of the active silicon layer 1 and the polysilicon layer 5 forming the word lines (WL). The drain contacts 20 of Q3 and Q4 are bit line Bit bar (where "bar" represents the inverted signal) and Bi, respectively.
connected to t. PMOS Q5 transistor and Q6
The transistor is connected to metal layer 7 or V _DD .
The drain contacts 40 and 42 of Q5 and Q6 are
It is connected to the node indicated by the black circle in FIG.

A conventional SRAM cell formed in three dimensions (3D) using thin film Si PMOS load transistors is shown in FIGS. The circuit of FIG. 3 is substantially the circuit of FIG.
The circuit is the same.

FIG. 4 shows the structure of a conventional 3D SRAM cell,
And the fabrication method used to increase the density of the memory array. The 3D SRAM cell has PMOS transistors Q5 and Q6 as thin film transistors (TFT).
Layers, preferably in poly-Si (p-Si) formed by excimer laser annealing. The transistors Q1 to Q4 are formed in a crystalline Si wafer substrate. More specifically, as shown in FIG. 4, Q1 N
The MOS transistor and the Q2 NMOS transistor are formed by the overlap between the active n-silicon layers 21 and 23 and the first polysilicon layers 16 and 15, respectively. Similarly, Q3 and Q4 are formed by the overlap of the active silicon layers 11 and 12 with the first polysilicon layer 17 forming the word line (WL).
The drain contacts 18 of Q3 and Q4 are bit lines (B) formed in an aluminum (Al) metal layer.
L bar and BL). The second polysilicon layer 28 forms the gates of the PMOS TFTs Q5 and Q6 (lower gate TFT structure). Third polysilicon layers 13 and 14 form the active layers of TFTs Q5 and Q6 and also form the V _DD line. The overlap between the second polysilicon layer 28 and the third polysilicon layers 13 and 14 forms TFTs Q5 and Q6, respectively.

Differential Cascode Voltage Switch (DCVS)
Logic is a dual rail CMOS circuit technology, which has potential advantages over traditional single rail NAND / NOR random logic in terms of layout area, circuit delay, power consumption and logic flexibility. The DCVS consists of a stack of NMOS differential pairs, which are connected to a pair of cross-connected PMOS loads for pull-up. Direct current (dc) does not flow in the static mode.
Thus, complex Boolean logic functions, which may require several gates in conventional CMOS logic, can be implemented in a single stage gate in DCVS.

The conventional simple differential cascode voltage switch (DCVS) logic relevant to the present invention is shown in FIGS. A configuration circuit diagram of a conventional DCVS AND / NAND gate is shown in FIG. 5, and a layout diagram thereof is shown in FIG. In this case, all six transistors are formed in a single level Si wafer substrate. There are four drive transistors and Q1 through Q4 are NMOS devices, which form an n-channel logic evaluation (true and inversion) tree. The circuit load is constituted by two cross-connected PMOS load transistors Q5 and Q6, which are important to the invention. This is because these devices occupy a large area of the Si wafer structure, thus preventing conventional DCVS logic from achieving very high areal densities.

In FIG. 5, the left leg of the NMOS logic tree is the series NMOS transistors Q2 and Q1.
And is connected to the ground to form one pull-down network. Q2 and Q1 operate as switches controlled by their gate signals A and B, respectively. The right leg of the NMOS logic tree is a parallel NM
It is composed of OS transistors Q3 and Q4. Both transistors are connected to ground to form another pulldown network. Q3 and Q4 are controlled by their gate signals, inverting inputs A and B, respectively. The pull-up network is composed of two cross-connected PMOS transistors Q5 and Q6. When the input signals A and B transition from low to high, the transistors Q1 and Q2 turn on. At this time, the node Y bar is discharged to the ground. The node Y is in a floating state during the transition period in which the inverted input signals A bar and B bar transit from high to low.

Both NMOS transistors Q3 and Q4 are off. The ground level on node Y-bar turns on the cross-connected PMOS load transistor Q6. The output node Y is charged high. This implements the dual AND / NAND logic function.

A layout diagram of a simple DCVS AND / NAND gate is shown in FIG. The NMOS transistors Q1 and Q2 are formed by overlapping the active n silicon layer 31 and the polysilicon layers 36 and 37. Thereby the source and drain diffusions are self-aligned with the gates A and B. The source contact 41 of Q1 is connected to V _ss or ground by the metal layer 40. The drain contact 43 of Q2 is connected to node 1 or Y bar. Similarly, the NMOS transistors Q3 and Q4 are formed by overlapping the active n silicon layer 31 and the polysilicon layers 38 and 39. Thereby the source and drain diffusions are self-aligned with the gates A and B. The source contacts 45, 47 of Q3 and Q4 are connected to V _ss or ground by the metal layer 40. Common drain of Q3 and Q4
Contact 49 is connected to node 2 or Y. PM
The OS transistors Q5 and Q6 are formed in the p + region implanted in the n-well region 33. The n-well is typically a deeper implant compared to the source / drain implant of the transistor. Therefore, it is necessary for the outer dimensions to provide sufficient space between the edge of the n-well and the adjacent n + diffusion. Again, PMOS transistors Q5 and Q6 are formed by the overlap of active p-silicon layer 32 and polysilicon layers 34,35. The source contacts 51, 53 of Q5 and Q6 are connected to the metal layer 50 or V _DD . The drain contacts 55, 57 of Q5 and Q6 are connected to nodes 1 and 2 or Y-bar and Y, respectively.

A cross-sectional view of the structure of the present invention is shown in FIG.
More specifically, FIG. 7 shows a cross-sectional schematic view of the most general form of the invention, namely, a three-dimensional (3D) CMOS transistor pair used to form both logic and SRAM memory devices. For convenience, only transistor levels are shown (wiring levels not shown). In this simplified sectional view, one NMOS transistor 4
00 is formed in a crystalline bulk Si wafer substrate 401. The PMOS load transistor 411 is formed in the Si layer on the NMOS device. Si layer 406 is PMOS
Used as a TFT, preferably an excimer laser
Polycrystalline Si (p-S) formed by the annealing method
i). Alternatively, this is a rapid thermal annealing (RT
It is p-Si formed by the A) method. In essence, the bottom of the structure includes a thick insulator 402, a via hole 403 and a conductor 404 filling the via hole.

The thick insulator 402 is formed by chemical mechanical polishing (C
MP) method to planarize, leaving a planar surface 405 for subsequent formation of PMOS transistor 411. On top of the structure is a thin Si layer 406, a gate dielectric layer 407,
A gate conductor 408 and source and drain contacts 409 are included. Source metal level and drain metal level 409 are thick insulators (passivation)
Insulated by layer 410. The formation of the thin film Si upper level of this structure will be described later with reference to FIGS.

The general case and preferred embodiments of the present invention will be described with reference to FIGS. This is an embodiment of the present invention, an AN in a DCVS logic circuit.
3 shows a detailed structure of a 3D circuit configuration of a D differential logic gate and a NAND differential logic gate. The DCVS circuit concept is shown in FIG. 8 in differential form, which includes an AND gate and a NAN in a DCVS logic circuit (three-dimensional configuration or 3D DCVS).
Both circuit configuration diagrams of the D gate are shown. Again, for convenience, only transistor levels and selected wire levels up to M4 are shown (full wire levels not shown). Active transistors Q1-Q4 are formed in a crystalline Si wafer substrate. Two cross-connected PMOS load transistors Q5 and Q6 are preferably formed of polycrystalline Si (p-S) by excimer laser annealing.
i) is used to form in the TFT layer. Depending on the differential input, one output (F or F bar) is pulled down by the NMOS combinatorial logic evaluation tree network. Positive feedback action causes the PMOS latch to have a static output F
And F-bar, or fully differential V _DD and ground logic levels.

The basic circuit operation of 3D DCVS is the same as 2D DCVS described above in connection with FIG. 3D
, The cross-connect PMO with two pull-up load networks
Including STFT. This offers a great advantage in terms of design flexibility of the load element. The pull-up performance of complex logic gates, ie the fast rise time, can be dramatically improved. Traditionally, dual rail logic was used exclusively in high performance digital systems. 2D or 3D
The design procedure for constructing a more complex NMOS logic tree compatible with DCVS is the Karnaugh map (K map).
Can be synthesized by

A detailed sectional view showing the structure of this circuit is shown in FIG. The p− epitaxial layer 501 is the p + substrate 50.
0 attached. P by standard NMOS process
Active transistors Q1 to Q4 are formed on the + substrate 500. Active area 5 for transistors Q1 to Q4
03 is defined by ion implantation of N additive.
A shallow trench isolation (STI) 502 then isolates adjacent devices Q2 and Q3. The deposited polysilicon layer is patterned to form the self-aligned Si gates of transistors Q1-Q4, 524, 525, 526 and 527, respectively. The N-doped source region and drain region 503 are formed by ion implantation. A source contact 505 is formed and connected to the first metal layer (M1). The source junction contacts of transistors Q1, Q3 and Q4 are connected to M1, or ground. The transistor gates of Q1, Q2, Q3 and Q4 are connected to the input signals B, A and A bar, B bar, respectively. Thick insulator 506 is deposited by chemical vapor deposition (CVD). As described above, the thick insulator 506 is planarized by the chemical mechanical polishing (CMP) method to form the flat surface 5
18 is left for the subsequent formation of the PMOS load transistor.

Next, the bulk NMOS transistor and PM
Via holes, important for connection to OS thin film transistors (TFTs), are patterned and etched. These via holes are made up of conductors 530 and 532.
Is filled with. Conductor 530 connects Q2 to Q5. Conductor 532 connects Q3 and Q4 to Q6.

The PMOS load transistor is TFT Si
The layer is formed in polycrystalline Si (p-Si), preferably formed by an excimer laser annealing method. The structure begins with the deposition of a thin Si layer and begins with the active island 50.
7 is patterned. A gate insulator layer 508 is formed conformally deposited. Next, a highly doped polysilicon layer is deposited to self-align the silicon gate 5
09 is formed. Ion implantation is used to form P-doped source and drain regions. Source·
Contact and drain contacts are connected to the M2 or M3 metal layer. Drain of TFT Q5
Contact 531 is connected to metal layer M2 to form node F bar. Drain contact 53 of TFT Q6
3 is connected to the metal layer M2 to form a node F. These nodes are connected to the output signal lines F bar and F, respectively. Further, the source contact 512 of the TFT Q5
And the source contact 511 of the TFT Q6 is connected to the M3 layer 514 and then via the via 516 to the fourth metal layer (M4) 517. V _DD is thin film wiring 51
4 to TFT Q6 through interconnect 511 and similarly from thin film wiring 514 to TFT Q5 through interconnect 512. Deposited dielectric layer 510
And 515 separate the thin film wiring levels. Only the essential wiring levels are shown here. Also, only one of the wiring levels placed on V _DD 514 is shown. The rest of the wiring connections are formed by standard VLSI technology.

Specific cases and preferred embodiments of the present invention will be described with reference to FIGS.
3D differential cascode voltage switch with pass gate (D
A new high performance and low power circuit technology called CVSPG) is described. Circuit style is N in DCVS
DCVSPG instead of MOS logical stacking tree
It is designed using the passgate logic tree in. DCV
S is classified as a ratio circuit.
DCVSPG is a ratioless circuit
Is considered. FIG. 10 shows the DCVS in the three-dimensional structure.
FIG. 6 is a circuit diagram of a simple AND / NAND gate formed using PG logic.

In FIG. 10, the left leg of the passgate logic tree consists of two parallel NMOS Q2 and Q1. Here in DCVS, these two N
Although the MOS transistors are in series (see FIG. 8), DC
In VSPG, these two NMOS transistors are in parallel. There are clearly advantages when complex logic functions are designed (see Figures 12 to 15). The right leg of the passgate tree is also two parallel NMOSs
It is composed of Q3 and Q4. Passgate logic trees can be very systematically synthesized by using the Carno diagram recursively. The basic logic with two input variables A and B is shown in FIG. Input signal A or B is NM
Either OS gate control or NMOS source connection. In this case, assuming the signal A is a control variable, the B signal is a functional variable. The control variable is used to connect to the gate and the functional variable is connected to the source of the NMOS device. Under the control signals A bar and A, the term (te
rms) are grouped together as shown in FIG. A bar is connected to the control gates of Q1 and Q3.
A is connected to the control gates of Q2 and Q4. Q1, Q
The sources of 2, Q3 and Q4 are the function variables V _DD ,
Connected to B bar, ground and B. The two cross-connected TFT PMOS transistors Q5 and Q6 form a pull-up network just as shown in FIG.

3D DCVSPG A shown in FIG.
The ND / NAND circuit actually solves the floating node problem by replacing the NMOS tree with a passgate design. In the same previous state, both input signals A
Both Q2 and Q4 turn on when B and B transition from low to high. The node F bar is then discharged to ground when the inverted signals A and B are then transitioned from high to low. However, the output node F is immediately charged to the high state. This implements a dual AND / NAND logic function. The floating node problem does not occur.

FIG. 11 is a detailed sectional view of a structure for realizing the circuit of FIG. For convenience, only transistor levels and selected wire levels up to M4 are shown (full wire levels not shown). The detailed formation of this circuit is very similar to FIG. The only change is the transistor connection mechanism. In FIG. 10, the left leg of the NMOS network is a parallel connection. A p-epitaxial layer 601 is deposited on the p + substrate 600. A standard NMOS to form active transistors Q1 to Q4 on the p + substrate 600.
Process is used. The formation of this structure has already been described above in connection with FIG. Shallow trench isolation (STI) 60
2 separates adjacent elements Q2 and Q3. The deposited polysilicon layer is patterned to form self-aligned Si gates 604, 624, 625 and 626. The N-doped source and drain regions 603 are formed by ion implantation.

Four subsequent connections are connected to the first metal layer (M1).
Is formed by using. The source junction contacts of transistors Q1 and Q2 are connected to V _DD and the input signal B bar, respectively. The source junction contacts of transistors Q3 and Q4 are connected to ground and input signal B, respectively. These connections are made using the deposited polysilicon layer. Q1 transistor gate 60
The transistor gates 625 of 4 and Q3 receive the input signal A
Connected to the bar. The transistor gate of Q2 is connected to the input signal A and the transistor gate of Q4 is also connected to the input signal A. Next, a thick insulator 606
Are deposited by chemical vapor deposition (CVD). As described above, the thick insulator 606 is planarized by chemical mechanical polishing (CMP), leaving a planar surface 618 for subsequent formation of the PMOS load transistor. The via holes are patterned and etched and conductors 630 are deposited to fill the via holes.

Again, the formation of TFTs Q5 and Q6 begins with the active area for transistor island 607. Next, a thin insulator gate insulator layer 608 is deposited. Next, a highly doped polysilicon layer is deposited to form a self-aligned silicon gate 609. Ion implantation is used to form P-doped source and drain regions using gate 609 as a self-aligned mask. TFT Q5 and Q6
Drain contacts 631 and 633, respectively,
A second metal layer (M2) is used to connect to the output signal lines F bar and F, respectively. Further, the source contacts 612 and 611 of the TFTs Q5 and Q6, respectively, are connected to the third metal layer (M3) 614. The connection from M3 to the fourth metal layer (M4) 617 is shown as stud 616. V _DD is applied to TFT Q6 from thin film line 614 through interconnect 611. V _DD is also thin film wiring 6
14 through TFT 612 to TFT Q5. Deposited dielectric layers 610 and 615 separate the thin film wiring levels. Only the essential wiring levels are shown.
Also, only one of the wiring levels placed on V _DD 614 is shown. The rest of the wiring connections are formed by standard VLSI technology.

The most general form of the invention is shown in FIG.
I will describe it with reference to 2. FIG. 12 is a general form of the invention that includes a logic gate with multiple differential (double rail) inputs to form a combinatorial logic network.
There are two cross-connected PMOS TFTs 76 and 77 on top. The logic design means is DCVS or DCVSP
This is accomplished by G by cascoding the differential pair of NMOS devices into a powerful combinatorial logic tree network capable of handling complex Boolean logic functions. Therefore, conventional CMO
The complex logic that may require several gates in S is
It can be implemented with a single stage gate in DCVS or DCVSPG. For example, as shown in FIG. 13, in a conventional CMOS circuit, a logical addition circuit can be realized by 16 transistors (8 PMOS transistors and 8 NMOS transistors). On the other hand, in DCVS, 12 transistors (2 PMOS transistors and 10 NMOS transistors) are provided as shown in FIG. 14, and in DCVSPG, 10 transistors (2 transistors are provided as shown in FIG. 15). Of P
MOS transistor and 8 NMOS transistors)
Form a logic gate circuit.

The combinational logic element is a non-stacked PM
It can be designed using OS devices as pull-up devices in load and buffer circuits. Therefore, the optimization of the PMOS device and the optimization of the interval between the PMOS and the NMOS are relaxed, which reduces the burden of device and process complexity in the DCVS design.

In accordance with the present invention, for a single set of process steps forming both logical and memory structures,
It will be described with reference to FIGS. 16 to 19. These figures show the thin film transistor (TFT) PMOS of the present invention.
1 illustrates a general flow of process steps for forming a level. First, assume that a completed NMOS transistor level 802 is present on a Si wafer substrate 801. The thick insulator 803 is chemically mechanically polished (C
MP) to adhere and planarize. This allows TFT
A smooth starting surface 800 for formation is provided. Via holes 804 are lithographically patterned, etched, filled with conductors and interlevel connections 8
Form 05. The conductor is preferably a refractory metal such as tungsten. After planarization of the interlevel connection 805, a thin film of amorphous Si (about 500 Å (Å) to 1000Å thick) is deposited by a suitable method (sputtering, plasma enhanced CVD or LPCVD) and lithographically patterned into islands. Converted to p-Si. Excimer laser annealing (ELA) is deposited amorphous Si
Rapid thermal annealing (RTA) may also be used, although it is the preferred method for crystallizing thin films . FIG. 16 shows the resulting polysilicon island 806.

FIG. 17 shows the deposition of the gate dielectric 807, which is preferably about 1000 Å to 1500 Å thick amorphous SiO ₂ and is deposited by chemical vapor deposition (CVD).
It is deposited at a temperature of 00 ° C to 400 ° C. The gate electrode is deposited as a blanket metal layer (aluminum or other metal) and lithographically patterned to form gate 808. P-type additive boron 80
9 are placed in the thin film Si layer 806 by ion implantation or ion shower doping. The energy of the B + ions is selected such that the ions penetrate the dielectric 807 and enter the thin film Si layer 806. Gate 8
08 is used to mask the layer where the additive is not placed, so the gate is a self-aligned mask. Optionally, a two step doping procedure may be used to form the lightly doped drain structure. The structure is then heated by RTA or ELA method for a few seconds to activate the boron atoms of the additive.

FIG. 18 shows the deposition of thick insulator 810,
This is amorphous SiO ₂ or silicon nitride deposited by chemical vapor deposition. Via holes 811 are patterned and etched to contact the source and drain regions 812 of the TFT.

FIG. 19 shows the deposition of conductor 813 filling via hole 811. The preferred material is aluminum, but other metals can be used. Source / drain metal levels 814 are deposited and patterned into thin film wiring (TFT source / drain metal levels). Finally, passivation insulator 815 is deposited. Here is the circuit diagram and TF
Wiring level 814 is not shown in detail to emphasize the T layer. The essential wiring levels are shown in FIGS.

In summary, the following matters will be disclosed regarding the configuration of the present invention.

(1) A plurality of transistors formed in two separate semiconductor levels, a bulk silicon (Si) level and a thin film Si level, in a single integrated circuit (IC) chip, Transistors form a logic circuit in a selected area of the IC chip, and a static random access transistor in a remaining area of the IC chip.
Transistors connected to form a memory (SRAM) array. (2) A p-type metal oxide semiconductor (PMOS) load element formed in the thin film Si level and the bulk Si
N-type metal oxide semiconductor (NM
The transistor according to (1) above, including an OS) driving element. (3) The transistor according to (1), wherein the transistor connected to form the logic circuit is configured as a differential cascode voltage switch (DCVS) logic. (4) The transistor according to (3), wherein the transistor is connected to form a complex Boolean logic function element in an n-tree network. (5) The transistor according to (1) above, wherein the transistor connected to form the logic circuit is configured as a differential cascode voltage switch (DCVS) logic having a pass gate. (6) The transistor according to (5), wherein the transistor is connected to form a complex Boolean logic function element in an n-tree network. (7) A cell of the SRAM array is formed in four n-type metal oxide semiconductor (NMOS) drive transistors formed in the bulk Si level and in the thin film Si level disposed on the drive transistors. And the two p-type metal oxide semiconductor (PMOS) load transistors described in (1) above. (8) The transistor according to (1), wherein the two Si levels are separated by a dielectric layer that is planarized by chemical mechanical polishing (CMP) before forming the thin film Si layer. (9) An n-type metal oxide semiconductor (NMOS) transistor formed in the bulk Si level, and the NMO.
A p-type metal oxide semiconductor (PMOS) transistor formed in the thin film Si level disposed on the S-transistor, the thin film Si level being an excimer
Formed by a laser annealing (ELA) method,
The transistor according to (1) above. (10) A method of forming a plurality of transistors in two separate semiconductor layers in an integrated circuit (IC) chip, the method comprising:
Forming an n-type metal oxide semiconductor (NMOS) transistor in the bulk silicon (Si) level; depositing a thick insulator on the bulk Si level; and depositing the deposited thick insulator on the bulk Si level. A planarization step, and a thin film (T) on the planarized thick insulator.
F) forming a Si level, said TF Si
Implanting a p-type additive into the level, and adding a p-type metal oxide semiconductor (PM) into the TF Si level.
OS) forming a transistor. (11) The above (1), wherein the p-type additive is boron.
0) The method described. (12) connecting the transistors to form a logic circuit in a selected area of the IC chip;
Connecting the transistors to form a static random access memory (SRAM) array in the remaining area of the IC chip. (13) The transistor connected to form the logic circuit is a differential cascode voltage switch (DCV).
S) The method according to (10) above, which is configured as logic. (14) The method according to (13), wherein the transistors are connected to form a complex Boolean logic function element in an n-tree network. (15) The method according to (10), wherein the transistors connected to form the logic circuit are configured as a differential cascode voltage switch (DCVSPG) logic having a pass gate. (16) The method according to (15), wherein the transistors are connected to form a complex Boolean logic function element in an n-tree network.

[Brief description of drawings]

FIG. 1 is a block diagram of a conventional planar SRAM cell.

FIG. 2 is a plan view of a conventional planar SRAM cell.

FIG. 3 is a configuration diagram of a conventional three-dimensional SRAM cell.

FIG. 4 is a sectional view of a conventional three-dimensional SRAM cell.

FIG. 5 is a block diagram of a conventional DCVS logic cell.

FIG. 6 is a plan view of a conventional DCVS logic cell.

FIG. 7 shows a complementary metal oxide semiconductor (CMO) according to the present invention.
S) A sectional view showing a three-dimensional structure of a transistor pair.

FIG. 8 is a configuration diagram of a three-dimensional DCVS logical AND / NAND gate.

FIG. 9 is a cross-sectional view of a three-dimensional DCVS logic AND / NAND gate.

FIG. 10 is a block diagram of a specific logical AND / NAND gate formed by three-dimensional DCVSPG (pass gate) logic.

FIG. 11 is a cross-sectional view of a particular logic AND / NAND gate formed by three-dimensional DCVSPG (pass gate) logic.

FIG. 12 is a block diagram and block diagram of general n-tree logic formed by three-dimensional DCVS logic.

FIG. 13 is a configuration diagram of a conventional (two-dimensional) static CMOS adder circuit formed by DCVS logic.

FIG. 14 shows two PMOS thin film transistors (TFTs).
And 3 using 10 NMOS crystalline Si transistors
It is a block diagram of a three-dimensional DCVS addition circuit.

FIG. 15: Two PMOS TFTs and eight NMOSs
It is a block diagram of the three-dimensional DCVSPG addition circuit which uses a crystalline Si transistor.

FIG. 16 is a cross-sectional view showing TFT-level process steps used in both 3D SRAM and 3D DCV logic.

FIG. 17 is a cross-sectional view showing TFT-level process steps used in both 3D SRAM and 3D DCV logic.

FIG. 18 is a cross-sectional view showing a TFT level process procedure used in both 3D SRAM and 3D DCV logic.

FIG. 19 is a cross-sectional view showing TFT-level process steps used in both 3D SRAM and 3D DCV logic.

[Explanation of symbols]

1, 11, 12, 21, 23, 31 Active n silicon layers 3, 4, 5, 13, 14, 15, 16, 17, 28, 3
4, 35, 36, 37, 38, 39, 406 Polysilicon layers 6, 7, 40, 50, 513, 514, 517, 61
4,617 metal layers 10, 18, 20, 30, 32, 40, 41, 42, 4
3, 45, 47, 49, 51, 53, 55, 57, 40
9, 505, 511, 512, 531, 533, 60
5, 611, 612, 628, 631, 633 Source or drain contact 32 Active p silicon layer 33 n-well region 400, 802 NMOS transistor 401, 500, 801 Silicon wafer substrate 402, 410, 506, 606, 803, 810 , 8
11,815 Insulators 403, 516, 530, 532, 616, 630, 8
04 via hole 404, 530, 532, 630, 805, 813 conductors 407, 508, 608, 807 gate dielectric layer (insulating layer) 408 gate conductor 411 PMOS load transistor 501, 601 p-epitaxial layer 502, 602 trench isolation 503 , 603, 812 Source or drain regions 507, 607, 806 Polysilicon islands 509, 524, 525, 526, 527, 604, 6
09, 624, 625, 626 Silicon gate 510, 515, 610, 615 Dielectric layer 609, 808 Gate 616 Stud 809 Boroned 814 Source or drain metal level

Front page continuation (51) Int.Cl. ⁷ Identification code FI H01L 21/8244 H01L 27/04 A 27/04 27/06 102J 27/06 27/10 381 27/10 461 29/78 613B 27/11 H03K 19/094 A 29/786 H03K 19/0944 19/20 (72) Inventor Philip George Emma United States 06811, Connecticut Fox Den Road 28 (72) Inventor Wei Huang United States 10504, New York Armonk, Long Pond Road 3 (72) Inventor Stefan McConnell Gates, United States 10562, Inningwood Road, Oschining, NY 22 (56) Reference JP-A-6-13576 (JP, A) JP-A-6-13576 8-241957 (JP, A) JP-A-62-190753 (JP, A) JP-A-9-45922 (JP, A) JP-A-8-167655 (JP, A) IEEE Journal of Solid State Circit s, Vol. 32, No. 4, April 1997, pp. 563-573

Claims (7)

(57) [Claims] 1. A plurality of three-dimensional structures formed in two separate semiconductor levels, a bulk silicon (Si) level and a thin film Si level, within a single integrated circuit (IC) chip.
An IC chip consisting of transistors, said Val
The plurality of transistors at the Si level and the thin film S
The i-level transistors are respectively
Differential cascode voltage scans are performed in selected areas of the IC chip.
Switch (DCVS) logic circuit differential input transistor and
And a load transistor, and
In the remaining area of the IC chip, static random
Drive Transistor for Each Cell of the Memory Access Memory Array
Connected to form a star and load transistor
Merged logic and memory IC chip. Wherein according to the DCVS the differential displays the amount <br/> claim 1 connected to transistor constitutes a complex Boolean logic function element into the n- tree network in the logic circuit I
C chip. 3. The DCVS logic circuit includes a pass gated differential circuit.
Dynamic Cascode Voltage Switch (DCVSPG) logic circuit
The IC chip according to claim 1 . Wherein said differential input <br/> transistors of the DCVSPG logic circuit, IC chip according to claim 3 which is connected to form a complex Boolean logic function element into the n- tree network . 5. Within a single integrated circuit (IC) chip,
Silicon level (Si) and thin film Si level 2
Multiple three-dimensional structures formed in two separate semiconductor levels
A method of forming an IC chip comprising a combination of the number of transistors, the bulk Si level in the steps of forming a plurality of n-type metal oxide semiconductor (NMOS) transistors, thick on the bulk Si level on an insulating Depositing a body, planarizing the deposited thick insulator, forming a thin film Si level on the planarized thick insulator, p-type additive in the thin film Si level Implanting a plurality of p-type metal oxide semiconductor (PMOS) transistors in the thin film Si level, the plurality of NMOS transistors and the plurality of PMOs.
S-transistors are respectively selected from the IC chips.
The differential cascode voltage switch (DCV
S) Differential input transistor and load transistor of logic circuit
Connected to form a star and the IC chip
In the remaining area, static random access
The drive transistor and load transistor of each cell of the memory array
A method of forming a merged logic and memory IC chip comprising the steps of connecting to form a transistor . 6. The DCVS theory according to the step of connecting.
The method of claim 5 including connecting the differential input transistors of a logic circuit to form a complex Boolean logic functional element in an n-tree network. 7. The connecting step comprises the steps of :
OS transistor and the plurality of PMOS transistors
Respectively in selected areas of the IC chip,
Differential cascode voltage switch with pass gate (DCVS
PG) the differential input transistor and load transistor of the logic circuit
Claims including connecting to form a transistor.
The method according to 5 .