JP2008004666A - Method of manufacturing three dimensional semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a performance suitable for a current IC by improving crystallinity of a laser (re) crystallizing Si layer; in a method of manufacturing a three dimensional semiconductor device in which an insulating film is formed on an Si layer where a circuit of semiconductor elements is formed, a polycrystal or amorphous Si layer is stacked on the insulating film, the stacked layer is (re) crystallized by laser irradiation or scanning to form another circuit of semiconductor elements there, and these circuits are connected together. <P>SOLUTION: Insulating films 17 and 26 are flattened by CMP. Polycrystal or amorphous Si layers 22 and 32 are stacked, which are irradiated/scanned with solid continuous wave laser having energy of 10 J/cm<SP>2</SP>or higher per radiation area. A laser annealing is applied just after it. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

The present invention relates to a method for manufacturing a three-dimensional semiconductor device, particularly a semiconductor device that is three-dimensionally multilayered for use in an IC such as a storage device such as a DRAM, SRAM, or a flash memory, or a microprocessor.
Hereinafter, the prior art will be described in the following order.
(B) Three-dimensional semiconductor device using laser recrystallization (b) Three-dimensional semiconductor device not using laser recrystallization (c) Main / sub beam laser irradiation (d) Laser annealing (e) Laser recrystallization (F) Large power laser (g) Insulating film

(B) 3D semiconductor device using laser recrystallization Non-patent document 1 (ECS, Vol1, No. 2, March-April, 1990, pp 137-142, “Feasibility of 3D Integration”, Nobuo Sasaki) Without destroying the device formed on the Si substrate, recrystallize Si under seed less growth conditions on the SiO ₂ layer using a laser (type not specified) recrystallization technique, It explains that a three-dimensional semiconductor device is manufactured by forming a transistor in this recrystallized layer and bonding it to a transistor formed on a Si substrate. An example of a three-layer SRAM is shown as an example of a three-dimensional semiconductor device.

  In Non-Patent Document 1, it is important to control the heat flow caused by laser irradiation in order to form a Si layer without crystal grain boundaries. Specific means include a heat sink structure, indirect laser annealing, an antireflection cap, and the like. It is explained that there is. Although the recrystallized structure actually formed is a structure in which many grain boundaries are arranged in a wedge shape, it is stated that the characteristics of MOSFETs are the same as those of SOI without grain boundaries. However, it can be said that the obtained Si layer does not satisfy the crystallinity required for current IC devices.

In Non-Patent Document 1, as a mask for manufacturing 3DCMOS, (a) first layer active region formation, (b) first layer polycrystalline Si gate patterning, (c) second layer active region formation, (d) (2) Polycrystalline Si gate patterning of the second layer, (e) Contact opening, (f) Al patterning etching for electrodes, and (d) Opening of bond pads. Gate insulating films are formed between the mask steps (a) and (b) and between (c) and (d).
The manufacturing process will be described with reference to these masks. (A) The first layer active region is formed on the Si substrate, while (c) the second layer active region is formed by CVDSiO ₂ with the first layer structure. After coating, a polycrystalline Si layer and the like are once formed, laser recrystallized, and then patterned using a mask to make a three-dimensional device.

Non-Patent Document 2 (Mat. Res. Symp. Proc. Vol. 33 (1984) “3-DIMENSIONAL INTEGRATION FABRICATED BY USING SEEDED” LATERAL EPITAXIAL FILM ON SiO ₂ "N. SASAKI et al). From the underlying single crystal Si, Si recrystallized by CW laser irradiation crystallization extends 20 μm laterally on the SiO ₂ film. Therefore, an attempt is made to grow a crystal close to a single crystal that has inherited the seed orientation by using the base single crystal as a seed, but the single crystal growth distance in the lateral direction is at most 20 μm.

  Non-Patent Document 3 (Appl. Phys. Lett 44 (10), 15 May, 1984m pp 994-996, Single crystalline Si islands on an amorphous insulating layer recrystallized by an indirect laser heating technique for three-dimensional integrated circuits. R. Mukai According to et al), the Si layer on the Si substrate on which the MOSFET is formed is recrystallized by laser irradiation to form a second MOSFET. In this document, argon ion laser irradiation is performed through the Si cap layer, whereby the Si layer under the Si cap layer is indirectly heated to recrystallize.

According to Non-Patent Document 4 (Journal of Electronic Materials, Vol. 15, No. 6, 1986, Laser-Recrystallized Film with a Control of Grain Boundary Location Using Surrounding Antiflection Cap Method), SOI having an insulating film structure on the Si substrate surface An MOSFET is formed on top of this, and an Ar laser recrystallization method is used to eliminate the grain boundary from the crystal in the channel region. Specifically, the insulating film is a 1 μm SiO ₂ , 0.1 μm Si—N film, and a 0.4 μm poly Si layer having a <110> orientation is formed thereon, and a part of the Si layer is exposed. When the cap layer is formed and laser irradiation is performed, the center is low in the window portion without the cap layer, and a high temperature gradient is generated around the periphery, so that nucleation proceeds from the center of the window to the periphery of the window. In the Si layer located under the window, there is no crystal grain boundary, and a <100> oriented Si layer is generated. Certainly, the Si layer under the window is a single-crystal region with no grain boundaries, but many streak-like grain boundaries have been observed in the cross-section and plane around the Si layer. It is not a polycrystalline structure.

  According to Non-Patent Document 5 (2000-IEDM, Selective Single-Crystalline-Silicon Growth at the Predefined Active Region of TFT's on a Glass by Scanning CW Laser Irradiation. A. Hara et al) It has been reported that single crystal Si having a width of 1.5 μm and a length of 20 μm was formed on a glass substrate by the chemical method. In this method, a Si cap layer is formed above the channel region of the transistor, thereby making crystal growth a single crystallization condition.

In Non-Patent Document 6 (2002-IEEE; High-Performance Single-Crystalline-Silicon TFT's on a Non-Alkali Glass Substrate. Y. Sano et al), the width is increased by the recrystallization method using Nd: YVO ₄ solid-state continuous wave laser. It has been reported that single-crystal Si having a length of 8 μm and a length of 20 μm was made on a glass substrate. In this method, a Si cap layer is formed above the channel region of the transistor, thereby making crystal growth a single crystallization condition. FIG. 1 (a) of FIG. 1 showing a cross-sectional view of a cap layer is shown in FIG. 1, FIG. 3 (b) showing a plan view is shown in FIG. 2, and FIG. 5 showing a source / drain region is shown in FIG. Quote. A large number of crystal nuclei exist at the end of the region A where the laser scanning starts, the crystal grain boundary extends in a V shape from the crystal nucleus, and then merges to form a parallel crystal grain boundary. In the region marked Nucleus in FIG. 2, the fine irregularities of the substrate are grain boundary generation sources. If the grain boundary accidentally passes through the capping Si gap, this extends to region C. Also, the grain boundaries marked as Parallel grains disappear in the middle of the scan line, so it can be said that the grain boundaries are very unstable. The transistor is formed in a single crystal region having no crystal grain boundary.

(B) Three-dimensional semiconductor devices that do not use laser recrystallization As described above, laser recrystallization has been proposed, but the mainstream of subsequent development of three-dimensional semiconductor devices is to transfer or peel off a single crystal Si substrate. Heading the way. Some of the prior art in this field are listed below.

  Patent Document 1: Japanese Patent Application Laid-Open No. 2005-86089 includes a step of peeling and transferring at least one of thin film device layers from another substrate.

  Patent Document 2: Japanese Patent Laid-Open No. 2001-189419 states that laser SOI has developed a method that does not depend on laser recrystallization because it is difficult to ensure crystallinity. In this patent document, two semiconductor substrates on which IC circuits are formed are bonded so that the IC circuits face each other and are electrically connected.

  Non-Patent Document 7: 2005 IEEE New Three-Dimensional Integration Technology Using Self-Assembly Technique, Fukushima et al, for example, DRAM, SRAM, flash memory, logic LSI, power IC, analog LSI, MMIC, sensor chip, etc. A technology called Super Smut Cut Technology has been announced. The essence of this technology is that a chip is separated from a wafer that has been formed on a wafer and has been confirmed to have good performance, such as a wafer in which DRAM, SRAM, flash memory, etc. are formed in the above example. There is a place to pile up.

(C) Main / sub beam type laser irradiation Patent Document 3: Japanese Patent No. 2748377 (Japanese Patent Laid-Open No. 1-128422) relates to a method of recrystallizing poly-Si or the like with two main and sub lasers. In particular, it has been proposed to suppress the rise of the melt by irradiating the sub-beam to the solidification end where the melt generated by the main beam irradiation solidifies.

  Patent Document 4: Japanese Patent No. 3289681 (Japanese Patent Laid-Open No. 2000-21776) relates to a method of recrystallizing polycrystalline Si having a large particle diameter by pulse laser irradiation, and is emitted from a first pulse laser light source. Proposed to control the cooling rate of the heating and cooling process by emitting a second pulse laser after the semiconductor melted by irradiation of the pulsed light reaches the maximum temperature and until solidification is completed. ing. The theory underlying this proposal is the idea that a low solidification rate is necessary to obtain good crystals. The produced crystal is a polycrystalline material having a substantially circular grain boundary.

  Patent Document 5: Japanese Patent Application Laid-Open No. 2001-126987 discloses that an amorphous Si is irradiated with an excimer laser beam having an energy E1 that produces crystals and crystallites having a large particle diameter, and then the crystallites having energy lower than that of E1 are applied. It has been proposed to irradiate an excimer laser beam with energy that can be melted and recrystallized.

  Patent Document 6: Japanese Patent Laid-Open No. 2003-068644 relates to a method of recrystallizing polycrystalline Si having a large particle diameter by pulse laser irradiation, and a material having a closed crystal grain boundary is generated. In this method, Si is melted by the first pulse laser beam, and then the crystal grains are grown by the second pulse laser beam without completely dissolving the Si crystal grains.

  Patent Document 7: Japanese Patent Application Laid-Open No. 2004-207691 discloses a method of irradiating a thin silicon film with a pulsed laser beam having a fine width, and repeatedly melting and solidifying the irradiated silicon thin film over the entire thickness direction of the irradiation region of the laser beam. As a method of increasing the lateral growth distance, an irradiation method in which a second laser beam is irradiated to a region including the irradiation region of the first laser beam is proposed as a method for increasing the lateral growth distance. It has been proposed to heat the semiconductor and reduce the crystal growth rate, thus increasing the lateral growth distance and producing a polycrystalline material in which the individual crystals consist of long crystals.

(D) Laser annealing technology Non-patent document 8: "Si thin film melting by laser annealing, high-performance poly-Si crystallization technology based on crystallization process", Hatano et al., Laser Research Vol. 31 (2003) No. 1 Pp. 57-62 elucidate the following points regarding the recrystallization of poly Si that is melted and solidified in an extremely short time by an excimer laser: the lateral crystal growth rate is 7 m / s; The characteristics are a grain size of 5 μm or more and the preferred plane orientation 110; the device characteristics are field-effect mobility 460 cm ² / Vs.

Non-Patent Document 9: “NMOS-Junction Integration Study with Ultra-High Temperature Non-Diffusive Laser Annealing for the 45nm Node and Below” Ext Abs 5 th International Workshop on Junction Technology, 2005, S 1-3, Pouydebaseque et al states that laser annealing is equivalent to flash annealing in terms of impurity diffusion distance.

(E) Display device utilizing laser recrystallization By the way , generally, alkali-free glass with a heat-resistant temperature of 750 ° C. or lower is used for the display device, and it is sold by Corning under the trade name Eagle 2000. . An SOI wafer in which a polysilicon thin film transistor is formed on an insulating film coated on a substrate is used. In this SOI wafer, by crystallization (ELC) of amorphous Si by excimer laser irradiation, an electron mobility of 100 times or more than that of an amorphous Si transistor has been achieved.

  Recently, even greater progress has been achieved in SOI wafers for display devices (Non-Patent Document 10: Monthly Display, February 2003, Reprint, “CW Lateral Crystallization (CLC) Technology and High Mobility Low Temperature Poly on Glass Substrate) Si-TFT ”, Nobuo Sasaki, pp. 43-50. In this document, TFT mobility is increased to be comparable to bulk single crystal MOSFETs in SOI devices using glass substrates. The description of Non-Patent Document 10 is cited below.

Quote 1:. . . The CLC technology will be described in comparison with the ELC method, which is a conventional low-temperature poly-Si crystallization technology. The common point is that the buffer SiO ₂ is deposited on the glass substrate and the amorphous Si deposited thereon by PCVD is crystallized by laser irradiation. In ELC, pulsed laser irradiation is repeated with the melting region shifted slightly. The overlap of the melted area between the previous and subsequent irradiations is 90-99%, so each location will receive 10 to 100 pulsed irradiations. The crystal grains can be aligned by this multiple times of pulse irradiation, and variations in TFT characteristics are suppressed. For each pulse. . . Crystal growth from the interface with the underlying SiO ₂ and crystal growth from the side occur, but out of the melt width of 0.4 mm, the growth from the side only has a length of several μm at most, and the majority is the base It is a crystal grain region grown upward from the interface. If a crystal consisting only of a narrow lateral growth region from the side surface obtained by pulse irradiation is repeatedly irradiated while shifting the laser spot in steps of several μm, which is the narrow region width, it can also be produced by a pulse laser.

  Citation 2: In CLC, irradiation is performed while scanning a continuous wave (CW) solid-state laser. The Si portion irradiated with the laser spot melts and crystal growth occurs as the spot moves laterally with respect to the substrate. That is, the lateral growth is mechanically lateral by continuous scanning of the laser spot in the lateral direction.

  Citation 3: CLC always has a melting region, and as a result, one solid-liquid interface is maintained, and the crystal growth is performed by moving the solid-liquid interface to the lateral, so continuous and steady crystal growth. Is a process.

  Reference 4: A SEM photograph of the crystal surface after Secco etching to reveal the grain boundary. The crystal obtained by CLC has a structure in which crystal grain boundaries are arranged almost in parallel, and the size of the single crystal region is about 0.3 μm of excimer laser crystallization (ELC), which is widely used at present. Compared to grains, it is overwhelmingly larger than the normal TFT channel region.

  Citation 5: In ELC poly-Si-TFT, it is thought that the mobility is lowered because the carrier must exceed the potential barrier at the grain boundary, but the source / When the drain direction is formed, even if randomly generated grain boundaries happen to exist in the TFT channel region, carriers do not need to exceed the potential barrier of the grain boundary, and the TFT is as large as when there is no grain boundary in the channel region. Mobility is obtained.

  Reference 6: The throughput of crystallization is determined by the area scanning speed which is the product of the melt width and the scanning speed. In ELC, the scanning speed is very small due to the limitation of pulse frequency, but in CLC, a large scanning speed can be obtained. However, if the scanning speed is simply increased while maintaining the same irradiation power with the same laser spot shape,. . . TFT mobility decreases and approaches the ELC value. At this time, the grain boundary has changed from the grain boundary on the flow aligned in one direction to the grain boundary of the excimer granularity (polygonal), so that the grain boundary scattering increased and the mobility decreased. Understandable.

Reference 7: Change in grain boundary shape due to scanning speed is as follows. . . This is because the angle of the solid-liquid interface with respect to the substrate surface is inclined from vertical to diagonal, and as a result, the lateral growth approaches the vertical growth of ELC. . . . The CLC laser irradiation energy density is calculated to be 12.5 J / cm ² at a scanning speed of 20 cm / s and 1.25 J / cm ² at 200 cm / s. On the other hand, in ELC, the energy density per pulse is about 0.3 J / cm ² , but in ELC, 90 to 99% overlap irradiation is performed, so the irradiation energy density is 3 to 30 J / cm ² .

Reference 8: The mobility of the transistor is higher when the laser scanning speed is slower, and a mobility of 500 cm ² / V-sec or more is obtained with an irradiation energy of 10 J / cm ² or more.

  Reference 9: The wavelength of the laser is 532 nm, and the output fluctuation is less than 1%.

  Quote 10

The orientation of the Si crystal layer obtained by the CLC method is almost (100) (Non-Patent Document 11, IEDM01-747 “High Performance Poly-Si TFT on a Glass by a Stable Scanning CW Laser Lateral Crystallization” (Akito Hara et al) The diode-pumped solid-state continuous wave laser (10W, 532nm, Nd: YVO ₄ ) was used, and the spot size was 400 × 20μm. Crystallized.

  Non-Patent Document 12 (SID 02 DIGEST, 12.3: High Throughput CW-Laser Lateral Crystallization for Low-Temperature Poly-Si TFTS and Fabrication of 16 bit SRAMs and 270 MHz Shift Registers, N. Sasaki et al, pp 154-156, A single crystal region having a width of 150 μm, which is substantially the same as that of Non-Patent Document 8 and is selectively irradiated with four solid continuous wave lasers each having a width of 150 μm and an output of 6-7 watts simultaneously. (4 rows x 5 = 20 in the figure) are formed.Amorphous Si is between each row.Si between 5 single crystal Si in each row takes precedence over (100) A pixel device, which is an oriented polycrystal and may be slow in mobility, is fabricated, and a device such as an SRAM is fabricated in the 20 single crystal regions.

  According to Non-Patent Document 13 (ECS, May 2005, Process Integration of Glass Substrate by CW-Laser Lateral Crystallization (CLC) Nobuo Sasaki), the thickness of the amorphous Si layer subjected to CLC is 40-250 nm.

  Non-Patent Document 14 (Appl. Phys, Lett. 45 (10), pp 1098-1100, 15 November 1984, “Melt-width enhancement in the recrystallization of reactive silicon-on-insulator by twin-laser-beam-induced substrate inter In “heating” Nobuo Sasaki et al), polycrystalline Si on an amorphous insulating layer is recrystallized by twin CW argon laser irradiation / scanning, so there is no grain boundary or sub-grain boundary, width 20 μm, length 1.8 A recrystallized region of mm is formed.

  Usually, a grain boundary is a boundary between crystal grains grown from nuclei. On the other hand, in the CLC method, it is not clear from citations 2 and 3 where nucleation occurs, and in citation 4, it is described as “like a grain boundary”. Non-Patent Document 10 uses the term crystal grain boundary. Although it is not clear from these documents whether the defects that appear linear in the laser scanning direction are indeed normal grain boundaries, in this specification, the structure of the CLC-treated Si layer is referred to The term “grain boundary” described in the above is quoted as it is. In any case, it is clear that the characteristics of the transistor become better as the number of crystal grain boundaries decreases.

(F) Large power laser By the way, the laser technology is Nisshin Shinpo, and according to recent information, a 412W solid state green laser has been developed (Non-Patent Document 15: July 5, 2005 announced by Mitsubishi Electric Corporation, Search the internet). This laser is a pulse oscillation having an oscillation wavelength of 532 nm. In general, it is considered that the output is reduced to less than 1/10 when continuous (cw) oscillation is used, but this output greatly exceeds the output of the continuous wave laser used in the above-mentioned prior art documents.

(G) Insulating film Patent Document 8: Japanese Patent Application Publication No. 2004-535062 discloses that the SiO ₂ layer of MOS-FET is amorphous, so that the layer near Si is filled with defects, resulting in a decrease in switching speed. It states that you are. In this patent document, in order to form a single atomic layer of Si and O (oxygen) during deposition of Si on a Si substrate, an insulating film is formed by introducing oxygen so that SiOx (0 <x <2) is satisfied. The properties have been improved.
JP 2005-86089 A JP 2001-189419 A Japanese Patent No. 2748377 Japanese Patent No. 3289681 JP 2001-126987 A Japanese Patent Laid-Open No. 2003-068648 JP 2004-207769 A JP-T-2004-535062 ECS, Vol1, No. 2, March-April, 1990, pp 137- 142, “Feasibility of 3D Integration”, Nobuo Sasaki Mat. Res. Symp. Proc. Vol. 33 (1984) “3-DIMENSIONAL INTEGRATION FABRICATED BY USING SEEDED LATERAL EPITAXIAL FILM ON SiO2” N. SASAKI et al. Appl. Phys. Lett 44 (10), 15 May, 1984m pp 994-996, Single crystalline Si islands on an amorphous insulating layer recrystallized by an indirect laser heating technique for three-dimensional integrated circuits.R. Mukai et al. Journal of Electronic Materials, Vol. 15, No. 6, 1986, Laser-Recrystallized Film with a Control of Grain Boundary Location Using Surrounding Antiflection Cap Method 2000-IEDM, Selective Single-Crystalline-Silicon Growth at the Predefined Active Region of TFT's on a Glass by Scanning CW Laser Irradiation. A. Hara et al. 2002-IEEE; High-Performance Single-Crystalline-Silicon TFT's on a Non-Alkali Glass Substrate. Y. Sano et al. 2005 IEEE New Three-Dimensional Integration Technology Using Self-Assembly Technique, Fukushima et al "Si thin film melting by laser annealing, high-performance poly-Si crystallization technology based on crystallization process", Hatano et al., Laser Research Vol. 31 (2003) No. 1, pp. 57-62 “NMOS-Junction Integration Study with Ultra-High Temperature Non-Diffusive Laser Annealing for the 45nm Node and Below” Ext Abs 5 th International Workshop on Junction Technology, 2005, S 1-3, Pouydebaseque et al Monthly Display, February 2003, Reprint, “CW Lateral Crystallization (CLC) Technology and High Mobility Low Temperature Poly-Si-TFT on Glass Substrate” Nobuo Sasaki, pp. 43-50 IEDM01-747 ”High Performance Poly-Si TFT on a Glass by a Stable Scanning CW Laser Lateral Crystallization” (Akito Hara et al). SID 02 DIGEST, 12.3: High Throughput CW-Laser Lateral Crystallization for Low-Temperature Poly-Si TFTS and Fabrication of 16 bit SRAMs and 270MHz Shift Regsiters, N. Sasaki et al, pp 154-156 ECS, May 2005, Process Integration of Glass Substrate by CW-Laser Lateral Crystallization (CLC) Nobuo Sasaki) Appl. Phys, Lett. 45 (10), pp 1098-1100, 15 November 1984, “Melt-width enhancement in the recrystallization of present silicon-on-insulator by twin-laser-beam-induced substrate inter heating” Nobuo Sasaki et al) Realizing approximately twice the high output with the same size as before, developing the world's highest output 412W "solid green laser", July 5, 2005 Mitsubishi Electric Corporation, Internet search literature "Electronic Materials" December 2004 issue, VLSI manufacturing / test equipment guidebook, CMP equipment, pp. 137-145

  As described in Patent Document 2, a general view is that a three-dimensional device by laser recrystallization has a problem in performance, and it is not based on a laser as proposed in Non-Patent Document 7. Development of manufacturing methods for three-dimensional semiconductor devices is currently the mainstream. Certainly, the crystallinity of the Si layer formed by the laser recrystallization technique proposed in Non-Patent Document 1 is inferior. In other words, IC semiconductor devices are now increasingly miniaturized, and as a result, higher speeds, lower power consumption, and higher reliability are progressing further. Of course, high density is also pursued by the method of Non-Patent Document 1 by a three-dimensional structure, but in the 1990s when Non-Patent Document 1 was published, the pattern rule was about 500 nm, and now it is 90 nm. In order to meet the pattern rule of 70 to 90 nm, it is necessary to improve the crystallinity of the Si layer because it is predicted that it will be 70 nm in the near future.

  The present inventors proposed a manufacturing method of an SOI wafer for a display whose substrate is glass proposed by Non-Patent Document 10, that is, a solid-state continuous wave laser crystallization method of a three-dimensional semiconductor device disclosed in Non-Patent Document 1. Focused on manufacturing application. The latter semiconductor device is an arithmetic unit, a storage device, etc., and the clock pulse is higher than that of the former display device, and the pattern rule is stricter than that of the former. Therefore, the crystal characteristics are insufficient only by CLC crystallization. In particular, Si obtained by CLC crystallization has many dislocations and crystal defects that can be seen at grain boundaries detected by Seco Etch. Furthermore, since an IC circuit element is formed on a single crystal Si substrate which is a general material of a three-dimensional semiconductor device, high temperature treatment may deteriorate the characteristics of these elements.

  In consideration of the situation described in the preceding two paragraphs, the present inventors currently require the IC to have crystallinity of a Si (silicon) layer recrystallized by a CLC method using a solid-state continuous wave laser. Development is being carried out for the purpose of manufacturing three-dimensional semiconductor devices without significant modifications to existing semiconductor device manufacturing equipment lines, while improving to meet the demands for miniaturization and higher speeds.

One of the present applicants in Japanese Patent Application No. 2006-104503 (hereinafter referred to as “prior application”) filed on April 5, 2006 formed an insulating film on the Si layer on which the circuit of the semiconductor element is formed. A polycrystalline Si layer or an amorphous Si layer having a hydrogen content of 1 atomic% or less is laminated on the insulating film, and the polycrystalline Si layer or the amorphous Si layer is irradiated with laser and scanned. In a method of manufacturing a three-dimensional semiconductor device in which a circuit of another semiconductor element is formed in a recrystallized or crystallized Si layer and these circuits are connected, the insulating film is formed at least on the insulating film. After planarizing by CMP, the polycrystalline Si layer or the amorphous Si layer is laminated, and laser irradiation and scanning for recrystallizing or crystallizing the Si layer are performed with an energy of 10 J / per irradiation area. Performed by a solid continuous wave laser of cm ² or more, Hydrogen ions are added to the recrystallized or crystallized Si layer irradiated with laser at a dose of 10 ¹⁴ / cm ² or more, and then laser heat treatment is performed under the condition that the recrystallized or crystallized Si layer does not melt. A method for manufacturing a three-dimensional semiconductor device is proposed. Furthermore, instead of laser heating after hydrogen ion addition, it was also proposed to perform RTA (Rapid Thermal Processing) at a temperature of 900 ° C or lower.

In the prior application, the CLC method was considered as follows. That is, the laser scanning speed at which mobility (cm ² / Vs) superior to ELC is obtained by the CLC method is in the range of 20 to 100 cm / s (Non-Patent Document 10, FIG. 7). This speed is equal to the solid-liquid interface moving speed (V _L ), and the pulling speed (V _c ) in the Si single crystal pulling method is about 1 to 2 mm / min, and again the solid-liquid interface moving speed (V _c ) Is equal to the lifting speed. When these ratios are calculated, V _L = 100 to 1000 V _c and there is a difference of 10 ² to 10 ³ times. In Figure 7 above, when the laser scanning is faster, the mobility (cm / Vs) is no different from that of ELC. The solid-liquid interface movement speed (V _L ) cannot follow the very fast laser scanning speed. Nucleation occurs at the SiO ₂ / Si interface.

Further, in the prior application, when the thin film Si is recrystallized by the CLC method under the condition that the solid-liquid interface moving speed V _L is high (that is, V _L >> V _c ), it is positioned on the solid side with the solid-liquid interface as a boundary. It is considered that the Si crystal that moves away from the heat source, that is, the melting spot by the laser, rapidly cools down, so that the crystal distortion and the like are thought to increase even if crystal defects are not reached.

The present inventors paid attention to the fact that defects generated by the CLC method have the following features.
(A) Defects extend in the Si crystal in the laser scanning direction, that is, in a direction substantially along the moving direction of the solid-liquid interface.
(B) Defect generation status, particularly frequency, is affected by the surface condition of the underlying SiO ₂ layer. That is, in the Si layer at a position close to the underlying SiO ₂ film, the occurrence of defects is affected by the roughness of the underlying layer.
(C) Almost all defects disappear when they grow to some extent. That is, one linear defect does not extend the entire length in the laser scanning direction. This can be analyzed as follows. Defects occur at the solid-liquid interface where the phase change occurs, and there are some sorts of defects at the solid-liquid interface. As the solid-liquid interface moves with laser scanning, linear defects extend from the defect seed into the (re) crystallized Si. When the defects extend to some extent, they disappear and a complete Si crystal is obtained.
(D) When two defects intersect, they merge into one and then disappear.
(E) As described in (a) and (b) above, the defect extends and no loop is formed.

  Among the features of the defects described above, once a defect has occurred, the energy of the defect can be said to be very small. In addition, Si atoms sandwiching linear defects are easily moved by the heat of the Si layer, and try to form a complete crystal. At this time, since the energy of the defect is very small, the Si atoms that attempt to form a complete crystal exceed the energy of the defect, and the defect disappears, that is, forms a complete crystal without being repaired. Since this phenomenon is annealing due to the heat of Si itself, it can be called self-annealing.

  As described above, the energy of defects generated by the CLC method is very small, but considerable defects remain in the (re) crystallized Si layer, and thus the (re) crystallized Si having defects The characteristics are insufficient for use in IC devices such as arithmetic devices and storage devices. However, since the Si layer itself has sufficient energy for self-annealing, the application of laser energy auxiliary immediately after CLC crystallization can promote the disappearance of defects.

That is, the present invention forms an insulating film on a Si layer on which a circuit of a semiconductor element is formed, laminates a polycrystalline Si layer or an amorphous Si layer on the insulating film, and the polycrystalline Si layer or By irradiating and scanning an amorphous Si layer with a hydrogen content of 1 atom% or less, a circuit of another semiconductor element is formed in the recrystallized or crystallized Si layer, and these circuits are connected. In the method of manufacturing a three-dimensional semiconductor device, the insulating film is flattened by CMP at least on a portion where a circuit element is formed, and then the polycrystalline Si layer or the amorphous Si layer is laminated, Laser irradiation and scanning for recrystallizing or crystallizing the Si layer are performed by a solid continuous wave laser having an energy of 10 J / cm ² or more per irradiation area, and the recrystallization or scanning is performed immediately after the solid continuous wave laser irradiation and scanning. The crystallized Si layer is A process for producing a three-dimensional semiconductor device, characterized by Aniru. Next, features of the present invention will be described.

  The starting material of the three-dimensional semiconductor device manufacturing method is a Si layer in which a circuit of a semiconductor element is formed, for example, a circuit in which elements such as a transistor, a resistor, a capacitor, a diode, and a conductance are electrically connected is formed. Single crystal (100) oriented Si substrate. This Si substrate may be a known SOI (Silicon on Insulator) substrate. Circuits formed on single-crystal Si substrates have excellent electrical characteristics, but high electrical characteristics are not required. For switch circuits, load circuits, etc., amorphous Si layers or polycrystalline A Si layer or the like may be used as a starting material. Furthermore, an Si layer recrystallized by a solid-state continuous wave laser proposed in Japanese Patent Application No. 2006-18658 filed on Jan. 27, 2006 by one of the present applicants may be used. . The key points of this method are as quoted in the next three paragraphs 0052-0054.

Method 1: Thickness of a polycrystalline Si layer or an amorphous Si layer having a hydrogen concentration of 1% by mass or less (hereinafter referred to as “Si layer”) on a substrate having at least a surface made of SiO ₂ The polycrystalline Si layer is recrystallized by scanning a solid-state continuous wave laser with an energy of 10 J / cm ² or more per area irradiated with a laser beam spot. The amorphous Si layer is crystallized, and then the surface of the Si layer scanned by the solid-state continuous wave laser is subjected to a CMP (chemical mechanical polishing) treatment on at least a portion on which a circuit element is formed, A method for producing an SOI wafer, wherein the heat treatment is performed in a temperature range of 800 to 1200 ° C. in a hydrogen atmosphere.

Second method: An amorphous Si layer having a hydrogen concentration of 1% by mass or less and a thickness of 1 to 10 μm is formed on a substrate having at least a surface made of SiO ₂ , and the layer is formed on the amorphous Si layer. The surface of the amorphous Si layer is crystallized by irradiating and scanning with a solid continuous wave laser at an energy of 10 J / cm ² or more per surface area of the amorphous silicon, and then the amorphous that is not crystallized with the SiO ₂ film Crystallized Si is grown inside the amorphous Si layer by heat treatment at 800 to 1200 ° C. in a state where the hydrogen concentration at the interface with the porous layer is 0.1% by mass or more. SOI wafer manufacturing method.

The starting material of the SOI wafer in the first and second methods is obtained by forming a SiO ₂ film by a known method such as thermal oxidation on a single crystal Si wafer on which no device such as a transistor is formed. Instead of this single crystal Si wafer, a Si substrate in which the orientation generated in the upper part or the lower part of the ingot is disturbed by the Si pulling method may be used. Such a substrate is used as a dummy wafer and does not become a product, but can be used as a starting material in the present invention. A polycrystalline Si substrate or the like can also be used. The thickness of the SiO ₂ film needs to sufficiently fulfill the insulating function. On the other hand, when the SiO ₂ layer is thick, the difference in thermal expansion between the upper and lower layers during CLC processing or in the device manufacturing process becomes a problem, and therefore it is preferably 4000 nm or less.
In addition, a synthetic quartz (SiO ₂ ) substrate can be used. Quartz substrates have recently been developed by the melting method using silica sand as a raw material, and high-purity substrates that can be used as IC substrates are also commercially available. Also, graphite, SiC, sapphire, etc. can be used with a SiO ₂ film deposited on the surface by CVD.

Subsequently, in the present invention, SiO ₂ , SiN, Si ₃ N ₄ , SiON or the like is formed by a known method on the Si layer where the circuit of the semiconductor element is formed. In the following description, an example of forming a SiO ₂ film generally used as a gate insulating film of a MOSFET will be specifically described. The SiO ₂ film forming method is roughly classified into a thermal oxidation method, a CVD method and a high pressure oxidation method. The thermal oxidation layer is a method of oxidizing the bulk of the Si layer with oxygen gas containing moisture. Currently, the condition of 800 ° C for 30 minutes is used to manufacture devices with a pattern rule of 90 nm. The quality of the SiO ₂ film formed by the thermal oxidation method is excellent. The CVD method is a method in which SiH ₄ or Si ₂ H ₆ is used as a source gas and is oxidized by O ₂ , CO ₂ , N ₂ O, etc., and is performed at a lower temperature than the thermal oxidation method, and the quality is poor. The high pressure oxidation method can form an oxide film having a thickness of 10 nm (100 Å) even at a low temperature of about 500 ° C.

The function of the insulating film is to (1) electrically insulate the lower layer from the upper layer by the element; (b) the gate oxide film of the MOS transistor, the thickness is about 10 nm (100 angstroms); (c) the flash memory Gate oxide film; (d) Cover film of LDD (Light Dosed Drain) that increases the breakdown voltage of the MOSFET. Others are (e) an insulating film of flash memory. Flash memory is expected to be used for a long period of about 10 years, during which hot electrons are repeatedly injected from the gate oxide film. The thickness of the gate oxide film is currently about 10 nm (100 angstroms), but it is predicted that it will be reduced to 7 nm (70 angstroms) due to future miniaturization.
As a method for improving the function of the insulating film, the method of Patent Document 8 has been proposed, but it involves a change in the material of the insulating film. However, even in three-dimensional device in the two-dimensional device, after forming a thickness 10~500nm in _{SiO 2, SiN, Si 3 N} 4, SiON known method a film of known materials, such as, gas lasers, excimer lasers By heating at a temperature below the melting point with a solid laser or the like, densification can be achieved and film quality and pressure resistance can be improved.

Next, either polycrystalline or amorphous Si is formed on the SiO ₂ film. These Si layer growth methods are known per se. These examples will be described.
(B) Amorphous Si
It can be grown at a temperature of 250 to 350 ° C. by plasma CVD using SiH ₄ as a source gas. The amorphous Si layer formed by the plasma CVD method contains a large amount of hydrogen of 15 to 10 atomic% corresponding to the above temperature range. Hydrogen can be reduced to 0.1-1 mass% or less by heating to a temperature below the crystallization temperature of 500-600 ° C. Furthermore, amorphous Si can grow a film having a very low hydrogen content by sputtering or vapor deposition. Further, an amorphous Si layer can be grown by a low pressure CVD method using disilane as a source gas at 400 to 500 ° C. or monosilane as a source gas at 550 ° C. to 630 ° C.
(B) Polycrystalline Si
Polycrystalline Si can be formed on the SiO ₂ film by LP-CVD at 540 to 620 ° C. using SiH ₄ and Si ₂ H ₆ as source gases. In addition, amorphous Si formed by the plasma CVD method described in the previous section (a) and having a hydrogen concentration of less than 0.1 atomic% may be heated to 600 ° C. for 18 to 20 hours to form polycrystalline Si. it can.

As described above, in the method of Non-Patent Document 10, the CLC-treated Si layer has a so-called crystal grain boundary, and thus belongs to a polycrystalline material in a broad sense. In the method of the present invention, the polycrystalline Si laminated on the SiO ₂ film is different from the polycrystalline structure in which the grain boundary in Non-Patent Document 10 extends in the laser scanning direction and the plane direction is aligned. Has granular crystal grains to be formed.

Subsequently, the amorphous Si layer is crystallized or the polycrystalline Si layer is recrystallized by laser irradiation.
A circuit element and a conductor for connecting these are formed on the (re) crystallized Si layer by a known method, and the circuit is connected to the circuit formed in the lower Si single crystal substrate described above. A three-dimensional semiconductor device is fabricated by forming a conductor. Subsequently, CMP processing and solid-state continuous wave laser irradiation, which are features of the present invention, will be described.

The SiO ₂ film described in paragraphs 0055 and 0056 has fine irregularities. In the present invention, before the laser irradiation, the SiO ₂ film is planarized to a roughness of about 0.3 to ₁ nm by CMP to reduce microscopic irregularities at the interface with the Si layer. As a result, generation of crystal grain boundaries during laser irradiation is suppressed. The CMP process may be performed on the second layer circuit element, for example, the first layer SiO ₂ which is the base of the portion where the transistor is formed, at the stage of forming the second layer. . However, CMP processing can be performed on a wafer on which a scribe line or the like is set, except for the scribe line. Various methods and apparatuses described in Non-Patent Document 16 can be used for CMP.

The recrystallization of Si by solid-state continuous wave laser irradiation and lateral scanning performed in the present invention is a CLC method as described in Citations 1 to 9 described in Non-Patent Document 10. Also, solid-state continuous wave lasers with an output of 10 to 15 W and a wavelength of 532 nm are currently provided. With this output, if the thickness of the amorphous Si layer irradiated with the solid-state continuous wave laser exceeds 500 nm (5000 angstroms), the entire layer cannot be crystallized by the solid-liquid interface movement, and the underlying SiO ₂ film Since nucleation occurs at the interface, the thickness of these layers needs to be 500 nm or less. In the description of the present specification, “crystallization” corresponds to amorphous Si, and in the case of polycrystalline Si, recrystallization occurs by laser irradiation. These are described in terms of “crystallization”. ing. Laser irradiation is preferably performed in an atmosphere of nitrogen gas or argon gas.

Furthermore, if the hydrogen content of the amorphous Si layer exceeds 1% by mass, peeling occurs during laser irradiation, so that the hydrogen content of the amorphous Si layer needs to be suppressed to 1% by mass or less. Next, the laser energy was set to 10 J / cm ² or more because below this energy, the grain boundary detected by Secco etching becomes granular.

The matter related to the thickness of the crystallized Si layer will be described.
(A) The thickness of the Si layer forming the SOI-IC circuit element is generally 20 to 70 nm. Currently, devices are made on the Si crystal obtained by the pull-up method, so there is no problem in forming the Si layer with the above thickness. However, when using a Si crystal prepared by the CLC method, an amorphous Si layer having the above thickness is formed, or a thicker amorphous Si or polycrystalline Si layer (hereinafter referred to as this paragraph and In the next paragraph, it is abbreviated as “Amorphous Si layer”, and then the choice is made between thinning by polishing or making the device only on top.
(B) If the thickness of the amorphous Si layer is very thin, CLC-crystallized amorphous Si layer is, for example, 10 nm or less under the condition that CMP is not applied to the underlying SiO ₂ film. Under the influence of the underlying SiO ₂ film, the desired (100) is increased instead of the desired (100), while the amorphous Si layer with a thickness of 200-400 nm is approximately lower on the lower side after CLC crystallization. Except for 10 nm, the orientation is almost (100). Therefore, when making a device with an extremely thin Si layer, or when making a device with a deep active region in a Si layer with a certain thickness, crystals other than (100) existing at the interface are used. It is necessary to reduce it.
(C) Some devices require high mobility depending on the type of device, while others do not, such as an SRAM load transistor described later. The requirement for crystallinity is naturally severe for the former, and the latter is relatively loose. Therefore, it is possible to form a thin amorphous Si layer and then improve the crystallinity by hydrogenation or the like.

In consideration of the above items (a) to (c), the present invention has the following amorphous Si layer thickness setting mode.
(a) An amorphous Si layer having a thickness of 100 to 200 nm is formed, a series of treatments of the present invention are performed, and then CMP is performed to obtain the above-described thickness of 20 to 70 nm. This is to reduce the influence of the interface as much as possible, although the crystallinity of the Si layer at the SiO ₂ film interface is improved by self-annealing + laser annealing.
(b) An amorphous Si layer having a thickness of 20 to 70 nm is formed, and self annealing + laser annealing is performed. This method has the advantage of producing a device that does not require high mobility in a short process.

The greatest feature of the present invention is that laser annealing is performed immediately after laser crystallization without adding hydrogen to the laser heating after hydrogenation treatment proposed in the prior application. Laser annealing is a treatment that promotes self-annealing in the present invention.
The laser for laser annealing may be either a continuous wave or a pulse, the wavelength is not particularly limited, and the output is not particularly limited, but is preferably in the range of 0.2 to 0.5 J / cm ² per surface.

If the laser for crystallization is fixed and the Si wafer is mounted on a movable stage, the laser for annealing is also fixed, while the laser moving type for crystallization is for laser annealing. The laser is also mobile. Laser crystallization and laser annealing will be described with reference to FIG. In the figure, 50 is the underlying SiO ₂ film, 52 is the Si layer, 53 is an amorphous Si layer that is not yet crystallized, 54 is crystallized single crystal Si, and 55 is a solid-liquid interface.

Referring to FIG. 4, the generation and growth of defects that occur during CLC crystallization will be described. The laser beam for crystallization actually has a width, but is indicated by a line with L. Since the laser scanning direction is the left direction in the drawing, the solid-liquid interface existed on the right side of the illustrated position at the time ₍₁₎ before the time illustrated in FIG. A defect 56 is generated at this specific time, and the defect 56a is not continuous with the solid-liquid interface 55 at the time shown in FIG. Meanwhile, the time point ₍₁₎ later than, the time point ₍₂₎ after the time point shown in FIG. 4, defects 56b is generated at the solid-liquid interface, a solid-liquid interface of the current shown in Fig. 4 55 Is continuous. Therefore, at the time shown in FIG. 4, there are still seeds that generate defects 56 b at the solid-liquid interface 55, while there are no seeds that generate defects at the solid-liquid interface 55 with respect to the defects 56 a. . On the other hand, the defect 56a itself becomes a seed and the defect tries to grow even in the region 54a. At the same time, since the single crystal Si is self-annealed, the latter action overcomes the former action. The defect 56a does not extend into the region 54a, that is, the growth has stopped. The reason why the defects generated by CLC crystallization seem to disappear is due to the fact that the defect growth is stopped as described above.

In consideration of the generation and growth of defects as described above, in the present invention, the solid-liquid interface 55 generated by laser irradiation, that is, within the single-crystal Si 54 and as close to the solid-liquid interface 55 as possible. The length of the defect 56 is made as short as possible by irradiating a laser for annealing. More specifically, the solid-liquid interface 55 is affected by the underlying SiO ₂ film, and defect seeds are generated at different places from time to time. However, since the growth of defects and the movement of Si atoms forming a complete crystal are in a competitive state from the moment when the defects are generated, defects 56 grow to some extent by laser annealing in a region where the temperature is high immediately after crystallization. Although it is unavoidable, the growth of defects can be prevented and the length thereof can be shortened. In addition, when the laser treatment after hydrogenation of the prior application is performed after the treatment of the present invention, a Si layer with very few defects can be generated.

By the way, of the defects generated by CLC crystallization, those generated on the outermost surface of 1 nm or less can be removed by chemical cleaning. On the other hand, defects generated in the deep portion of 1 to ₂ nm (10 to 20 angstroms) from the underlying SiO ₂ film in the Si layer hardly affect the device characteristics. Therefore, in particular, the defect to be processed by laser annealing is in the middle between the surface portion and the deep portion.

Laser annealing will be described in more detail with reference to FIGS. 5 to 9 showing examples of the configuration of a laser crystallization / annealing apparatus for carrying out the method of the present invention.
A substrate 62 with a Si film, which is a material for a three-dimensional device, is placed on a stage 61. A solid CW laser transmitter 63 serving as a laser beam generation source for performing crystallization and a laser oscillator 64 serving as a laser beam generation source for performing laser annealing are provided. Attenuators 65 and 67 and an optical device are provided respectively. Systems 66 and 68 are connected in series. The laser beams emitted from the laser oscillators 63 and 64 have the energy distribution shown in FIG. 6 and are concentric. This is shaped into a beam by optical systems 66 and 68 including a homogenizer. That is, the homogenizer divides the cross section of the beam into a large number and enlarges or reduces the divided beam. These shaped beam long axes are trapezoidal as shown in FIG. 7, and short axes are trapezoidal or oblique trapezoidal as shown in FIG.

  As shown in FIG. 9, the laser beam 70 for crystallization and the laser beam 71 for annealing are shaped by optical systems 66 and 68. The laser 71 is a CLC crystallized Si layer and is irradiated for annealing at a position close to the vicinity of the solid-liquid interface. When these two laser beams 70 and 71 come close to each other, the Si layer is melted in both beam regions, so that the laser beam 71 cannot perform the intended annealing. On the other hand, if the two laser beams 70 and 71 are too far apart, the defect once generated disappears only by the effect of self-annealing of the Si crystal, so that the effect of laser annealing is lost. Considering these points, the distance between the laser beams 70 and 71 is preferably 0.02 to 0.1 μm. Two or more laser beams 71 can be arranged in the laser scanning direction.

When the Si layer treated by the above-described method is subjected to CMP treatment and then epitaxial growth is performed by CVD (Chemical Vapor Deposition), a Si layer with better crystallinity can be obtained. Epitaxial growth can be performed by a known method after hydrogen termination treatment of the underlying Si layer with hydrofluoric acid or the like, but at a temperature of 450 to 800 ° C., SiH ₄ , Si ₂ H ₆ gas and carrier gas are cooled at a low temperature. It is preferable to carry out by epitaxial growth. The lower the epitaxial growth within this temperature range and the higher the degree of vacuum, the better the crystallinity of the epitaxial layer, and it is possible to grow a crystal having almost no grain boundary defects detected by the underlying Secco etch. A transistor or the like is formed in the epitaxial layer thus formed. The thickness of the epitaxial layer for adjusting the thickness of the Si single crystal layer is preferably 10 to 10,000 nm.

Although the present invention can manufacture a three-dimensional semiconductor device of any IC circuit, an embodiment in which the 6-transistor complete CMOS-SRAM shown in FIG. Show.
In FIG. 10, Q1 and Q2 are drive transistors (NMOS), Q3 and Q4 are load transistors (PMOS), and these Q1, Q2, Q3, and Q4 constitute a flip-flop. Q5 and Q6 are selection transistors (NMOS). If the bit line (D) is set to H with these gates open, the bit line (D bar) is L, that is, A is 1 and B is 0. Done. If H and L are reversed, A becomes 0 and B becomes 1. Reading is performed by setting the word line (W) to H and opening the gates of Q5 and Q6.

In a normal two-dimensional device, six transistors are formed and arranged on a Si substrate.
In the present application, the three transistors Q1, Q3, Q5 or Q2, Q4, Q6 are arranged in a three-layer arrangement, so that the area occupied by the SRAM can be reduced as compared with the prior art. In the embodiment shown in FIGS. 8 and 9, Q1 is configured as the first layer level, Q3 is configured as the second level, and Q5 connected to the word line is configured as the third layer level. The configurations of Q2, Q4, and Q6 are the same.

11 and 12, the first to third layers are shown as L1, L2, and L3, respectively. Reference numeral 10 denotes a p-type (100) Si substrate, which includes a source 12, a drain 11 and a channel between them, a gate insulating film (SiO ₂ ) 13 formed by a thermal oxidation method, and an N ⁺ polysilicon electrode 14. MOS transistor (Q1) is isolated by an insulating region 15 made of SiO _2. The insulating region 15 is formed by a shallow touch isolation technique.
The insulating film that separates the transistor Q1 and the one transistor Q3 of the CMOS formed above the transistor Q1 is formed thick as a SiO ₂ layer 17 by CVD.

An upper surface 17a of the SiO ₂ layer 17 is flattened by CMP, and an amorphous or polycrystalline Si layer is formed thereon, CLC crystallization by a solid continuous wave laser, hydrogen treatment, and heat treatment by laser such as excimer. A Si layer 20 (hereinafter referred to as “laser crystallized Si layer”) is formed through a series of processes such as the above. The laser crystallized Si layer 20 is once formed entirely and patterned after a series of treatments. 21 is a channel region, 22 is a p-type source, and 23 is a p-type drain. 24 is a gate insulating film, 25 is a gate electrode of p + type polycrystalline Si, 26 is a second-layer CVD-SiO ₂ for element separation of upper and lower layers and the same level layer, and its upper surface 26a is flattened, A state in which a third laser-crystallized Si layer 32 is formed thereon is shown.

After the formation of the first layer and the second layer, the aluminum wiring 27 for connecting the source of Q1 and the drain of Q3, and the aluminum wiring 28 for connecting Q1 and Q5 (not shown in FIG. 11) are connected to the SiO ₂ layer 17, It is formed by opening 26 windows and depositing aluminum. An N ⁺ buried layer 30 is provided at the tip of the aluminum wiring 27 in order to reduce the resistance. 29 is an aluminum wiring for connecting Q3 to the power supply line (V _DD ).
FIG. 7 shows a state in which the aluminum wirings 27 to 32 are formed and the layer 35 is formed by CVD on the third layer of SiO ₂ . Wirings 27-32 will require W, W-Si, Co, Co-Si, etc. as devices become smaller.

FIG. 12 is a cross-sectional view taken along the line AA ′ of FIG. 11, and particularly shows the structure of the transistor Q5 formed in the third layer L3. As described above, Q5 is formed in the laser-crystallized Si layer 32, and has a source 35, a drain 36, a channel 37, a gate insulating film (SiO ₂ ) 38, and a gate electrode 39. Reference numeral 41 denotes an aluminum electrode and wiring connected to the source 35 of Q3, and is connected to the bit line. An aluminum electrode 42 is connected to the drain 38 of Q3 and is connected to Q1 and Q3. Since the illustrated SRAM has a three-layer structure, the upper surface of the uppermost CVD-SiO ₂ layer 35 reflects the unevenness of the electrodes and is not flattened. 45 is a moisture-proof film and 43 is a pad portion. In order to increase the speed of semiconductor devices, it is effective to shorten the wiring and reduce the stray capacitance. For this purpose, as shown in the wirings of FIGS.

  As described above with reference to FIGS. 11 to 12, according to the present invention, not only can the area of the SRAM be reduced, but also the first and second layers are laminated with flat layers. A continuous thin film can be arranged in multiple stages on each layer.

The order of the processes is as follows: (1) SiO ₂ film formation (CVD and thermal oxidation), (2) formation of an amorphous or polycrystalline Si layer, and (3) the present invention. CMP by the first and second methods, laser crystallization / hydrogen addition / heat treatment, (4) region formation by impurity doping, and (5) electrode formation are repeated for these second and third layers. Drill the last vertical metal hole.
Although the three-layer device has been described in the embodiment, it goes without saying that a device having four or more layers can be manufactured in the same manner.

As described above, the laser-crystallized Si layer formed and prepared by the method of the present invention has electrical characteristics required for current IC devices because of its good crystallinity. In the manufacturing of 3D semiconductor devices according to the present invention, a conventional SOI wafer may be used as a material, but there is no cutting or bonding process at all. Can be manufactured.
If a 90 nm mask, which is the current pattern rule, is used and a three-layer structure is used, miniaturization corresponding to the 52 nm pattern rule can be achieved. Since this 52 nm is said to be 2 to 3 years ahead, the method of the present invention can achieve miniaturization after 2 to 3 years.

It is a figure which shows the cross section of a cap layer in the nonpatent literature 6. FIG. It is a top view of Si layer which has received laser irradiation in nonpatent literature 6. 6 is a diagram illustrating a source and a drain of a transistor of Non-Patent Document 6. It is explanatory drawing of the defect which generate | occur | produces by ClC crystallization. It is a figure which shows the laser crystallization and annealing apparatus structural example. It is a figure which shows energy distribution of the beam radiate | emitted from the laser oscillator. It is a figure which shows the energy of the major axis direction of the beam shape | molded by the optical system. It is a figure which shows the energy of the short axis direction of the beam shape | molded by the optical system. It is explanatory drawing of the laser beam which performs crystallization and annealing. It is a circuit diagram of complete CMOS SRAM. FIG. 5 is a three-dimensional structure diagram of the SRAM of FIG. FIG. 8 is a cross-sectional view taken along line A-A ′ of FIG.

Explanation of symbols

10-single crystal Si substrate 17-first layer CVD-SiO ₂
26-first layer CVD-SiO ₂
13, 24, 32--crystallized Si layer (Si layer obtained by laser crystallization of amorphous or polycrystalline Si layer followed by heat treatment such as hydrogen treatment and RTA)
55-Solid-liquid interface 70-Laser beam for crystallization 71 Laser beam for annealing

Claims (2)

An insulating film is formed on a Si layer on which a circuit of a semiconductor element is formed, and a polycrystalline Si layer or an amorphous Si layer having a hydrogen content of 1 atomic% or less is stacked on the insulating film, A circuit of another semiconductor element is formed in a recrystallized or crystallized Si layer by irradiating and scanning a laser on an Si layer or an amorphous Si layer, and a three-dimensional semiconductor device for connecting these circuits. In the manufacturing method, at least a portion where a circuit element is formed on the insulating film is planarized by CMP, and then the polycrystalline Si layer or the amorphous Si layer is laminated, and the Si layer is recrystallized. Laser irradiation and scanning to crystallize or crystallize are performed by a solid continuous wave laser having an energy of 10 J / cm ² or more per irradiation area, and the recrystallized or crystallized Si layer is immediately after the solid continuous wave laser irradiation and scanning. Laser annealing A method for manufacturing a three-dimensional semiconductor device, characterized in that: 2. The method of manufacturing a three-dimensional semiconductor device according to claim 1, wherein an epitaxial Si layer is grown after CMP processing is performed on the surface of the Si layer subjected to the laser annealing treatment.