JP2007189235A - Thin film semiconductor device and display system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an LDD type thin film semiconductor device capable of a high-speed operation without adding new process steps, and to provide a manufacturing method of the thin film semiconductor device and a display system. <P>SOLUTION: In the thin film semiconductor device including a non-single crystalline semiconductor film that is formed on an insulating substance of a substrate with the insulating substance at least in a part of a surface, the semiconductor film comprises: first impurity semiconductor films (3 and 4) arranged at a source section and a drain section of the thin film transistor; and a second impurity semiconductor film (9) of high resistance arranged at least either between the drain section and the channel section of the thin film transistor or between the source section and the channel section. In the case of expressing an LDD length at the drain section as Llddd and a distance between the edge side on the channel section side of the contact hole at the drain section to the gate electrode as Lcontd, they are in such a relationship that 0.8×Llddd≤Lcontd≤1.2×Llddd. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a thin film semiconductor device including a non-single-crystal semiconductor film, a manufacturing method thereof, and a display system using the thin film semiconductor device.

  In recent years, thin film semiconductor devices including non-single-crystal (including polycrystalline and amorphous) semiconductor films are often used for display portions and peripheral circuits of active matrix liquid crystal display devices. It is also used in image sensors and SRAMs. The thin film semiconductor device here is a generic term for a semiconductor film itself, a thin film transistor (TFT), or a CMOS type TFT having a p-channel TFT and an n-channel TFT. It will be called a thin film semiconductor device or a TFT.

  When a thin film semiconductor device is used for a peripheral circuit of a liquid crystal display device, for example, high speed operation is required. This is because if the peripheral circuit can be operated by a high-speed thin film semiconductor device, not only the thin film semiconductor device of the display unit but also a peripheral circuit composed of a shift register, an analog switch, etc. can be integrally formed on the liquid crystal substrate. It is.

  In addition, if the speed of the thin film semiconductor device can be increased, the usage application of the thin film semiconductor device can be greatly expanded as compared with the conventional case. That is, conventionally, the use of such a thin film semiconductor device is limited to a liquid crystal display device and has not been used for a digital circuit / analog circuit in which a single crystal MOSFET is used. This is because a thin film semiconductor device has a low mobility and a low speed compared to a single crystal MOSFET. However, if the speed of the thin film semiconductor device can be increased and it can be operated at the same speed as that of the single crystal MOSFET, a digital circuit / analog circuit that has conventionally only used the single crystal MOSFET is designed using the thin film semiconductor device. It becomes possible to do. Unlike the single crystal MOSFET, the thin film semiconductor device is formed on an insulating material. For this reason, there is no problem with conventional single crystal MOSFETs in which noise is transmitted through the substrate or latch-up occurs due to current through the substrate. Also in the above sense, increasing the speed of the thin film semiconductor device is a major technical problem.

In order to increase the speed of the thin film semiconductor device, the following problems must be solved. For example, FIG. 56A shows an example of the structure of a thin film semiconductor device, and FIG. 56B shows an equivalent circuit diagram of the thin film semiconductor device. In FIG. 56B, Rc1 and Rc2 are contact resistances in the contact portion 412 (contact between the wiring 408 and the source portion 404) and the contact portion 414 (contact between the wiring 410 and the drain portion 406), respectively. It is. Rs is the source resistance of the source portion 404, Rch is the channel resistance of the channel portion 402, and Rd is the drain resistance of the drain portion 406. In order to increase the speed of the thin film semiconductor device, first, it is necessary to reduce the series resistance values of these resistors Rc1, Rs, Rch, Rd, and Rc2 when the transistor is in the ON state. Here, when the total resistance when the transistor is in the on state is described as Ron, Ron is the sum of the channel resistance Rch (on) in the on state and other all parasitic resistances Rp. That is,
Ron = Rch (on) + Rp
= Rch (on) + (Rc1 + Rs + Rd + Rc2)
It becomes. Therefore, in order to increase the speed of the thin film semiconductor device, it is desirable to reduce both the channel resistance Rch (on) in the on state and the total parasitic resistance Rp. In order to reduce Rch (on), it is necessary to devise a manufacturing process of a semiconductor film constituting the thin film semiconductor device. Specifically, the mobility of the semiconductor film may be increased. It is also effective to shorten the channel portion 402. In order to reduce Rs and Rd, the impurity concentration of the source and drain portions may be increased or the quality of the semiconductor film forming the source / drain portions may be increased. In order to reduce Rc1 and Rc2, a method of using a barrier metal or the like can be considered. However, a method of increasing the impurity concentration of the source part and the drain part is effective for simplifying the manufacturing process.

In order to increase the mobility of the semiconductor film, it is desirable to employ a polycrystalline silicon (polysilicon) thin film semiconductor device. This is because the polycrystalline silicon thin film semiconductor device usually has a mobility of about 10 cm ² / v · sec or more, and the mobility is much higher than the amorphous silicon (amorphous silicon) thin film semiconductor device.

Conventionally, as a method for manufacturing such a polycrystalline silicon thin film semiconductor device, for example, the following three manufacturing methods are known. In the first manufacturing method, first, a polycrystalline silicon film is deposited by LPCVD at a deposition temperature of about 600 ° C. or higher. At this time, the size of the region (island) constituting the polycrystalline silicon is in the range of about 20 nm to 80 nm. Thereafter, the surface of the polycrystalline silicon film is thermally oxidized to form a semiconductor layer and a gate insulating layer of the thin film semiconductor device. At this time, the interface roughness (centerline average roughness Ra) between the gate insulating film and the gate electrode is about 3.1 nm or more. In this case, for example, in the case of n-channel type thin film semiconductor device, the mobility becomes ^{10cm 2 / v · sec~20cm 2 /} v · sec approximately. In addition, the average grain area (average grain area) of the semiconductor film thus obtained is about 4000 to 6000 nm ² .

In the second manufacturing method, first, an amorphous silicon film is deposited by a plasma CVD method (PECVD method). Thereafter, heat treatment is performed in a nitrogen atmosphere at 600 ° C. for about 20 to 80 hours, thereby changing the amorphous silicon film into a polycrystalline silicon film (solid phase growth method). Thereafter, the surface of the polycrystalline silicon film is thermally oxidized to form a semiconductor layer and a gate insulating layer of the thin film semiconductor device. Then, after the thin film semiconductor device is completed, hydrogen plasma irradiation is performed. In this case, the mobility is approximately 150 cm ² / v · sec in the case of an n-channel thin film semiconductor device [S. Takenaka et. al, Jpn J. et al. Appl. Phys. 29, L2380, (1990)].

In the third manufacturing method, first, a polycrystalline silicon film is deposited at a deposition temperature of 610 ° C. by LPCVD. Then, Si ⁺ having a dose of about 1.5 × 10 ¹⁵ cm ⁻² is implanted into the polycrystalline silicon film, thereby changing the silicon film to an amorphous film. Thereafter, heat treatment is performed for several tens of hours to several hundred hours in a nitrogen atmosphere at 600 ° C., and the amorphous is recrystallized to obtain a polycrystalline silicon film. Next, the surface of the polycrystalline silicon film is thermally oxidized to form a semiconductor layer and a gate insulating layer of the thin film semiconductor device. Then, after the thin film semiconductor device is completed, a silicon hydride natriide (p-SiN: H) film is deposited by a plasma CVD method, followed by a heat treatment at 400 ° C. to perform a hydrogenation treatment. In this case, the mobility is about 100 cm ² / v · sec in the case of an n-channel thin film semiconductor device [T. Noguchi et al. al, J. et al. Electrochem. Soc. 134, 1771 (1987)]
However, various problems are inherent in the first to third manufacturing methods described above. In the second manufacturing method, ie, a manufacturing method in which an amorphous silicon film is deposited and then subjected to heat treatment for several tens of hours, a thin film semiconductor device with high mobility can be obtained, but the process is remarkably long and the productivity is avoided. I don't get it. In the second manufacturing method, the initial semiconductor film is deposited by the PECVD method, so that fine particles are generated in the reaction furnace, adhere to the substrate and become defects, and the yield decreases. A third manufacturing method, that is, a manufacturing method in which silicon atoms are implanted after depositing a polycrystalline silicon film and heat treatment is performed for several tens of hours to several hundreds of hours is the same as the second manufacturing method described above. In comparison, the process is longer and complicated. Further, if one process is added, it alone causes a decrease in product yield. Furthermore, performing heat treatment for several tens of hours to several hundred hours is impractical from the standpoint of mass production and is not practical.

On the other hand, the first manufacturing method, that is, a method of manufacturing a thin film semiconductor device by simply depositing a polycrystalline silicon film by LPCVD and then thermally oxidizing it is rich in mass productivity and stability in a very simple process. . However, as described above, in the first manufacturing method, the average grain area of the polycrystal constituting the semiconductor film is as small as about 4000 to 6000 nm ² and the mobility is also 10 cm ² / v · sec to ²⁰ cm ² / v ·. There was a problem of being small and sec.

Next, the contact resistance Rc, and the reduction in resistance of Rs and Rd will be considered. The TFT includes a TFT having a normal structure and a lightly doped drain (hereinafter abbreviated as LDD) type TFT. In order to reduce the total parasitic resistance Rp formed by the sum of Rc1, Rc2, Rs, and Rd, the present inventor further proceeds to reduce the total resistance Ron in the ON state by using LDD. It is considered most desirable to adopt a type TFT. First, the structure and manufacturing method of a TFT having a normal structure will be briefly described with reference to FIG. In this manufacturing method, first, a gate insulating film 25 is formed on an insulating substrate 21 on a semiconductor thin film 22 patterned in an island shape, and a gate electrode 26 is formed thereon. Next, an impurity serving as a donor is implanted at a high concentration into the semiconductor thin film of the source / drain portion of the n-channel TFT to form the n ⁺ semiconductor thin film 23. Similarly, an impurity serving as an acceptor is implanted at a high concentration into the semiconductor thin film of the source / drain portion of the p-channel TFT to form the p ⁺ semiconductor thin film 24. Although this method becomes self-aligned type TFT for implanting impurities using the gate electrode as a mask, non by forming an island shape the n ⁺ semiconductor thin film or a p ⁺ semiconductor thin film containing a pre impurities in the source and drain portions A self-aligned TFT can also be used. If these TFTs are covered with an interlayer insulating film 27 and wiring is patterned with a metal thin film 28, a TFT having a normal structure is completed.

  In a semiconductor integrated circuit using a single crystal substrate, a single crystal MOSFET having an LDD structure is widely used. This is because with the LDD structure, generation of photocarriers can be suppressed and reliability can be improved. As conventional techniques of LDD type MOSFETs, there are, for example, Japanese Patent Laid-Open Nos. 02-058274 and 02-045972. Further, as conventional techniques for manufacturing LDD type MOSFETs, there are JP-A-62-1241375 and JP-A-62-2234372. Since a single crystal semiconductor has a small diffusion coefficient, the LDD length can be reduced to about one-tenth of the channel length. Therefore, the on-state current of the LDD type MOSFET is reduced only by about 10% compared to the MOSFET having the normal structure. However, in a TFT using a non-single-crystal semiconductor thin film, accelerated diffusion occurs along the crystal grain boundary, so that the substantial diffusion coefficient increases by an order of magnitude or more than that of the single-crystal semiconductor. Therefore, in the LDD type TFT, the LDD length has to be increased, and there is a problem that the on-current is less than half that of the TFT having the normal structure due to the high resistance value of the LDD portion. For this reason, conventional LDD TFTs have not been used in circuits that require high-speed operation. On the other hand, in the self-aligned TFT having the normal structure shown in FIG. 27, high-concentration impurities are implanted in the source / drain portions. For this reason, the problem of parasitic resistance is small, but there is another problem as follows, which also hinders the speeding up of the circuit. That is, there is a problem that the so-called overlap capacitance increases due to the above-described enhanced diffusion, and the device capacitance increases. For example, in FIG. 27, an overlapping portion indicated by Yjn in the n-channel TFT is a parasitic capacitance, and an overlapping portion indicated by Yjp in the p-channel is a parasitic capacitance. The n-channel effective channel length Leffn and the p-channel effective channel length Leffp are overlapped from the n-channel gate electrode length (see FIG. 27, sometimes referred to as the gate electrode width) Lgaten and the p-channel gate electrode length Lgatep, respectively. The length is obtained by subtracting twice Yjn and twice Yjp. For example, when a polysilicon TFT is taken as an example, this overlapping portion is 1 μm or more, and thus a gate electrode length of 6 μm or more is required to obtain an effective channel length of 4 μm. This means that the capacity of 1.5 times or more of the original element becomes a load, and the operation speed becomes 2/3 or less of the original speed. For the above reasons, it has not been possible to improve the operation speed of the conventional normal self-aligned TFT. Further, as described above, the conventional LDD TFT has not been used for a circuit that requires high-speed operation.

  For example, Japanese Patent Laid-Open No. 05-173179 is known as a conventional technique in which a peripheral circuit of a liquid crystal display device that requires high-speed operation is integrally formed with TFTs. A normal structure TFT is used. This is because, as described above, the conventional LDD type TFT is not suitable for high-speed operation. On the other hand, an LDD type TFT is used for the display portion. This is because the liquid crystal in the display portion is a high-resistance material, and therefore it is necessary to suppress the off-current of the pixel TFT.

Japanese Patent Laid-Open No. 6-102531 is known as a conventional technique using LDD type TFTs not only in the display portion but also in peripheral circuits. However, this conventional technology also presupposes that the LDD TFT has a low on-current. The on-current is increased by adding new process steps such as a solid phase growth method and a hydrogenation process (see the left column, lines 26 to 36, page 7 of JP-A-6-102531). In other words, this conventional technique obtains benefits such as prevention of leakage current by adopting the LDD structure, while compensating for the decrease in on-current due to the adoption of the LDD structure by adding a new process step. That is why. For example, this prior art discloses that the dose amount of impurities implanted into the LDD region is 1 × 10 ¹⁴ cm ⁻² or less (see left column, lines 45 to 48 on page 5). However, this numerical limitation is not a numerical limitation for optimizing the on / off current ratio, but merely a numerical limitation for reducing the off current and suppressing the leakage current. Therefore, in such a limitation, the off current can be reduced, but the on current cannot be increased. This is because as the dose of the impurity implanted into the LDD region is reduced, the resistance of the LDD region is increased and the on-current is reduced. Similarly, this prior art discloses that the dose amount of the impurity implanted into the source / drain region is in the range of 1 × 10 ¹⁴ to 1 × 10 ¹⁷ cm ⁻² (right column 11 on page 5). See lines 14-14). However, this numerical limitation is not a numerical limitation such as optimization of the diffusion length by accelerated diffusion and reduction of resistance of Rc, Rs, and Rd. Further, in this prior art, the channel length is 6 μm (see the left column on page 7 and lines 14 to 16), and there is no disclosure of a technique for shortening the TFT with a channel length of 5 μm or less.

As described above, in the LDD type TFT of this conventional example, the on-current cannot be increased, and the resistance of parasitic resistances such as Rc, Rs, and Rd is reduced while the diffusion length is optimized. In addition, the channel cannot be shortened. Therefore, there is a problem that it cannot be applied to a high-speed circuit unless a new process step such as a solid phase growth method is added. Therefore, an LDD type TFT that operates at high speed without adding such a new process step, or an LDD type TFT that operates at higher speed when a new process step is added is desired.
S. Takenaka et. al, Jpn J. et al. Appl. Phys. 29, L2380, (1990) T.A. Noguchi et al. al, J. et al. Electrochem. Soc. 134, 1771 (1987)

  The present invention has been made to solve the technical problems as described above, and an object of the present invention is to provide an LDD type thin film semiconductor device capable of high-speed operation without adding a new process step. And a manufacturing method of the thin film semiconductor device and a display system using the thin film semiconductor device.

  Another object of the present invention is to increase the speed of a thin film semiconductor device, to broaden the use of the thin film semiconductor device, and to be used for a digital circuit and an analog circuit that conventionally used a single crystal MOSFET. A semiconductor device and a method for manufacturing the thin film semiconductor device are provided.

  Another object of the present invention is to provide a thin film semiconductor device that can be manufactured by a simple and efficient process and has good characteristics, a method for manufacturing the thin film semiconductor device, and a display system using the thin film semiconductor device. It is in.

  In order to achieve the above object, the present invention provides a thin film semiconductor device including a non-single-crystal semiconductor film formed on an insulating material of a substrate, at least a part of the surface of which is an insulating material. Has a high resistance disposed in at least one of the first impurity semiconductor film disposed in the source portion and the drain portion of the thin film transistor, and between the drain portion and the channel portion of the thin film transistor and between the source portion and the channel portion. When the LDD length in the drain portion is Llddd and the distance from the end of the contact hole on the channel portion side to the gate electrode is Lcontd, the second impurity semiconductor film is 0.8 × Llddd ≦ It is characterized in that Lcontd ≦ 1.2 × Llddd.

  According to the present invention, Lcontd can be set to a value in the range of ± 20% of Llddd. As a result, the contact resistance can be prevented from greatly increasing, and the parasitic resistance based on the resistance of the LDD portion can be reduced.

  Similarly, when the LDD length in the source portion is Lldds and the distance from the edge of the contact hole on the channel portion side to the gate electrode is Lconts, 0.8 × Lldds ≦ Lconts ≦ 1.2 It is desirable to have a relationship of × Lldds.

  The present invention also provides a p-type thin film transistor having the first and second impurity semiconductor films in which the implanted impurity is p-type, and the first and second impurity semiconductors in which the implanted impurity is n-type. And an n-type thin film transistor having a film. With such a CMOS structure, low power consumption and high speed of the device can be achieved, and for example, a thin film semiconductor device optimal for use in a peripheral circuit of a liquid crystal display device can be provided.

  In this case, it is desirable that the gate electrode length of the p-type thin film transistor is smaller than the gate electrode length of the n-type thin film transistor. That is, by this, the p-type thin film transistor and the n-type thin film transistor can balance the on-current, and the circuit can be configured with the same channel width, so that a high-density circuit can be realized.

  The channel width of the n-type thin film transistor may be smaller than the channel width of the p-type thin film transistor. As a result, it is possible to further increase the speed by balancing the on-current. For example, if all the gate electrode lengths are set to the minimum dimensions of the design rule, the manufacturing process can be easily managed.

  In the above case, both the gate electrode length of the p-type thin film transistor and the gate electrode length of the n-type thin film transistor are preferably 5 μm or less. This is because further speedup can be achieved.

According to another aspect of the present invention, there is provided a method for manufacturing a thin film semiconductor device including a non-single-crystal semiconductor film formed on an insulating material of a substrate where at least a part of the surface is an insulating material. And a step of implanting impurities using a photoresist as a mask, and a dose amount of impurities implanted using the gate electrode as a mask is 1 × 10 ¹³ cm ⁻² to 1 × 10 ¹⁴ cm ⁻² The dose of impurities implanted using the photoresist as a mask is in the range of 5 × 10 ¹⁴ cm ⁻² to 1 × 10 ¹⁶ cm ⁻² .

  According to the present invention, impurity implantation can be performed with low energy and high throughput. In addition, since the LDD length can be set freely, as many LDD structures as necessary can be formed in the necessary portions, and the degree of freedom in circuit design is high. Moreover, the impurity to be implanted can be optimized.

  In this case, for example, the impurity may be implanted after the gate electrode is used as a mask and the insulating film is formed on the gate electrode surface layer portion.

  In the above case, it is desirable to include a step of forming an impurity semiconductor film in an island shape on the source and drain portions of the thin film transistor and forming an intrinsic semiconductor film on the impurity semiconductor film formed in the island shape. . As a result, the channel portion can be thinned to improve the TFT characteristics, and the source / drain portions can be thickened to reduce the contact resistance. In this method, even when the contact hole is opened by dry etching, a sufficient over-etching margin can be obtained, so that the yield is improved.

  In this case, the insulating film formed on the surface layer of the gate electrode may be formed by thermally oxidizing or anodizing the material of the gate electrode, or may be formed by a predetermined deposition method. Accordingly, a film can be formed at a low temperature and a high throughput by using a deposition method such as a chemical vapor deposition method. In addition, the insulating film can be multi-layered by these combinations to further reduce defects.

The present invention also provides a display system using a thin film semiconductor device including a non-single-crystal semiconductor film formed on the insulating material of a substrate having at least a part of the surface of the insulating material. An active matrix portion formed thereon, and a data driver portion and a scan driver portion formed on the insulating material and configured by the thin film semiconductor device, wherein the semiconductor film includes a source portion and a drain portion of a thin film transistor A first impurity semiconductor film disposed in a portion, and a high-resistance second impurity semiconductor film disposed in at least one of between a drain portion and a channel portion and between a source portion and a channel portion of the thin film transistor In addition, the maximum impurity concentration of the second impurity semiconductor film is in a range of 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ¹⁹ cm ⁻³ .

  According to the present invention, since the data driver section and the scanning driver section using the LDD type TFT are provided, high-speed operation is possible at a low voltage, and current consumption is small.

  In the present invention, the maximum impurity concentration and the LDD length of the first impurity semiconductor film can be optimized, and the channel length can be reduced.

  In the present invention, the data driver unit or the scan driver unit may include a bidirectional shift register circuit using a clocked gate. As a result, the left and right and top and bottom of the screen can be easily reversed, and the application range of the display device is expanded.

  In the present invention, the data driver unit or the scan driver unit may include a plurality of shift register circuits having different clock signal phases, and may include a gate for inputting the outputs of the plurality of shift registers. Thereby, various timing pulses can be generated at high speed. For example, it is possible to serially input a signal of an HDTV data driver, which has been impossible in the past.

  In the present invention, the data driver unit or the scan driver unit includes a level shifter circuit and a shift register circuit, and the shift register circuit can be driven at a TTL level or less. As a result, the interfaces of the external circuits are all below the TTL level, and the external circuits can be reduced in size, cost, and power consumption.

  In the present invention, the input portion of the level shifter circuit may include a p-type thin film transistor and an n-type thin film transistor connected in series. As a result, stable operation is possible even if the input / output voltage difference is large.

  In the present invention, the data driver unit includes a shift register circuit, a video line, and an analog switch, and an output of the shift register circuit is input to a gate terminal of the analog switch via a level shifter circuit or directly. Accordingly, element driving is performed in a dot sequential analog manner. As a result, a very small data driver with low power consumption can be configured, and a compact display device can be realized.

  According to the present invention, the data driver unit includes a first-stage analog latch connected to a video line, a second-stage analog latch to which an output of the first-stage analog latch is input, and the two-stage analog latch And an analog buffer connected to a signal line to which an output of the analog latch of the eye is input, and thereby element driving is performed in a line sequential analog manner. Thereby, it is possible to drive a large-size active matrix LCD.

Further, according to the present invention, the data driver unit includes n sets of first stage latches connected to n digital signal input lines and n sets of two stages to which an output of the first stage latch is input. And a decoder connected to the gate of the ²ⁿ analog switch to which the output of the second-stage latch is input, whereby element driving is performed digitally. As a result, a large-scale digital data driver using a latch and a decoder can be configured, and a multimedia display capable of interfacing with digital signals can be realized.

  The present invention also includes a video signal amplifier circuit that amplifies the video signal output from the video signal generator, and a timing controller that generates a timing signal synchronized with the video signal output from the video signal generator, The data driver unit and the scan driver unit are driven by the timing signal. Thereby, power consumption of the entire system can be suppressed, and a system suitable for portable use can be made.

  The timing controller, the data driver unit, and the scan driver unit are driven at a TTL level or less. This makes the external circuit very simple.

  Moreover, the present invention is characterized in that the timing controller is constituted by the thin film semiconductor device. As a result, the system can be further reduced in size and cost.

  According to the present invention, the video signal amplifier circuit includes a signal frequency conversion circuit or a γ correction circuit for converting the video signal into a plurality of low frequency signals. As a result, the horizontal resolution can be improved and excellent halftone display can be achieved.

  Further, the present invention is characterized in that the video signal amplifier circuit is constituted by the thin film semiconductor device. As described above, if the video signal amplifier circuit is also formed integrally with the thin film semiconductor device of the present invention, the display system can be significantly reduced in size and cost.

  The present invention also provides a thin film semiconductor device including a non-single-crystal semiconductor film formed on an insulating material of a substrate having at least a part of the surface being an insulating material, wherein the semiconductor film is a seed for film formation. The semiconductor film is deposited by a chemical vapor deposition method under the condition that the generation rate of nuclei to be reduced is reduced and the growth rate of islands generated from the nuclei is increased. A first impurity semiconductor film disposed in a portion, and a high-resistance second impurity semiconductor film disposed in at least one of between a drain portion and a channel portion and between a source portion and a channel portion of the thin film transistor It is characterized by including.

  According to the present invention, an LDD TFT circuit including a semiconductor film can be realized by generating a semiconductor film based on the principle that the generation rate of nuclei is reduced and the growth rate of islands is increased. This can improve mobility, decrease contact resistance, shorten the transistor channel, improve breakdown voltage, and the like, and can realize a high-speed thin film semiconductor device that is not inferior to that of a single crystal MOSFET. In particular, in the present invention, the island region constituting the semiconductor film is very large, and thereby there are very few crystal defects in the polycrystalline structure after the heat treatment. Therefore, the resistance of the LDD portion can be lowered, and the on-current can be further improved.

  In this case, in the present invention, the maximum impurity concentration and the LDD length of the first and second impurity semiconductor films can be optimized, and the channel length can be reduced.

In particular, when optimizing the maximum impurity concentration of the second impurity semiconductor film, the range of the maximum impurity concentration can be 2 × 10 ¹⁷ cm ⁻³ to 1 × 10 ¹⁹ cm ⁻³ , The density setting range can be widened. That is, according to the present invention, the semiconductor film is generated based on the principle that the generation rate of nuclei is reduced and the growth rate of islands is increased, so that crystal defects can be reduced and resistance in the LDD portion can be lowered. Therefore, even if the maximum impurity concentration is set low, the sheet resistance in the LDD portion does not increase so much, and therefore the lower limit value of the maximum impurity concentration can be set to a low value such as 2 × 10 ¹⁷ cm ^−3. is there.

  When the LDD length is optimized, the LDD length range can be set to 0.3 μm to 4 μm, and the setting range of the LDD length can be widened. That is, in the present invention, the semiconductor film is generated based on the principle of slowing the nucleus generation rate and increasing the island growth rate, so that the grain boundaries in the semiconductor film can be reduced, and the enhanced diffusion can be reduced. can do. Therefore, the minimum LDD length can be shortened to about 0.3 μm. Thereby, the parasitic resistance in the LDD portion can be further reduced.

  Further, the present invention is characterized in that the second impurity semiconductor film is disposed in the entire region of the source portion and the drain portion of the p-type thin film transistor in which the impurity implanted into the impurity semiconductor film is p-type. .

  That is, in the present invention, the sheet resistance in the second impurity semiconductor film into which the low concentration impurity is implanted can be reduced. Therefore, for the p-type thin film transistor, it is possible to omit the implantation of the high-concentration impurity and to configure the entire source region and drain region with the low-concentration second impurity semiconductor film. As a result, for example, the number of photo steps can be reduced by one, and the circuit can be easily integrated.

  The present invention also provides a method of manufacturing a thin film semiconductor device including a non-single-crystal semiconductor film formed on an insulating material of a substrate having at least a part of the surface as an insulating material. And a step of depositing a semiconductor film by a chemical vapor deposition method under the condition of slowing the generation rate of islands and increasing the growth rate of islands generated from the nuclei.

  According to the present invention, in the semiconductor film deposition process, the generation of nuclei and the growth of islands are in a competitive process. The island grows and the insulating material surface is covered by the island. As a result, the area of the island is increased, and for example, the area of grains generated by performing heat treatment or the like on the semiconductor film can be increased. Thereby, the mobility of the thin film semiconductor device can be increased. In addition, since the island region is enlarged, the surface of the semiconductor film becomes smooth. As described above, according to the present invention, a silicon film is simply formed by chemical vapor deposition without passing through complicated and redundant processes such as silicon ion implantation, long-time heat treatment, or hydrogenation. The characteristics of the thin film semiconductor device can be dramatically improved by an extremely simple process of forming a film. Note that the semiconductor film deposited in the present invention is not limited to amorphous, but it is not known that such an island region exists particularly in the case of an amorphous structure. For the first time, its existence was recognized by a force microscope (AFM).

  In this case, in the present invention, it is desirable that the nucleus generation rate is controlled by the deposition temperature, and the island growth rate is controlled by the deposition rate. The deposition temperature is preferably 580 ° C. or lower, and the deposition rate is preferably 6 Å / min or higher. That is, by setting the deposition temperature and the deposition rate in such ranges, the island area can be made very large. However, the generation rate of nuclei may be controlled by the type of the substrate. Further, the deposition rate can be determined by the flow rate of the source gas, the deposition pressure, and the like.

  In the present invention, the deposition temperature is desirably 550 ° C. or lower. That is, the maximum value of the average grain area can be obtained by setting the deposition temperature to 550 ° C. or lower.

  In the present invention, the deposition temperature is more preferably 530 ° C. or lower. That is, by setting the deposition temperature to 530 ° C. or less, defects in the crystal can be reduced. The lower limit of the deposition temperature can be set to 460 ° C. for monosilane and 370 ° C. for disilane, for example, depending on the type of source gas.

In the present invention, when depositing a semiconductor film by the chemical vapor deposition method, at least one of source gas, monosilane (SiH ₄ ) or disilane (Si ₂ H ₆ ), is used. May be. The basic principle of the present invention is not significantly affected by the type of source gas, and other source gases may be used.

  In addition, the present invention is characterized by including a step of thermally oxidizing the surface of the semiconductor film after the semiconductor film deposition step. By performing the thermal oxidation treatment in this manner, an oxide film can be obtained, and for example, when the semiconductor film is in an amorphous state, it can be changed to a polycrystalline state.

  In addition, the present invention includes a step of irradiating the semiconductor film with optical energy or electromagnetic energy after the step of depositing the semiconductor film, and the maximum process temperature after the irradiation step is 350 ° C. or less. It is characterized by. According to the present invention, by adopting such a low-temperature process, it is possible to use inexpensive glass as the substrate, and it is possible to prevent the substrate from being distorted by its own weight.

  In this case, the method includes a step of performing a heat treatment on the semiconductor film at a temperature of 600 ° C. or lower after the step of depositing the semiconductor film, and a maximum process temperature after the step of performing the heat treatment is 600 ° C. or lower. It is good. By combining the low temperature process and solid phase growth in this way, a higher quality semiconductor film can be obtained. In this case, it is more preferable that the maximum process temperature after the heat treatment process is 350 ° C. or less.

  In addition, the present invention is characterized by including a step of performing a heat treatment on the semiconductor film at a temperature in the range of 500 ° C. to 700 ° C. after the step of depositing the semiconductor film. According to the present invention, by performing such a heat treatment, for example, an amorphous semiconductor film can be changed to a polycrystalline state at a relatively low temperature. This makes it possible to obtain a thin film semiconductor device having better quality characteristics. In this case, a more preferable temperature range for the heat treatment is 550 ° C to 650 ° C.

According to the present invention, in the thin film semiconductor device including a non-single-crystal semiconductor film formed on the insulating material of the substrate having at least a part of the surface being an insulating material, the semiconductor film is in a polycrystalline state. In this case, the average grain area is 10,000 nm ² or more. In the present invention, since the average area of the grains is thus large, the mobility can be increased and the speed of the thin film semiconductor device can be increased.

According to another aspect of the present invention, in a thin film semiconductor device including a non-single-crystal semiconductor film formed on an insulating material of a substrate, at least a part of the surface of which is an insulating material, a nucleus serving as a seed for generating the semiconductor film The average area of the islands generated is 10,000 nm ² or more. In the present invention, since the average area of the island is thus large, the average area of the grains obtained by, for example, heat treatment can be increased, and the speed of the thin film semiconductor device can be increased. Furthermore, the present invention has an advantage that the surface of the semiconductor film becomes smooth.

  Further, the present invention provides a thin film semiconductor device including a non-single-crystal semiconductor film formed on an insulating material of a substrate having at least a part of the surface being an insulating material, and is generated by thermally oxidizing the semiconductor film The center line average roughness of the interface between the formed gate insulating film and the gate electrode formed on the gate insulating film is 2.00 nm or less. In the present invention, since the center line average roughness is 2.00 nm or less, when a gate insulating film is formed on the semiconductor film, a flat gate insulating film surface is formed, and the source-gate breakdown voltage is improved. To do. Accordingly, pixel defects and the like are reduced. Furthermore, the thermal oxidation temperature can be lowered, and both cost reduction and high-definition high-density processing can be achieved. In addition, the life of the manufacturing apparatus is extended and maintenance is facilitated.

The present invention also provides a thin film semiconductor device including a non-single-crystal semiconductor film formed on an insulating material of a substrate having at least a part of the surface being an insulating material, wherein the semiconductor film is a source portion of a thin film transistor. And a first impurity semiconductor film disposed in the drain portion and a high-impurity second impurity semiconductor film disposed in at least one of the thin film transistor between the drain portion and the channel portion and between the source portion and the channel portion. The maximum impurity concentration of the second impurity semiconductor film is in the range of 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ¹⁹ cm ⁻³ .

According to the present invention, by using the LDD structure, it is possible to shorten the channel, increase the speed, and improve the breakdown voltage of the thin film semiconductor device. In order to realize this, the maximum impurity concentration of the second impurity semiconductor film, that is, the LDD portion is optimized. That is, the breakdown voltage can be improved by setting the maximum impurity concentration to 1 × 10 ¹⁹ cm ⁻³ or less. On the other hand, by setting the maximum impurity concentration to 1 × 10 ¹⁸ cm ⁻³ or more, the sheet resistance of the LDD portion can be lowered, and a decrease in on-current can be avoided. In this case, for further optimization, it is desirable that the maximum impurity concentration be in the range of 2 × 10 ¹⁸ cm ^{−3 to} 5 × 10 ¹⁸ cm ⁻³ , thereby optimizing the ratio of on-current to off-current. Can be.

The present invention also provides a thin film semiconductor device including a non-single-crystal semiconductor film formed on an insulating material of a substrate having at least a part of the surface being an insulating material, wherein the semiconductor film is a source portion of a thin film transistor And a first impurity semiconductor film disposed in the drain portion, and a high-resistance second impurity semiconductor film disposed in at least one of the thin film transistor between the drain portion and the channel portion and between the source portion and the channel portion. The maximum impurity concentration of the first impurity semiconductor film is in the range of 5 × 10 ¹⁹ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ .

According to the present invention, the maximum impurity concentration of the first impurity semiconductor film, that is, the source / drain portion is optimized. That is, by setting the maximum impurity concentration to 1 × 10 ²¹ cm ⁻³ or less, diffusion of impurities from the source / drain portion to the LDD portion can be suppressed, and the breakdown voltage of the thin film semiconductor device can be improved. On the other hand, by setting the maximum impurity concentration to 5 × 10 ¹⁹ cm ⁻³ or more, the contact resistance or the source / drain resistance can be reduced, and the speed of the thin film semiconductor device can be increased. In this case, for further optimization, it is desirable that the maximum impurity concentration be in the range of 1 × 10 ²⁰ cm ^{−3 to} 3 × 10 ²⁰ cm ⁻³ . In addition, the device can be miniaturized.

  The present invention also provides a thin film semiconductor device including a non-single-crystal semiconductor film formed on an insulating material of a substrate having at least a part of the surface being an insulating material, wherein the semiconductor film is a source portion of a thin film transistor And a first impurity semiconductor film disposed in the drain portion, and a high-resistance second impurity semiconductor film disposed in at least one of the thin film transistor between the drain portion and the channel portion and between the source portion and the channel portion. The LDD length in the drain part or the source part is in the range of 0.6 μm to 4 μm.

  According to the present invention, the element can be miniaturized by setting the LDD length to 4 μm or less. On the other hand, by setting the LDD length to 0.6 μm or more, it is possible to prevent a situation where the effective LDD length becomes zero and the breakdown voltage decreases due to the diffusion of impurities from the source / drain portions. In this case, in order to achieve further optimization, the LDD length is desirably in the range of 1 μm to 2 μm.

  The present invention also provides a thin film semiconductor device including a non-single-crystal semiconductor film formed on an insulating material of a substrate having at least a part of the surface being an insulating material, wherein the semiconductor film is a source portion of a thin film transistor And a first impurity semiconductor film disposed in the drain portion, and a high-resistance second impurity semiconductor film disposed in at least one of the thin film transistor between the drain portion and the channel portion and between the source portion and the channel portion. The length of the gate electrode formed on the semiconductor film through the gate insulating film is 5 μm or less.

  According to the present invention, since the gate electrode length can be shortened to 5 μm or less, a decrease in on-current due to the adoption of the LDD structure can be sufficiently compensated, and the speed of the device can be increased. In this case, the gate electrode length is desirably 3 μm or less. Thus, by shortening the channel to 3 μm or less, it is possible to further increase the speed. In addition, the operating power supply voltage can be reduced.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. The first to fifth examples described below are examples in which a semiconductor film manufacturing method is devised to obtain a high-speed thin film semiconductor device.

1. First Embodiment FIGS. 1A to 1D show manufacturing process diagrams of a thin film semiconductor device according to the first embodiment. 1A to 1D show process diagrams in the case of an n-channel TFT. The present invention is applied to a p-channel TFT and a CMOS TFT having an n-channel TFT and a p-channel TFT. Is naturally applicable (see FIG. 26). Also, a structure called a so-called double gate may be used.

  In the first embodiment, quartz glass is used as the substrate 201. However, any other type and size may be used as long as the substrate can withstand the maximum temperature during the manufacturing process of the thin film semiconductor device. First, a semiconductor film such as silicon, which will eventually become an active layer, is deposited on the substrate 201. At this time, if the substrate is a conductive material such as a silicon wafer or if the substrate contains impurities such as a ceramic substrate, an underlying protective film such as a silicon dioxide film or a silicon nitride film is deposited before the semiconductor film is deposited. May be deposited (see FIG. 25).

In the first embodiment, an intrinsic silicon film is deposited on the substrate 201 by the LPCVD method. As a result, the film thickness after deposition becomes 1000 mm. The LPCVD apparatus is a hot wall type and has a volume of 184.5 l. The total reaction area after inserting the substrate is about 44000 cm ² . The deposition temperature was 510 ° C., monosilane (SiH ₄ ) having a purity of 99.99% or more was used as the source gas, and the gas was supplied to the reactor at a flow rate of 100 SCCM. In this case, the deposition pressure was 0.8 torr, and under this condition, the deposition rate of the silicon film was 21.5 Å / min. Then, the silicon film thus deposited is patterned to obtain a silicon film 202 (see FIG. 1A).

Next, a silicon oxide film 203 was formed on the surface of the silicon film 202 patterned by a thermal oxidation method. Thermal oxidation was performed at 1 atm for 23 minutes 36 seconds in a 100% oxygen atmosphere at 1160 ° C. Thus, the silicon film was thinned to 400 mm, and a silicon oxide film having a thickness of 1200 mm was obtained (see FIG. 1B). Next, in order to adjust the threshold voltage of the thin film semiconductor device, ¹¹ B ⁺ was implanted into the semiconductor film with an acceleration voltage of 40 kv and a dose of 2 × 10 ¹² / cm ² .

Next, the gate electrode 204 is formed using a silicon film containing a donor or an acceptor. In this embodiment, the gate electrode is made of polycrystalline silicon containing phosphorus and having a thickness of 3500 mm. At this time, the sheet resistance of the gate electrode was 25Ω / □. Next, using this gate electrode as a mask, impurity ions 205 serving as donors or acceptors were implanted to form a source / drain portion 206 and a channel region 207 (see FIG. 1C). In the first embodiment, phosphorus is selected as the impurity element, and the impurity is implanted at a dose of 2 × 10 ¹⁵ / cm ² at an acceleration voltage of 90 kV.

  Next, an interlayer insulating film 208 was deposited by atmospheric pressure CVD or the like. The interlayer insulating film was made of a silicon dioxide film, and the film thickness was 5000 mm. After the interlayer insulating film was deposited, a heat treatment was performed at 1000 ° C. for 20 minutes in a nitrogen atmosphere to serve as both the baking of the interlayer insulating film and the activation of the impurity element added to the source / drain portions. Next, a contact hole was opened, and wiring 209 was formed with aluminum or the like, whereby a thin film semiconductor device was completed (see FIG. 1D).

The transistor characteristics of the n-channel TFT of the thin film semiconductor device thus prepared were measured. FIG. 2 shows the measurement results. The channel length and width were both 10 μm and measured at room temperature. As a result, as shown in FIG. 2, when the source / drain voltage (Vds) is 4 v and the gate voltage (Vgs) is 10 v (when the transistor is on), the source / drain current (Ids) is 75. .6 μA. Further, when Vds = 4v and Vgs = 0v (when the transistor is in an off state), Ids was 0.203 pA. As described above, a very good thin film semiconductor device having an on / off ratio of 8 digits or more with respect to the modulation of the gate voltage 10v was obtained. The mobility obtained from the saturation region of this transistor was 106 cm ² / v · sec, which was a very good value. As described above, according to the present embodiment, a thin film semiconductor device having very excellent characteristics without performing heat treatment for a long time, by an extremely simple process of only deposition by the LPCVD method, and without performing hydrogenation treatment at all. I was able to create it.

  FIG. 2 also shows a transistor characteristic diagram of the p-channel TFT. The p-channel TFT is formed by implanting an impurity serving as an acceptor, for example, boron, when forming the source part and the drain part.

Next, the thin film semiconductor device was subjected to hydrogen plasma treatment for 2 hours to perform hydrogenation treatment. As a result, the on-current was improved to 102 μA, the off-current was 0.0318 pA, and the mobility was improved to 129 cm ² / v · sec under the same measurement conditions as described above. As shown in the first embodiment, the silicon film is deposited by the LPCVD method to the deposition conditions of the present invention, and other silicon atoms are implanted or the semiconductor is subjected to a long-time heat treatment. It has become possible to easily manufacture a high-performance thin film semiconductor device without going through a troublesome process of (re) crystallization of the film.

2. Second Example Various thin film semiconductor devices were fabricated by the LPCVD method, with the only difference being the deposition conditions of the silicon film that will become the active layer, and the other steps being the manufacturing steps detailed in the first example. However, the hydrogenation treatment was not performed in the second example. In the second example, silicon films were deposited under various conditions, and the relationship between transistor characteristics and deposition conditions was examined. The silicon film was deposited by the LPCVD apparatus detailed in the first embodiment. The source gas is monosilane having a purity of 99.99% or more. The deposition temperature of the silicon film was varied between 490 ° C and 650 ° C. Further, the deposition was carried out by appropriately setting the monosilane flow rate between 10 SCCM and 100 SCCM and the deposition pressure between 1 mtorr and 0.8 torr. Thus, various silicon films were deposited under various deposition conditions. The film thickness of the deposited silicon film was 1000 ± 50 mm for all samples. After the deposition of the silicon film, a thin film semiconductor device was created by the same manufacturing process as in the first embodiment. The thickness of the silicon film after thermal oxidation was 400 ± 50 mm for all samples, and the thickness of the silicon oxide film as the gate insulating film was 1200 ± 50 mm. If the silicon film deposition conditions change, the deposition rate also changes. Further, if the deposition conditions are changed as shown in the first embodiment, the characteristics of the obtained thin film semiconductor device are also different. Therefore, FIG. 3 shows the relationship between the mobility of the thin film semiconductor device obtained by the above-described method, the deposition temperature of the silicon film, and the deposition rate. In FIG. 3, the horizontal axis represents the silicon film deposition time, the vertical axis represents the deposition rate, and the mobility of the corresponding thin film semiconductor device is represented by a numerical value. The unit of mobility is cm ² / v · sec. A dotted line in the figure indicates a boundary line at a deposition temperature of 580 ° C. and a boundary line at a deposition rate of 6 Å / min. The condition with good characteristics is indicated by a circle so that the relationship between the deposition conditions and the transistor characteristics can be understood at a glance, and is equivalent to the thin film semiconductor device produced in the comparative example (first manufacturing method described in the background art). Is indicated by a cross. In the comparative example, the deposition temperature when the polycrystalline silicon film is deposited and thermally oxidized is about 600 ° C. or higher. All of the thin film semiconductor devices manufactured by this comparative example have a mobility of about 15 cm ² / v · sec to about 20 cm ² / v · sec. It is understood that when the deposition temperature of the silicon film is about 580 ° C. or less, the characteristics of the thin film semiconductor device obtained according to the deposition rate of the silicon film are completely different. That is, when the deposition rate is 6 Å / min or more, a thin film semiconductor device having very high characteristics can be obtained without performing hydrogenation treatment as described in detail in the first embodiment. On the other hand, when the deposition rate is less than 6 Å / min, the mobility is about 16 cm ² / v · sec to about 19 cm ² / v · sec, which is the same as the case of the comparative example. Only when a thin film semiconductor device is manufactured by depositing a silicon film under conditions where the deposition temperature is 580 ° C. or less and the deposition rate is 6 Å / min or more, a very high performance thin film semiconductor device can be obtained.

The state after thermal oxidation of the silicon film forming the active layer of the thin film semiconductor device (circle mark in FIG. 3) according to the present invention was examined with a scanning electron microscope (SEM). SEM observation was performed on the exposed polycrystalline silicon surface after the silicon oxide film was peeled off with a 10% aqueous hydrofluoric acid solution after thermal oxidation. Mean values and standard deviation of grain area. The results are shown distribution of the grain area exponential distribution, both samples showed a value between 10000 nm ² of 20000 nm ^2. As an example, an electron microscope (SEM) photograph showing a crystal structure of a silicon film of a thin film semiconductor device having a deposition temperature of 510 ° C., a deposition rate of 12.9 １２ / min, and a mobility of 82 cm ² / v · sec is shown in FIG. Moreover, the distribution of the grain area confirmed in FIG. 4 is shown in FIG. The average value of the grain area (grain size) was 15600 nm ² and the standard deviation was 15300 nm ² . In the silicon film formed in this example, a large grain having a large area of 55000 nm ² or more was recognized (see the range of 55000 to 60000 in FIG. 6A).

On the other hand, FIG. 5 shows an electron microscope (SEM) photograph showing a crystal structure of a silicon film of a thin film semiconductor device created by a comparative example (first manufacturing method) for comparison. The grain area distribution of this comparative example is shown in FIG. The samples used in FIGS. 5 and 6B are samples in which a silicon film is deposited at a deposition temperature of 600 ° C. and a deposition rate of 37.7 Å / min. FIG. 5 shows the state of the silicon film after the sample is thermally oxidized. The mobility of this sample is 20 cm ² / v · sec. The average value of the grain area of the sample is 3430Nm ^2, the standard deviation of 4210nm ^2. Not only a thin film semiconductor device prepared by depositing a silicon film at a deposition temperature of 600 ° C. or higher, but also by depositing a silicon film at a deposition rate of less than 6 μm / min even when the deposition temperature is 580 ° C. or lower. The grain area of the silicon film of the thin film semiconductor device was less than 5000 nm ² both in average value and standard deviation.

As described above, when the silicon film is deposited at a deposition temperature of 580 ° C. or less and the deposition rate is 6 Å / min or more, and the silicon film is thermally oxidized, the average value of the grain area of the polycrystalline film forming the active layer Becomes 10000 nm ² or more, which is much larger than the conventional one, and the characteristics of the thin film semiconductor device are greatly improved.

A. About the Principle of the Present Invention In the present invention, a semiconductor film having excellent characteristics is generated by depositing a semiconductor film under the conditions of slowing the nucleus generation rate and increasing the island growth rate. Hereinafter, the principle of the present invention will be described with reference to FIGS. 7 (A) to (E) and FIGS. 8 (A) to (H).

  In general, when depositing a thin film by LPCVD (low pressure chemical vapor deposition), regardless of whether the deposited film is amorphous or polycrystalline, first some nucleus (a seed or center of film growth) on the insulating material. 30 and 31 occur (FIG. 7A). The molecules constituting the gas fly from the gas phase toward the substrate. These molecules receive heat from the substrate and cause a chemical reaction, and some molecules gather to produce these nuclei. The chemical reaction formula at this time is as follows, for example, taking monosilane as an example.

SiH ₄ → Si + 2H ₂ ↑
Next, these nuclei 30 and 31 grow to become islands 34 and 35, and in the meantime, another nuclei 32 and 33 are generated in vacant regions on the substrate (FIG. 7B). These nuclei 32 and 33 also grow to become islands 36 and 37, and the other islands 34 and 35 further grow during this time (FIG. 7C). In this way, new nuclei are no longer generated when there is no more space between islands. On the other hand, when the growth of the islands 34 to 37 further proceeds, the islands and the islands are united to form a thin film 38 (FIG. 7D). Then, the thin film 38 is further grown to complete the thin film 40 having a desired film thickness (FIG. 7E). As shown in FIG. 7 (E), regardless of whether it is amorphous or polycrystalline, the thin film 40 is originally formed from regions (islands in the late deposition process) 51, 52, 53, and 54 corresponding to the islands in the early deposition process. Composed. Until all the insulating material surface is covered with the deposited film, island growth and nucleation are in a competitive process. Accordingly, if the generation rate of the nuclei is decreased and the growth rate of the islands is increased, the islands become very large. As a result, the regions (islands in the late deposition process) 51 to 54 constituting the thin film become large. This point is apparent from FIGS. 8A to 8H. FIGS. 8A to 8D show the case of the present invention, which is a case where the generation rate of nuclei is lowered and the growth rate of islands is increased. On the other hand, in the comparative examples of FIGS. 8E to 8H, the generation rate of nuclei is higher and the growth rate of islands is lower than in the present invention. Thus, for example, three nuclei are generated in FIG. 8A, whereas five nuclei are generated in FIG. 8E. In addition, the island growth rate is faster in FIG. 8B than in FIG. 8F. When the island growth rate is high, as shown in FIG. 8C, the vacant area on the substrate is further reduced, and the number of nuclei generated can be further reduced. On the other hand, in FIG. 8G, the island growth rate is slow, so that the number of vacant regions on the substrate is not so small, and the number of nuclei generated cannot be suppressed so low compared to FIG. 8C. As described above, the island is small in the comparative example (FIG. 8H), but the island grows very large in the present invention (FIG. 8D). Then, when the semiconductor film composed of the islands (regions) thus greatly grown is subjected to thermal oxidation or the like to change from the amorphous state to the polycrystalline state, it is composed of large grains as shown in FIG. A semiconductor film is formed. Here, such a region constituting the semiconductor film is generally called a grain in a polycrystalline state.

  The principle of the present invention described above can be applied not only when the deposited film is amorphous but also when it is polycrystalline. However, particularly in the case of an amorphous film, it is difficult to consider that such a region called an island exists. That is, amorphous is random with no order in the growth direction, such as single crystal and polycrystal, and therefore, a region (boundary) separating such random and random ones. Because it was difficult to think that there exists. For example, FIG. 9 shows an electron microscope (SEM) photograph showing the amorphous state of the silicon film when the deposition temperature is 510 ° C. and the deposition rate is 12.9 Å / min. FIG. 9 corresponds to the SEM photograph shown in FIG. 4 before thermal oxidation. As shown in FIG. 9, in the amorphous film before thermal oxidation, a region called an island is not observed depending on the SEM. Therefore, it was believed that such an area called an island does not exist in the case of an amorphous film.

  However, when the present inventor observed this amorphous film with an atomic force microscope (AFM), it was confirmed that such a region called an island was present. For example, FIG. 10 shows an electron microscope (AFM) photograph showing an amorphous state immediately after deposition of a silicon film when the deposition temperature is 510 ° C. and the deposition rate is 12.9 Å / min. That is, the island that was not confirmed by the SEM of FIG. 9 was clearly confirmed by the AFM of FIG. Further, FIG. 11 shows an electron microscope (AFM) photograph showing the amorphous state of the silicon film when the deposition temperature is 570 ° C. Further, FIG. 12 shows an electron microscope (SEM) photograph showing a polycrystalline state after the silicon film is thermally oxidized. As is clear from a comparison between FIG. 10 and FIG. 11, the island size decreases as the deposition temperature increases. 4 (corresponding after thermal oxidation in FIG. 10) and FIG. 12 (corresponding after thermal oxidation in FIG. 11), as the deposition temperature rises and the islands constituting the deposited film become smaller, The grain area (grain size) constituting the subsequent polycrystalline film is also reduced. Thus, the size of the islands (regions) constituting the deposited film and the size of the grains constituting the polycrystalline film obtained by thermally oxidizing these films are clearly strongly correlated. That is, when a deposited film composed of large islands (regions) is thermally oxidized, a polycrystalline film composed of large grains and a thermal oxide film are obtained.

Actually, the silicon films of the thin film semiconductor device according to the present invention (circles in FIG. 3) are all in an amorphous state immediately after being deposited by the LPCVD method, and the size of islands (regions) constituting the amorphous state. For example, in the case shown in FIG. 10, the (diameter) is distributed from about 100 nm to about 400 nm. Further, the average area of the island is almost equal to or slightly smaller than the average area of the grain, and is 10,000 nm ² or more when the deposition temperature and the deposition rate are optimum.

In contrast, in a comparative example in which a silicon film is deposited at a deposition temperature of 580 ° C. or more and a thin film semiconductor device is formed using a thermal oxidation method, a polycrystalline state is formed immediately after deposition by the LPCVD method. The size (diameter) of the region that constitutes is distributed from about 20 nm to about 80 nm. In addition, the average area of the region in this case is 10000 nm ² or less. FIG. 13 shows an electron microscope (SEM) photograph showing a polycrystalline state before thermal oxidation when the deposition temperature is 600 ° C. Further, when the silicon film is deposited at 580 ° C. or less and the deposition rate is less than 6 Å / min, the deposited film is in an amorphous state, and the size of the region constituting the amorphous material is still about 20 nm to 80 nm. It was. As described above, when the diameter of the region constituting the semiconductor film immediately after deposition is distributed to 100 nm or more, by thermally oxidizing these semiconductor films, the average value of the grain area of the polycrystalline semiconductor film is 10000 nm ² or more. As a result, a high-performance thin film semiconductor device is obtained. In the second embodiment, the intrinsic silicon film is described in detail as an example. However, the semiconductor film deposition process is adjusted to deposit a thin film having a large region, and these are thermally oxidized to form a polycrystalline semiconductor film having a large grain size. The present invention of manufacturing a high-performance thin film semiconductor device is universal. Therefore, the present invention is effective not only in the case of using an intrinsic silicon film but also in the case where a silicon film containing a donor or an acceptor, a silicon germanium film, or the like is used for a semiconductor layer. The semiconductor film deposition method is not limited to the LPCVD method, and may be a plasma CVD method, a sputtering method, a vapor deposition method, or the like. If the average area of the island (region) constituting the semiconductor film immediately after film formation by these methods is 10000 nm ² or more, a large grain polycrystalline film can be obtained by thermal oxidation, and a high performance thin film semiconductor device Is manufactured.

B. Regarding Deposition Temperature and Deposition Rate As described above, in the present invention, the semiconductor film is deposited under the condition that the nucleus generation rate is lowered and the island growth rate is increased. In this case, the problem is how to control the nucleus generation rate and the island growth rate. In this embodiment, for example, the nucleus generation rate is controlled by the deposition temperature (substrate surface temperature), and the island growth rate is controlled by the deposition rate. And by lowering the deposition temperature, the generation rate of nuclei is reduced, and by increasing the deposition rate, the growth rate of the island is increased. However, the method for controlling the nucleus generation rate and the island growth rate is not limited to the above-described method, and the nucleus generation rate can be reduced by changing the material of the substrate, for example. For example, a special silicon dioxide film may be employed as a change in the material of the substrate.

  Now, when the deposition temperature is fixed, the deposition rate can be controlled by the flow rate of the source gas (monosilane, disilane, etc.) and the deposition pressure. However, the deposition rate is also related to the deposition temperature, and the deposition rate increases as the deposition temperature increases. However, if the deposition temperature is increased, the generation speed of nuclei is further increased as described above, and the principle of the present invention cannot be realized. Therefore, in this embodiment, the deposition temperature is fixed to a low value, thereby slowing the generation rate of the nuclei, while increasing the flow rate of the source gas in order to increase the deposition rate that has been slowed by lowering the temperature, or The deposition pressure is increased. As a result, a control method consistent with the principle of the present invention can be realized. In contrast, in the comparative example, for example, the deposition temperature is conventionally in the range of 600 ° C to 650 ° C. Under these conditions, as is apparent from FIG. 3, even when the flow rate of the source gas and the deposition pressure are controlled to increase the deposition rate, the generation rate of the nuclei is too high, so the islands constituting the deposited film are small and move. A high-quality, high-quality semiconductor film could not be obtained.

  Strictly speaking, the deposition rate is related not only to the deposition temperature, the flow rate of the source gas, and the deposition pressure, but also to, for example, the volume of the LPCVD apparatus and the total reaction area after inserting the substrate. For example, when the total reaction area is large, the deposition rate is slow even with the same raw material gas flow rate. For example, (J. Appl. Phys. 74 (4), 15 August 1993, pages 2870 to 2885) describes how the deposition rate is determined. In summary, the deposition rate is a function of the concentration of the source gas when the deposition temperature is fixed, and the higher the concentration, the faster the deposition rate. The concentration of the source gas becomes a function of the partial pressure of the source gas and the temperature of the source gas. The higher the partial pressure of the source gas, the higher the concentration, and the higher the source gas temperature, the lower the concentration. The temperature of the source gas is determined by the pumping speed of the pump attached to the chamber and the source gas flow rate. The deposition pressure is also related to the performance of the pump or the flow rate of the source gas. In any case, the deposition rate can be controlled by the flow rate of the source gas and the deposition pressure if parameters such as the deposition temperature, the volume of the LPCVD apparatus, and the total reaction area are fixed.

  The generation rate of nuclei is also affected by the flow rate of the source gas and the deposition pressure. However, the deposition temperature has a greater effect on the nucleus generation rate. The effect of increasing the flow rate of the source gas and increasing the deposition pressure is to increase the deposition rate rather than to increase the nucleus generation rate. Will be strongly affected.

  The deposition rate corresponds to the deposited film thickness divided by the deposition time, and the deposition time corresponds to the sum of the time required for nucleus generation and the time required for island growth. On the other hand, the growth rate of the island corresponds to a value obtained by differentiating the deposited film thickness with the deposition time. Therefore, strictly speaking, the deposition rate correlates with the growth rate of the islands, but is not equal. However, usually, the time required for the generation of nuclei is sufficiently small compared with the time for depositing a film of several hundreds of liters or more, so that the deposition rate and the island growth rate are almost equal. In fact, in all the experimental data shown in FIG. 3, the deposition time (T) and the deposited film thickness (tsi) have the relationship of the following equation (linear equation passing through the origin).

tsi = DR × T
In other words, the deposition rate DR and the island growth rate agree with each other within the measurement error.

C. Regarding the optimum value of the deposition temperature In FIG. 3, it is assumed that the deposition temperature is preferably 580 ° C. or lower. For example, FIG. 14 shows a characteristic diagram showing the relationship between the deposition temperature and the average grain area after thermal oxidation. 14 and FIG. 6A show data in which the points indicated by □ in FIG. 14 are determined. As shown in FIG. 14, the average grain area becomes very large at the deposition temperature of 580 ° C. However, as shown in the figure, it is possible to adopt the maximum value of the average grain area, preferably by setting it to 550 ° C. or less. FIG. 16 is a characteristic diagram showing the relationship between the deposition temperature and the leakage current when the transistor is off. As shown in FIG. 16, in the range where the deposition temperature is 530 ° C. or less, the leakage current at the off time is greatly reduced. In general, the off-state leakage current increases when there are many defects in the crystal. Therefore, from the characteristic diagram of FIG. 16, it is understood that when a semiconductor film is deposited at 530 ° C. or lower and thermal oxidation is performed, not only the grain area is increased, but also defects in the crystal can be reduced. .

  The lower limit of the deposition temperature can be determined depending on the type of raw material gas and the like. When the raw material gas is monosilane, for example, it is 460 ° C., and when it is disilane, it is, for example, 370 ° C.

  In FIG. 14, when the deposition temperature is lower than 500 ° C., the grain area is reduced. This is a case where the source gas is monosilane, and such a result is not obtained when disilane or the like is used. The reason is that in the case of monosilane, the deposition rate decreases when the deposition temperature is lower than 500 ° C., but in the case of disilane or the like, this is not the case.

D. Regarding the roughness of the surface of the semiconductor film and the surface of the gate insulating film In general, when an oxide film is formed by a thermal oxidation method, the surface shape of the completed oxide film inherits the surface shape of the semiconductor film before oxidation. Since the MOS field effect transistor forms a gate electrode on such an oxide film, the surface shape of the semiconductor film immediately after being deposited by the LPCVD method or the like reflects the interface shape between the gate insulating film and the gate electrode of the thin film semiconductor device. Is done. In other words, if the deposited semiconductor film is smooth, the interface between the gate insulating film and the gate electrode is also smooth. If the surface of the deposited semiconductor film is uneven, the interface between the gate insulating film and the gate electrode is also uneven. The flatness at the interface between the gate insulating film and the gate electrode affects the source-gate breakdown voltage or the drain-gate breakdown voltage when the thin film semiconductor device is manufactured. When the unevenness is severe, electric field concentration easily occurs, and a high electric field is generated locally, and avalanche breakdown easily occurs between the source and gate or between the drain and gate. Since the surface of the deposited semiconductor film was very smooth in the thin film semiconductor device (circle mark in FIG. 3) according to this example, the roughness of the surface of the gate insulating film after thermal oxidation is the average of the center line average roughness (Ra). The interval estimate at a value of 1.995 nm and 95% confidence coefficient was 0.323 nm. In contrast, the surface of the deposited semiconductor film is uneven regardless of the deposition temperature, and the roughness of the surface of the gate insulating film after thermal oxidation is the center line, regardless of the deposition temperature. The average value of the average roughness (Ra) was 3.126 nm, and the interval estimate value with a 95% confidence coefficient was 0.784 nm. In this embodiment, the reason why the surface of the deposited semiconductor film is smooth is that the island region in the amorphous state is large as shown in FIG. The centerline average roughness here refers to the area of the portion obtained by folding the roughness curve from the centerline divided by the measured length.

Reflecting these facts, the breakdown voltage between the source and gate of the thin film semiconductor device according to the present invention (circled in FIG. 3) is three thin film semiconductor devices for each sample when the source is grounded and the gate is negative. As a result, all samples were very good at 100 v or higher (withstand pressure of 8.333 Mv / cm or higher). On the other hand, the breakdown voltage between the source and gate of the thin film semiconductor device according to the comparative example (marked with x in FIG. 3) was examined for each of the three thin film semiconductor devices with 11 samples measured when the source was grounded and the gate was negative. As a result, 28 samples showed a breakdown voltage of 100v or more, and there was a sample (a sample with a deposition temperature of 585 ° C. and a mobility of 15 cm ² / v · s) that caused avalanche breakdown at 65v (see FIG. 17). When a thin film semiconductor device is applied to a liquid crystal panel, the maximum applied voltage between the source and the gate is about 20 V, but there are several hundred thousand or more thin film semiconductor devices in one panel. Since the avalanche breakdown between the source and the gate is a stochastic process, it is understood that the thin film semiconductor device of the present invention greatly improves the pixel defect due to the source and gate short circuit as compared with the comparative example.

3. Third Example The material gas was changed by the LPCVD method, and the thin film semiconductor device was produced by the manufacturing process detailed in the first example for other processes. In the third example, a semiconductor film was deposited using disilane (Si ₂ H ₆ ) having a purity of 99.99% or more as a source gas in the LPCVD apparatus described in detail in the first example. The deposition temperature was 450 ° C. and disilane was introduced into the 100 SCCM reactor. Helium having a purity of 99.9995% or more was used as a dilution gas and introduced into a 100 SCCM reactor. The pressure during silicon film deposition was 0.3 torr, and the deposition rate was 19.97 Å / min. The silicon film thus obtained was in an amorphous state and had a thickness of 1000 mm. The size of islands (regions) constituting the amorphous film was distributed from about 150 nm to about 450 nm. After patterning the amorphous film, thermal oxidation was performed at 1 atm for 23 minutes and 36 seconds in a 100% oxygen atmosphere at 1160 ° C. The surface roughness of the gate insulating film after thermal oxidation was 1.84 nm in terms of centerline average roughness (Ra). Further, when the gate insulating film was peeled off with a 10% hydrofluoric acid aqueous solution and the exposed surface of the polycrystalline silicon film was observed with an SEM, the average value and standard deviation of the grain area of the polycrystalline silicon film were 14110 nm ² and 15595 nm, respectively. ² . Hereinafter, a thin film semiconductor device was created by the manufacturing process detailed in the first embodiment, and transistor characteristics were measured. The definitions of measurement conditions, on-current, off-current, and mobility are the same as in the first embodiment. As a result, an excellent thin film semiconductor device with an on-current of 53.5 μA, an off-current of 0.154 pA, and a mobility of 78.5 cm ² / v · sec was obtained without any hydrogenation treatment. Further, the source-gate breakdown voltage was 100 V or higher in all three thin film semiconductor devices. Further, when this thin film semiconductor device was irradiated with hydrogen plasma for 2 hours, the on-current was improved to 77.7 μA, the off-current to 0.137 pA, and the mobility to 107 cm ² / v · sec.

As shown in the third embodiment, when the semiconductor film is deposited at a temperature of 580 ° C. or less and at a deposition rate of 6 Å / min or more and subjected to thermal oxidation, the average grain area of the polycrystalline silicon film becomes 10000 nm ² or more. The effect of smoothing the interface between the insulating film and the gate electrode and obtaining a high-performance thin film semiconductor device is not limited to the case where the type of source gas is monosilane. This is because the basic concept of the present invention is to form a semiconductor film by lowering the deposition temperature and slowing down the generation rate of nuclei generated on the insulating material and increasing the island growth rate to 6 Å / min or more. This is because the region (island) is based on the principle of making it smooth and large. Therefore, the present invention is effective for any system in which the nucleation rate is low and the island growth rate is high. In the third embodiment, disilane is used as a raw material gas. However, if the raw material gas can suppress the nucleation rate by setting the deposition temperature to 580 ° C. or lower, and can increase the island growth rate at a deposition rate of 6 μm / min or higher. For example, trisilane (Si ₃ H ₆ ), fluorinated silane (Si _n H _x F _y : n, x, y are integers), silane chloride (Si _n H _x Cl _y : n, x, y are integers), etc. However, the present invention is also effective.

4). Fourth Example Thin film semiconductor devices were prepared by changing the thermal oxidation temperature for forming the gate insulating layer. In the fourth embodiment, an intrinsic silicon film is deposited on a quartz substrate to a thickness of 1000 mm by LPCVD. Deposition conditions are the same as in the first embodiment. That is, the deposition temperature was 510 ° C., monosilane having a purity of 99.99% or more was used as a raw material gas, and the monosilane was supplied to a 100 SCCM reactor. The deposition pressure was 0.8 torr and the silicon film deposition rate was 21.5 Å / min. After patterning the silicon film, a silicon oxide film serving as a gate insulating layer was formed on the silicon film surface by a thermal oxidation method. At this time, the thermal oxidation temperature was used as a parameter. The thermal oxidation temperatures were 1160 ° C, 1100 ° C, 1050 ° C, 1000 ° C, 950 ° C and 900 ° C. The thermal oxidation furnace is initially maintained at 800 ° C. at 1 atmosphere in a 100% oxygen atmosphere. After inserting the substrate into the thermal oxidation furnace in this state, the temperature was raised to a desired oxidation temperature at a rate of 10 ° C./min. After reaching the oxidation temperature, thermal oxidation was carried out while maintaining that state for an appropriate time according to each temperature. In the case of 1160 ° C., this time is 23 minutes and 36 seconds. Below, 51 minutes 59 seconds at 1100 ° C, 1 hour 38 minutes 33 seconds at 1050 ° C, 3 hours 17 minutes 15 seconds at 1000 ° C, 6 hours 49 minutes 40 seconds at 950 ° C, 14 hours 48 minutes 23 seconds at 900 ° C there were. After completion of this thermal oxidation, the inside of the reaction furnace was replaced with nitrogen and maintained at the thermal oxidation temperature for 15 minutes, and then the substrate was taken out. By this step, the film thickness of the thermal oxide film becomes 1200 mm at all thermal oxidation temperatures, and the film thickness of the polycrystalline silicon film serving as the active layer of the thin film semiconductor device becomes 400 mm. Thereafter, a thin film semiconductor device was fabricated in exactly the same steps as those described in detail in the first embodiment. However, the final hydrogenation treatment was not performed in the fourth example. The transistor characteristics of the thin film semiconductor device thus obtained are shown in FIG. In FIG. 18, the vertical axis represents the on-current. The upper horizontal axis represents the thermal oxidation temperature, and the lower horizontal axis represents the reciprocal of the absolute temperature of the thermal oxidation temperature. It can be seen from FIG. 18 that when the thermal oxidation temperature is lowered, the transistor characteristics deteriorate, but the degree of deterioration of the thin film semiconductor device fabricated according to the present invention is relatively small. For comparison, FIG. 18B shows the thermal oxidation temperature dependence of the transistor characteristics of the thin film semiconductor device prepared in the comparative example. In the thin film semiconductor device according to the comparative example, a silicon film that will eventually become an active layer is deposited at a deposition temperature of 600 ° C., a monosilane flow rate of 100 SCCM, a deposition pressure of 40 mtorr, and a deposition rate of 38.1 L / min. It was created. It can be seen that the characteristics of the thin film semiconductor device according to the comparative example are rapidly deteriorated when the thermal oxidation temperature is lowered, and the thermal oxidation temperature cannot actually be lowered. On the other hand, it can be seen that the thin film semiconductor device of the present invention is superior to the thin film semiconductor device obtained by thermal oxidation at 1160 ° C. in the comparative example even when the thermal oxidation temperature is 900 ° C. In the thin film semiconductor device according to the comparative example, the surface roughness of the MOS interface (interface between the semiconductor layer and the gate insulating layer) becomes severe when the thermal oxidation temperature is about 1100 ° C. or less. This is because the MOS interface is very stable in the thin film semiconductor device according to the present embodiment, but the roughness of the MOS interface does not become so severe even if the thermal oxidation temperature is lowered.

  19, 20, and 21 are electron microscope (SEM) photographs showing the state of the MOS interface of the thin film semiconductor device of this example when the thermal oxidation temperatures are 1160 ° C., 1050 ° C., and 900 ° C., respectively. Is shown. On the other hand, FIG. 22, FIG. 23 and FIG. 24 show electron microscopes (SEMs) showing the states of the MOS interface of the thin film semiconductor device of the comparative example when the thermal oxidation temperatures are 1160 ° C., 1050 ° C., and 900 ° C., respectively. A picture is shown. From these photographs, it is understood that the thin film semiconductor device according to this example does not have a very rough MOS interface even when the thermal oxidation temperature is lowered, as compared with the comparative example. For example, comparing FIG. 19 (this example) and FIG. 22 (comparative example), both of which have a thermal oxidation temperature of 1160 ° C., the MOS interface is smooth and there is no significant difference between the two. However, comparing FIG. 20 (this example) and FIG. 23 (comparative example), both of which have a thermal oxidation temperature of 1050 ° C., there is a considerable difference in the roughness of the MOS interface. Further, the difference between FIG. 21 (this example) and FIG. 24 (comparative example) both having a thermal oxidation temperature of 900.degree.

  Thin film semiconductor devices are often made on refractory quartz glass or the like. However, if the thermal oxidation temperature is lowered on any substrate, the amount of expansion and contraction of the substrate and the amount of warp deformation can be reduced, enabling high-density and high-definition processing. Further, from the viewpoint of the life and maintenance of the apparatus, it is preferable to lower the temperature. As described above, there are many benefits of lowering the temperature, but in the comparative example, as shown in FIG. From this point, the advantages of the present invention will be understood.

5). Fifth Example The fifth example is an example when the present invention is applied to a low temperature process.

  In recent years, with the increase in screen size and resolution of a liquid crystal display (LCD), the driving method has shifted from the simple matrix method to the active matrix method, and a large amount of information can be displayed. The active matrix method enables a liquid crystal display having more than several hundred thousand pixels, and forms a switching transistor for each pixel. As a substrate for various liquid crystal displays, a transparent insulating substrate such as a fused quartz plate or glass that enables a transmissive display is used. As the active layer of the thin film transistor (TFT), a semiconductor film such as amorphous silicon or polycrystalline silicon is usually used. However, when the drive circuit is integrated with the thin film transistor, polycrystalline silicon having a high operation speed is advantageous. It is. When a polycrystalline silicon film is used as an active layer, a fused quartz plate is used as a substrate, and a TFT is usually produced by a manufacturing method called a high-temperature process in which the maximum process temperature exceeds 1000 ° C. On the other hand, when an amorphous silicon film is used as an active layer, a normal glass substrate is used. In order to expand the LCD display screen and reduce the price, it is indispensable to use inexpensive ordinary glass as the insulating substrate. However, as described above, the amorphous silicon film has problems such as significantly lower electrical characteristics than the polycrystalline silicon film and a low operation speed. In addition, since the polycrystalline silicon TFT of the high temperature process uses a fused quartz plate, there is a problem that it is difficult to increase the size and cost of the LCD. As a result, there is a strong demand for a technique for producing a thin film semiconductor device having a semiconductor film such as a polycrystalline silicon film as an active layer on a normal glass substrate. Therefore, when using a large-sized normal glass substrate rich in mass productivity, there is a great restriction that the maximum process temperature is about 600 ° C. or less in order to avoid deformation of the substrate. That is, a technique for forming a thin film transistor capable of operating a liquid crystal display under such restrictions and an active layer of a thin film transistor capable of operating a drive circuit at high speed is desired. These are currently referred to as low temperature process poly-Si TFTs.

A conventional low-temperature process poly-Si TFT is a SID (Society for Information Display) '93 digest P.D. 387 (1993). According to this, first, an amorphous silicon (a-Si) film having a thickness of 50 nm is deposited at a deposition temperature of 550 ° C. using monosilane (SiH ₄ ) as a source gas by LPCVD, and laser irradiation is performed on the a-Si film. The a-Si film is modified to a poly-Si film. After patterning the poly-Si film, a SiO ₂ film as a gate insulating film is deposited at a substrate temperature of 100 ° C. by ECR-PECVD. After forming a gate electrode with tantalum (Ta) on the gate insulating film, donor or acceptor impurities are ion-implanted into the silicon film using the gate electrode as a mask to make the source / drain of the transistor self-aligned (self-aligned) Form. At this time, ion implantation uses a mass non-separation type implantation apparatus called an ion doping method, and phosphine (PH ₃ ) or diborane (B ₂ H ₆ ) diluted with hydrogen is used as a source gas. The activation of the implanted ions is 300 ° C. Thereafter, an interlayer insulating film is deposited, and electrodes and wirings are made of indium tin oxide (ITO) or aluminum (Al), thereby completing the thin film semiconductor device.

  However, various problems are inherent in the low-temperature process poly-Si TFT according to the prior art. The fifth embodiment described below also solves these problems. According to the fifth embodiment, a good thin film semiconductor device can be manufactured by a practical and simple method. Can do. Further, according to the fifth embodiment, a thin film semiconductor device can be manufactured more stably at a process temperature at which a normal large glass substrate can be used.

  Hereinafter, the fifth embodiment will be described in detail. 25A to 25D are views showing a manufacturing process of a thin film semiconductor device for forming a MIS field effect transistor.

In the fifth embodiment, a non-alkali glass of 235 mm □ (Nippon Electric Glass Co., Ltd. OA-2) is used as the substrate 101. However, the type and size of the substrate are not limited as long as the substrate can withstand the maximum process temperature. I will not. First, a silicon dioxide film (SiO ₂ film) 102 serving as a base protective film is formed on a substrate 101 by an atmospheric pressure chemical vapor deposition method (APCVD method), a PECVD method, or a sputtering method. In the APCVD method, a SiO ₂ film can be deposited using monosilane (SiH ₄ ) or oxygen as a raw material at a substrate temperature of about 250 ° C. to 450 ° C. In the PECVD method or the sputtering method, the substrate temperature can be set from room temperature to 400 ° C. In the fifth example, a 2000-nm SiO ₂ film was deposited at a temperature of 300 ° C. using SiH ₄ and O ₂ as source gases by the APCVD method.

Next, an intrinsic silicon film, which later becomes an active layer of the thin film semiconductor device, was deposited by about 500 mm. The intrinsic silicon film was deposited for 31 minutes at a deposition temperature of 495 ° C. using a high-vacuum LPCVD apparatus in which monosilane (SiH ₄ ) as a source gas was flowed at 200 SCCM. The high vacuum type LPCVD apparatus used in the fifth example has a volume of 184.5 l. The 17 substrates were inserted into a reaction chamber maintained at 300 ° C. with the front side facing down. After inserting the substrate, the operation of the turbo molecular pump was started, and after reaching a steady rotation, a leakage inspection was performed for 2 minutes. The leakage rate of degassing, etc. at this time was 3.3 × 10 ⁻⁵ torr / min. Thereafter, the temperature was raised from an insertion temperature of 300 ° C. to a deposition temperature of 495 ° C. over an hour. During the first 10 minutes of temperature increase, no gas was introduced into the reaction chamber and the temperature was increased in vacuum. The minimum background pressure reaching the reaction chamber 10 minutes after the start of temperature increase was 5.4 × 10 ⁻⁷ torr. Further, nitrogen gas having a purity of 99.9999% or more was kept flowing for 300 SCCM during the remaining 50 minutes. The equilibrium pressure in the reaction chamber at this time was 3.0 × 10 ⁻³ torr. After reaching the deposition temperature, SiH ₄ as a source gas was flowed at 200 SCCM, and a silicon film was deposited for 31 minutes and 00 seconds. The pressure in the reaction chamber was maintained at 1.3 torr by a pressure regulator. Since the thickness of the silicon film thus obtained was 514 mm, the deposition rate was 16.6 m / min. Thus, in the fifth embodiment, since the deposition temperature is 495 ° C. and the deposition rate is 16.6 Å / min, both the deposition temperature and the deposition rate are in the range of 580 ° C. or less and 6 Å or more shown in FIG. Will enter. Therefore, as described in the first to fourth embodiments, a semiconductor film having good characteristics can be formed.

The silicon film thus obtained is a high-purity a-Si film. Next, the a-Si film is irradiated with optical energy or electromagnetic wave energy for a short time to crystallize a-Si and modify it to polycrystalline silicon (poly-Si). In the fifth example, an excimer laser (wavelength: 308 nm) of xenon chloride (XeCl) was irradiated. The intensity half width of the laser pulse is 45 ns. Since the irradiation time is such a very short time, the substrate is not heated during the crystallization of a-Si to poly-Si, and therefore the substrate is not deformed. Laser irradiation was performed in air with the substrate at room temperature (25 ° C.). The area of one irradiation of laser irradiation is a square of 8 mm □, and is shifted by 4 mm for each irradiation. After scanning in the horizontal direction (Y direction) first, the vertical direction (X direction) is also shifted by 4 mm, and then the horizontal direction is shifted by 4 mm again. After that, this scanning is repeated over the entire surface of the substrate. Perform the second laser irradiation. This first laser irradiation energy density was 160 mJ / cm ² . After the first laser irradiation is completed, the second laser irradiation is performed on the entire surface with an energy density of 275 mJ / cm ² . The scanning method is the same as the first laser irradiation, and the 8 mm square irradiation area is shifted by 4 mm in the Y and X directions. By this two-stage laser irradiation, the entire substrate is uniformly crystallized from a-Si to poly-Si. In the fifth embodiment, a XeCl excimer laser is used as optical energy or electromagnetic wave energy, but the energy source is not limited to the energy source if the energy irradiation time is within several tens of seconds. For example, various lasers such as ArF excimer laser, XeF excimer laser, KrF excimer laser, YAG laser, carbon dioxide gas laser, Ar laser, dye laser, or lamp light such as arc lamp or tungsten lamp may be irradiated. . When arc lamp irradiation is performed, the lamp output is set to about 1 kW / cm ² or more and the irradiation time is set to about 45 seconds, so that the film quality modification from a-Si to poly-Si proceeds. Even during this crystallization, since the energy irradiation time is short, the substrate is not deformed or cracked by heat. Next, this silicon film was patterned to form a channel portion semiconductor film 103 to be an active layer of the transistor (FIG. 25A).

  Note that in order to modify the a-Si film into a poly-Si film, heat treatment may be performed at a temperature of about 600 ° C. or lower in addition to the energy irradiation. This is a method called a solid phase growth method. If the temperature is about 600 ° C., crystallization is completed by a heat treatment of about 8 to 24 hours. In this way, a method of manufacturing a thin film semiconductor device that combines a low temperature process and a solid phase growth method can be realized.

Thereafter, the gate insulating film 104 is formed by an ECR-PECVD method, a PECVD method, or the like. In the fifth example, a SiO ₂ film was used as the gate insulating film, and was deposited to a thickness of 1200 mm by PECVD (FIG. 25B). In the PECVD method, the substrate gas was formed at a substrate temperature of 300 ° C. using monosilane (SiH ₄ ) and laughing gas (N ₂ O) as source gases. The plasma was generated under the conditions of an output of 900 W and a degree of vacuum of 1.50 torr by a 13.56 MHz rf wave. The flow rate of SiH ₄ was 250 SCCM and the flow rate of N ₂ O was 7000 SCCM. The deposition rate of the SiO ₂ film was 48.3 Å / s. Immediately before and immediately after forming SiO ₂ under these conditions, the silicon film and the formed oxide film were irradiated with oxygen plasma to improve the MOS interface and the oxide film. In the fifth embodiment, monosilane and laughing gas are used as source gases, but not limited to these, organic silane such as TEOS (Si— (O—CH ₂ —CH ₃ ) ₄ ) and oxidizing gas such as oxygen are used. It may be used. Further, although a highly versatile PECVD apparatus is used here, it is needless to say that an insulating film may be formed by an ECR-PECVD apparatus. Whatever CVD apparatus or source gas is used, the insulating film formation temperature is preferably 350 ° C. or lower. This is important for preventing thermal deterioration of the MOS interface and the gate insulating film. The same applies to all the following steps. All process temperatures after the formation of the gate insulating film must be suppressed to 350 ° C. or lower. This is because a high-performance thin film semiconductor device can be manufactured easily and stably.

Subsequently, a thin film that becomes the gate electrode 105 is deposited by sputtering, vapor deposition, CVD, or the like. In the fifth embodiment, tantalum (Ta) was selected as the gate electrode material, and 5000 liters were deposited by sputtering. The substrate temperature during sputtering was 180 ° C., and argon (Ar) containing 6.7% nitrogen (N ₂ ) was used as the sputtering gas. The optimal nitrogen content in the argon is 5.0% to 8.5%. The crystal structure of the tantalum film obtained under these conditions is mainly an α structure, and its specific resistance is 40 μΩcm. Therefore, the sheet resistance of the gate electrode in the fifth embodiment is 0.8Ω / □.

After depositing a thin film to be a gate electrode, patterning is performed, and subsequently, impurity ion implantation 106 of phosphorus element or the like is performed on the intrinsic silicon film by using a bucket-type mass non-separation type ion implantation apparatus (ion doping method). A drain portion 107 and a channel region 108 were formed (FIG. 25C). In the fifth embodiment, since an N-channel TFT is aimed to be produced, phosphine (PH ₃ ) having a concentration of 5% diluted in hydrogen is used as a source gas, and a high frequency output of 38 W and an acceleration voltage of 80 kV are 5 × 10 ¹⁵ 1. / Cm ² concentration. At this time, the phosphorus concentration in the silicon film is about 5 × 10 ²⁰ cm ⁻³ . As the high-frequency output, an optimum value in the range of about 20 W to 150 W is used. When making a p-channel TFT, diborane (B ₂ H ₆ ) having a concentration of 5% diluted in hydrogen is used as a source gas, the high frequency output is changed from 20 W to 150 W, the acceleration voltage is 60 kV, and 5 × 10 ¹⁵ 1 / implanted in a concentration of about cm ^2. When a CMOS TFT is formed, one of n-channel TFTs and p-channel TFTs is alternately covered with a mask using an appropriate mask material such as polyimide resin, and each ion implantation is performed by the above-described method.

Next, 5000 μm of interlayer insulating film 109 is deposited. In the fifth embodiment, SiO ₂ is formed by PECVD as an interlayer insulating film. In the PECVD method, TEOS (Si— (O—CH ₂ —CH ₃ ) ₄ ) and oxygen (O ₂ ) were used as source gases at a substrate temperature of 300 ° C. The plasma was generated by a 13.56 MHz rf wave under conditions of an output of 800 W and a degree of vacuum of 8.0 torr. The TEOS flow rate was 200 SCCM and the O ₂ flow rate was 8000 SCCM. At this time, the deposition rate of the SiO ₂ film was 120 Å / s. After such ion implantation and formation of the interlayer insulating film, heat treatment was performed at 300 ° C. for 1 hour in an oxygen atmosphere to activate the implanted ions and to burn the interlayer insulating film. The heat treatment temperature is preferably 300 ° C to 350 ° C. Thereafter, contact holes are opened, and source / drain extraction electrodes 110 are formed by sputtering or the like, thereby completing a thin film semiconductor device (FIG. 25D). Indium tin oxide (ITO) or aluminum (Al) is used as the source / drain extraction electrode. The substrate temperature during sputtering of these conductors is about 100 ° C. to 250 ° C.

When the transistor characteristics of the thin film semiconductor device thus fabricated were measured, the source / drain current Ids when the transistor was turned on with the source / drain voltage Vds = 4 V and the gate voltage Vgs = 10 V was defined as the on-current ION. Thus, ION = (20.6 + 1.67, −1.48) × 10 ⁻⁶ A with a 95% reliability coefficient. The off-state current when the transistor was turned off at Vds = 4 V and Vgs = 0 V was IOFF = (2.27 + 0.40, −0.31) × 10 ⁻¹² A. Here, the measurement was performed at a temperature of 25 ° C. for a transistor having a channel portion length L = 10 μm and a width W = 10 μm. The effective electron mobility determined from the saturation current region (J. Levinson et al. J, Appl, Phys. 53, 1193'82) is μ = 47.54 ± 3.53 cm / v. sec. Thus, according to the present invention, a thin film semiconductor device having high mobility, changing Ids by nearly 7 orders of magnitude with respect to 10V modulation of the gate voltage, and further reducing the variation and achieving an extremely excellent and uniform thin film semiconductor device can be obtained. It was easily realized in a low temperature process of 600 ° C. or lower. Moreover, in the present invention, since the maximum process temperature is the first process, misalignment due to the thermal process is minimized, and an inexpensive glass substrate can be used. In this embodiment, since the initial a-Si film is composed of a large lump, the size of each crystal grain when crystallized increases, and high-performance electrical characteristics can be obtained. That is, an ideal a-Si film can be obtained by optimizing the film formation conditions of the initial a-Si film, and a uniform and high-quality poly-Si film can be obtained by crystallizing these. Regarding the quality of the initial a-Si film, the conventional a-Si film has a deposition temperature of about 550 ° C. or higher by LPCVD and does not consider the deposition rate, or the substrate temperature is also about 400 ° C. by PECVD. No consideration was given. Therefore, problems such as non-uniformity and inability to perform stable production have occurred. Another gist of the present invention is to suppress the process temperature after forming the poly-Si film to 350 ° C. or lower. This is because the MOS interface and insulating film quality can be stabilized. In that sense, the present invention is particularly effective for an upper gate type TFT as shown in FIGS. In the case of the lower gate type TFT, a silicon film is deposited after the gate insulating film is formed, and further crystallization such as laser irradiation is performed, so that the MOS interface and a part of the gate insulating film inevitably have a high temperature heat of nearly 1000 ° C. Even a short time is exposed to the environment. This thermal environment roughens the MOS interface and further changes the chemical composition and bonding state of the insulating film near the MOS interface. As a result, the transistor characteristics are deteriorated and the variation becomes large. When producing poly-Si TFTs by a low temperature process, it is the most important problem to form a high-quality poly-Si film. Therefore, when the amorphous film is crystallized by optical energy, electromagnetic energy, or a low temperature thermal environment of about 600 ° C., it is necessary to optimize the film quality of the amorphous film. As described in detail in the section “C. Optimum value of deposition temperature” in the second embodiment, the film was formed under conditions where the deposition temperature was 530 ° C. or less and the deposition rate was 6 Å / min or more. A crystalline semiconductor film (amorphous silicon film) has a large area of grains when the film is crystallized, and also reduces defects in the crystal. Therefore, an amorphous semiconductor film formed under these conditions is optimal as a semiconductor film for a low-temperature process.

  As described above, according to the fifth embodiment, a high-quality semiconductor film made of a polycrystalline silicon film or the like can be easily formed at a low temperature of less than about 600 ° C. As a result, the characteristics of the thin film semiconductor device were dramatically improved and stable mass production was realized. Specifically, it has the following effects.

  First, since the process temperature is as low as less than 600 ° C., it is possible to use inexpensive glass and reduce the product price. Furthermore, since distortion due to the weight of the glass itself can be prevented, a liquid crystal display (LCD) can be easily enlarged.

  Second, laser irradiation can be performed uniformly over the entire substrate. As a result, the uniformity of each lot was improved and stable production became possible.

  Thirdly, it becomes extremely easy to activate a self-aligned TFT whose source / drain is self-aligned with the gate electrode at an ion doping method and subsequently at a low temperature of about 300 ° C. to 350 ° C. As a result, it became possible to activate stably. Furthermore, a lightly doped drain (LDD) TFT can be formed easily and stably. Since the LDD TFT is realized by a low-temperature process poly-Si TFT, it is possible to miniaturize the TFT element and reduce the off-leakage current.

Fourthly, the conventional low-temperature process poly-Si TFT has shown only good transistor characteristics by SiO ₂ produced by the ECR-PECVD method, but the fifth embodiment can use a general-purpose PECVD apparatus. It became so. Therefore, it is possible to obtain a practical gate oxide film manufacturing apparatus that can be applied to a large substrate and has high mass productivity.

  Fifth, a better thin film semiconductor device having a larger on-current and smaller off-current than the conventional one was obtained. These variations were also reduced.

  As described above, when the present invention is applied to an active matrix liquid crystal display or the like, an inexpensive glass substrate or the like can be used, and a large and high quality LCD can be easily and stably manufactured. In addition, when it is applied to other electronic devices, the deterioration of elements due to heat is reduced. As described above, the fifth embodiment has a great effect of easily realizing high performance and low price of an active matrix liquid crystal display device and an electronic device such as an integrated circuit.

6). Sixth Example The sixth to twelfth examples described below are examples in which process conditions and the like are optimized to obtain an LDD type thin film semiconductor device (LDD type TFT circuit) having good characteristics at high speed. is there.

  The TFT circuit of the sixth embodiment is a CMOS circuit using LDD type TFTs for both p-channel and n-channel. Since the LDD TFT has a high resistance portion between the channel portion and the source / drain portion, the electric field concentration at the drain end of the channel can be suppressed. In addition, the gate-source breakdown voltage is improved. However, there is also a problem that the voltage applied to the channel portion is reduced by the high resistance portion and the on-current is reduced. For this reason, although LDD type TFTs are also used for switching elements in the active matrix portion, SRAM resistance elements, and the like, they have not been used in CMOS high-speed circuits. However, according to experiments and simulations, it has been found that a CMOS circuit using LDD type TFTs can operate at higher speed. However, the high-speed LDD type TFT according to the present invention is not limited to the CMOS structure but can be widely applied to an NMOS structure and a PMOS structure.

First, the structure and manufacturing method of the LDD type CMOS TFT will be described with reference to FIG. A gate insulating film 5 is formed on the semiconductor thin film 2 patterned in an island shape on the insulating substrate 1, and a gate electrode 6 is formed thereon. Next, an impurity serving as a donor in the semiconductor thin film source and drain portions of the n-channel TFT implanted at low concentration the n ^- semiconductor thin film 9. The dose of impurity implantation at this time is about 1 × 10 ¹³ cm ⁻² to 1 × 10 ¹⁴ cm ⁻² , preferably about 2 × 10 ¹³ cm ^{−2 to} 5 × 10 ¹³ cm ⁻² . When the dose amount is within this range, the maximum impurity concentration of the n ⁻ semiconductor thin film 9 is multiplied by 10 ⁵ (see the calculation formula described later) to obtain 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ^19. It is about cm ⁻³ , desirably about 2 × 10 ¹⁸ cm ^{−3 to} 5 × 10 ¹⁸ cm ⁻³ .

Subsequently, an impurity is implanted at a higher concentration into the source / drain portion to form an n ⁺ semiconductor thin film 3. The dose amount of the impurity implantation at this time is about 5 × 10 ¹⁴ cm ⁻² to 1 × 10 ¹⁶ cm ⁻² , preferably about 1 × 10 ¹⁵ cm ^{−2 to} 3 × 10 ¹⁵ cm ⁻² . When the dose is within this range, the maximum impurity concentration of the n ⁺ semiconductor thin film 3 is multiplied by 10 ⁵ to be about 5 × 10 ¹⁹ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ , preferably It becomes about 1 × 10 ²⁰ cm ^{−3 to} 3 × 10 ²⁰ cm ⁻³ . As a result, the island-shaped semiconductor thin film is divided into three different portions of resistance: the intrinsic semiconductor region of the channel portion, the high resistance impurity semiconductor regions on both sides thereof, and the low resistance impurity semiconductor region of the source / drain portions. become.

Similarly, an acceptor impurity is implanted into the semiconductor thin film of the source / drain portion of the p-channel TFT at a low concentration to form the p ⁻ semiconductor thin film 10, and subsequently implanted at a higher concentration into the source / drain portion of the p ⁺ semiconductor thin film 4. And In this method, since the impurity is implanted using the gate electrode as a mask, the boundary between the n ⁻ semiconductor thin film 9 and the channel portion and the boundary between the p ⁻ semiconductor thin film 10 and the channel portion has a self-aligned structure. The boundary between the n ⁻ semiconductor thin film 9 and the n ⁺ semiconductor thin film 3, the p ⁻ semiconductor thin film 10 and the p ⁺ semiconductor thin film 4 is formed by non-self-alignment using a photoresist or the like, and the side of the insulating film on the gate electrode In some cases, a wall is used for self-alignment.

Further, instead of partially implanting impurities into the intrinsic semiconductor as described above, an impurity-containing n ⁺ semiconductor thin film or p ⁺ semiconductor thin film may be formed in an island shape in the source / drain portions in advance. That is, in the TFT, it is desirable to make the (intrinsic) semiconductor thin film as thin as possible in order to limit the current flowing at the time of reverse bias. However, if the thickness is too thin, the aluminum wiring may penetrate through the substrate through the contact hole. Therefore, another island-like semiconductor thin film is formed in the source / drain portion, thereby preventing the above situation and making the (intrinsic) semiconductor thin film even thinner.

  Next, when these TFTs are covered with an interlayer insulating film 7 and wiring is patterned with a metal thin film 8, a CMOS TFT circuit is completed. As a material of the semiconductor thin film 2, a polysilicon or amorphous silicon thin film, a semiconductor thin film such as Te, or a compound semiconductor thin film such as CdSe can be used.

Next, the reason why the LDD type CMOS TFT circuit shown in FIG. 26 is more suitable for high speed operation than the normal structure CMOS TFT circuit shown in FIG. In FIG. 26, the length of the overlapping portion Yjn of the n-channel TFT and the overlapping portion Yjp of the p-channel TFT is smaller than that of the normal structure TFT as shown in FIG. This is because the concentration of impurities implanted into the n ⁻ semiconductor thin film 9 and the p ⁻ semiconductor thin film 10 is very small, and therefore the diffusion length in the channel direction is shortened. The capacitance of the overlapping portion is always a parasitic capacitance and a load on the CMOS circuit. Therefore, an LDD type CMOS TFT circuit having a small overlap capacitance is somewhat advantageous for high-speed operation as compared with a TFT having a normal structure unless the on-current is reduced. On the other hand, the n-channel effective channel length Leffn and the p-channel effective channel length Leffp are derived from the n-channel gate electrode length (see FIG. 26, sometimes referred to as the gate electrode width) Lgaten and p-channel gate electrode length Lgatep, respectively. The length is obtained by subtracting twice the overlapping portion Yjn and twice Yjp. Therefore, if the overlapping portion is small, the effective channel length becomes long and the on-current decreases. Since the LDD type CMOS TFT has a small overlapping portion as described above, the effective channel length is slightly longer than that of the normal structure TFT having the same gate electrode length, and the on-current is reduced. However, in practice, the LDD structure significantly improves the breakdown voltage between the source and the drain, so that a circuit can be configured with an extremely small gate electrode length. As a result, the effective channel length is shortened by adopting the LDD structure, and therefore, the decreased amount of reduced on-current can be compensated for by reducing the gate electrode length.

In general, the channel resistance Rch (on) in the on state of the TFT changes faster than the first order of the effective channel length Leff. That is, Rch (on) is
Rch (on) = k × Leff ⁿ
k: proportionality constant, n> 1
The power n of Leff is usually larger than 1. As a result, the on-current of the TFT increases rapidly as the effective channel length becomes shorter. This is because, in the case of TFT, the channel portion is in a polycrystalline state, so that the shorter the channel, the smaller the number of crystal grain boundaries (grain boundaries) contained in the channel, and the adverse effect on electrical conductivity decreases. It is thought to be from. For this reason, even if the current is somewhat limited by the parasitic resistance of the LDD portion, the current flowing through the element can rather be larger in the TFT of the LDD type having a shorter channel than the TFT having the normal structure. For example, FIG. 28 is a characteristic diagram showing the relationship between the gate electrode length and the source / drain breakdown voltage for each of the LDD type TFT of this embodiment and the TFT having the normal structure. As shown in FIG. 28, in the normal structure TFT, the gate electrode length is 5 μm or less, and the breakdown voltage between the source and the drain is deteriorated. That is, in the normal structure TFT, in order to obtain a sufficient source-drain breakdown voltage, the gate electrode lengths of both the p-channel TFT and the n-channel TFT must be 5 μm or more. On the other hand, in the LDD type TFT of this example, as is clear from FIG. 28, a sufficient source-drain breakdown voltage (20 V or more) can be obtained even when the gate electrode length is 5 μm or less. Even when the gate electrode length is 3 μm, a source-drain breakdown voltage of 20 V or more can be obtained. Furthermore, even when the gate electrode length is 2 μm, a source-drain breakdown voltage of 15 V or higher, which is higher than that of a normal structure TFT, can be obtained. Moreover, the off-state current is one digit or less.

  FIG. 29 is a characteristic diagram showing the relationship between the gate electrode length and the on-state current for each of the LDD type TFT of this embodiment and the TFT having the normal structure. As is clear from FIG. 29, the on-state current of the TFT having the normal structure when the gate electrode length is 5 μm is approximately the same as the on-state current of the LDD type TFT when the gate electrode length is 4 μm. That is, even if the on-current is reduced by using the LDD structure, it can be understood that if the gate electrode length is reduced, an on-current comparable to or higher than that of the normal structure can be obtained. In the LDD type TFT, even if the gate electrode length is 4 μm, there is no problem because a sufficient breakdown voltage can be obtained as shown in FIG. Further, the on-state current of the TFT having the normal structure when the gate electrode length is 4 μm is approximately the same as the on-current of the LDD TFT when the gate electrode length is 3 μm. Thus, even when the gate electrode length is 3 μm, as is clear from FIG. 28, a sufficient breakdown voltage can be obtained, so that there is no problem in this case. In the case of a TFT having a normal structure, if the gate electrode length is less than 4 μm, the source / drain breakdown voltage is insufficient, so that the on-current cannot be measured. On the other hand, with the LDD type TFT of this embodiment, sufficient source / drain breakdown voltage can be obtained even when the thickness is 2 μm, and the on-current in this case becomes very high as shown in FIG. That is, an on-current having a magnitude that cannot be obtained with a TFT having a normal structure can be obtained by, for example, setting the gate electrode length to less than 3 μm in the LDD TFT of this embodiment. As described above, according to this embodiment, both the p-channel and the n-channel are made LDD type, so that the gate electrode length can be both 5 μm or less, desirably 4 μm or less, and more desirably 3 μm or less. Can be realized.

  In addition, since the LDD type TFT also improves the gate-source breakdown voltage, the thickness of the gate insulating film can be reduced, for example, 1000 mm or less. When the gate insulating film is thinned, the channel capacity increases, but the threshold voltage decreases and the on-current increases, so that the operation speed of the TFT circuit can be improved.

  FIG. 30A is a circuit symbol of a CMOS inverter circuit, FIG. 30B is a circuit diagram thereof, and FIG. 30C is a diagram showing it as an equivalent circuit. The operation speed of the LDD type CMOS TFT circuit will be described using these. In general, in the CMOS digital circuit, the input of the next-stage gate is connected to the output of the gate as shown in FIG. Here, simply considering the case of two stages of inverters, the first stage TFTp1 or TFTn1 in FIG. 30B charges and discharges the two channel capacitances of the next stage TFTp2 and TFTn2. The time constant determines the switching speed. In FIG. 30C, the channel length of the LDD type CMOS TFT can be shortened, so that the on-resistance Rp1 of the p-channel TFT and the on-resistance Rn1 of the n-channel TFT are reduced, and the magnitudes of the charging current ip1 and the discharging current in1 are also increased. . Further, the overlap capacitance Cp02 of the p-channel TFT of the next stage and the overlap capacitance Cn02 of the n-channel TFT are also reduced for the above-mentioned reason, and the capacitance C2 of the channel portion is also reduced by shortening the channel length. The capacity value of the load is reduced under the conditions (on state, off state, and bias in the middle). That is, it can be seen that the short channel LDD type CMOS TFT circuit has a shorter charge / discharge time constant than the TFT circuit having the normal structure, and the operation speed is improved. Even if the resistance of the LDD portion is high and the on-resistance Rp1 of the p-channel TFT and the on-resistance Rn1 of the n-channel TFT are slightly higher than those of the normal structure TFT, the value of the time constant Rp1 × (Cp02 + Cn02 + C2) and Rn1 × (Cp02 + Cn02 + C2) ) Is smaller than that of a TFT having a normal structure, the operation speed is improved.

  FIGS. 31A and 31B show examples of transfer characteristics of TFTs actually manufactured with the structure of FIG. Compared with the transfer characteristics 41 and 43 of the normal TFT, the on-current is about 50% to 60% in the transfer characteristics 42 and 44 of the LDD type TFT. This is because the effective channel length of the LDD type TFT is longer than that of the TFT having the same gate electrode length. On the other hand, since the off-current has decreased dramatically, the on / off ratio has improved by an order of magnitude or more. Furthermore, the source-drain breakdown voltage and the source-gate breakdown voltage are greatly improved. Therefore, if the gate electrode length is halved in the LDD type, the on-current becomes equal to or higher, and the off-current can be reduced by one digit or more to improve the breakdown voltage.

  FIG. 32 shows the result of simulating the maximum operating frequency of the shift register circuit based on the characteristics of the prototype LDD TFT. As can be seen from this figure, the short channel LDD type TFT circuit can operate at a higher speed than the TFT circuit having the normal structure. In addition, even if the gate electrode length is about half, the LDD TFT has a much smaller off-current, so that the power consumption of the circuit can be reduced by driving with the same voltage. Further, since the LDD type TFT has much higher source-drain breakdown voltage and source-gate breakdown voltage, a high-voltage circuit can be configured as required. For example, this circuit can easily drive an electro-optical material that cannot be conventionally driven by a TFT circuit because a high drive voltage is required. As such an electro-optic material, for example, polymer dispersed liquid crystal or guest-host liquid crystal can be considered. These liquid crystals have a high threshold voltage, and if these liquid crystals are used for display elements of a liquid crystal display device, the viewing angle can be greatly improved.

  Here, in order to balance the on-current due to the difference in mobility between the n-channel TFT and the p-channel TFT, the gate electrode length of the n-channel TFT is made longer than that of the p-channel TFT. This is because it is desirable to make the on-currents of the two TFTs that are paired at the same level in order to operate the CMOS circuit at the highest speed. In particular, in a CMOS analog switch, since the parallel resistance value of two TFTs at an operating point needs to be a certain value or less, the resistance of a p-channel TFT must be made sufficiently small. From the viewpoint of space efficiency in layout, it is more advantageous to change the channel length at a constant channel width than to change the ratio of the channel width at a constant channel length. However, if the channel length cannot be shortened due to design rule restrictions, the channel length may be fixed with the gate electrode length as the minimum dimension, and the n channel width may be made smaller than the p channel width. In the case of an inverter-only circuit or an analog switch, the channel length and channel width of the p-channel TFT and the n-channel TFT can be determined relatively easily as described above. However, in a circuit where TFTs with the same polarity are arranged in parallel, such as NAND gates and NOR gates, the size of each TFT is optimized according to the purpose of the circuit operation. It is necessary to make it.

33A, 33B, and 33C are a circuit diagram, a pattern diagram, and a wafer cross-sectional view in the case where a CMOS inverter circuit is configured by a single crystal MOSFET. FIG. 34 shows a pattern diagram in the case where a CMOS inverter is constituted by TFTs. In a single crystal MOSFET, a P-Well is required to form an n-channel transistor, and therefore, the p-channel transistor and the n-channel transistor cannot be brought close to each other. Further, the single crystal MOSFET, in order to prevent latch-up or the like to stabilize the potential of the Well or N-Bulk occurs, the P-Well of ^P +, the N-Bulk of ^{N +} stopper (guard bar) It is necessary to provide. This stopper needs to be provided at the boundary between the p-channel transistor and the n-channel transistor. For this reason, the p-channel transistor and the n-channel transistor must be further separated. For this reason, the horizontal length in FIG. 33 is increased, and the area occupied by the circuit is increased. On the other hand, in the TFT, the semiconductor thin films separated into island shapes are completely insulated. Therefore, in the TFT, as shown in FIG. 34 (corresponding to the cross-sectional view of FIG. 27), it is not necessary to provide a stopper, and the lateral length in FIG. 34 can be reduced. Further, the structure is simpler than that of a single crystal MOSFET, and there is an advantage that p-channel transistors and n-channel transistors can be laid out freely. Therefore, if the manufacturing method of the first to fifth embodiments and the LDD type can be used to increase the TFT speed and bring the operation speed closer to that of the single crystal MOSFET, the advantages in the layout can be obtained. By utilizing this, it is possible to replace a circuit in which a single crystal MOSFET has been used so far with a TFT configuration. In many cases, TFTs are arranged in a pattern as shown in FIG. 34. In this case, it is advantageous in terms of layout efficiency to change the channel length while keeping the channel width constant.

7). Seventh Example In this example, optimization of manufacturing process conditions for an LDD type TFT will be described.

  In this embodiment, first, the maximum impurity concentration (dose amount) of the LDD portion is optimized, secondly, the maximum impurity concentration (dose amount) of the source / drain portion is optimized, and third, the LDD length. Has been optimized. Thus, in this embodiment, the high speed and high breakdown voltage of the LDD type TFT are achieved.

First, optimization of the maximum impurity concentration of the LDD part will be described. FIGS. 35 and 36 are characteristic diagrams showing the relationship between the dose amount of the LDD portion, the on-current, the off-current, and the on-off ratio (on-current / off-current). FIG. 37 is a characteristic diagram showing the relationship between the dose amount of the LDD portion and the sheet resistance of the LDD portion. Here, the polycrystalline semiconductor film is prepared according to the first manufacturing method of the background art, and the film thickness is about 500 mm. As is apparent from FIG. 35, if the dose of impurities implanted into the LDD portion is too high, the off current cannot be reduced. For example, in FIG. 35, the off-state current rapidly decreases at 1 × 10 ¹⁴ cm ⁻² or less. If the dose amount of the LDD portion is high, the electric field concentration at the drain end cannot be suppressed, which increases the off-current, and further causes a decrease in the source-drain breakdown voltage and the source-gate breakdown voltage. . Therefore, it is desirable that the dose amount of the LDD portion is 1 × 10 ¹⁴ cm ⁻² or less, and therefore the maximum impurity concentration of the LDD portion is 1 × 10 ¹⁹ cm ⁻³ or less by multiplying this by 10 ^5. It is desirable.

On the other hand, if the dose amount of the LDD portion is too low, the on-current is greatly reduced, as shown in FIG. This is because, as is clear from FIG. 37, when the dose amount of the LDD portion decreases, the sheet resistance of the LDD portion increases. For example, when the dose amount of the LDD portion is less than 1 × 10 ¹³ cm ⁻² , the sheet resistance becomes larger than 250 KΩ / □. When the sheet resistance is increased in this way, for example, when the on-resistance of the transistor is low and is about 10 KΩ to 20 KΩ, the sheet resistance is greatly affected. Therefore, it is desirable that the dose amount of the LDD portion is at least 1 × 10 ¹³ cm ⁻² or more.

Furthermore, as shown in FIG. 36, the on / off ratio has a maximum value between 1 × 10 ¹³ cm ^{−2 and} 1 × 10 ¹⁴ cm ⁻² , for example, the on / off ratio is 2 × 10 ¹³ cm ^−2. It becomes maximum at about 5 × 10 ¹³ cm ⁻² .

As described above, in the LDD portion, the dose amount is about 1 × 10 ¹³ cm ⁻² to 1 × 10 ¹⁴ cm ⁻² and the maximum impurity concentration is in the range of about 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ¹⁹ cm ^−3. It is desirable to be. More preferably, in the LDD portion, the dose amount is about 2 × 10 ¹³ cm ^{−2 to} 5 × 10 ¹³ cm ⁻² and the maximum impurity concentration is about 2 × 10 ¹⁸ cm ^{−3 to} 5 × 10 ¹⁸ cm ^−3. It is desirable that the range be By doing so, the maximum impurity concentration of the LDD portion is optimized.

JP-A-6-102531 discloses that the dose amount of the LDD portion is 1 × 10 ¹⁴ cm ⁻² or less as described above. However, the lower limit value is not disclosed in this prior art, and there is a maximum value of the on / off ratio in the range where the dose amount is 1 × 10 ¹⁴ cm ⁻² to 1 × 10 ¹³ cm ⁻² . There is no suggestion. Further, the idea of optimizing the maximum impurity concentration of the LDD portion is an idea that cannot exist in the technology of the single crystal LDD type MOSFET. This is because, in a single crystal LDD type MOSFET, the LDD length is as short as about 0.1 μm, for example, and therefore the resistance value of this LDD portion does not significantly affect the operation speed. For this reason, in the LDD type MOSFET, it is not necessary to consider the maximum impurity concentration of the LDD portion. On the other hand, in the non-single crystal LDD type TFT, the accelerated diffusion along the crystal grain boundary occurs as described above. Therefore, the LDD length must be longer than that of the single crystal MOSFET. For this reason, the sheet resistance of the LDD part becomes a problem, and the idea of optimizing the maximum impurity concentration of the LDD part is necessary to increase the speed.

Next, optimization of the maximum impurity concentration in the source / drain portion will be described. FIG. 38 is a characteristic diagram showing the relationship between the dose amount of the source / drain portion and the diffusion length, and FIG. 39 shows the relationship between the dose amount of the source / drain portion and the contact resistance in the source / drain portion. A characteristic diagram is shown. As shown in FIG. 38, the diffusion length increases as the dose of impurities implanted into the source / drain portions increases. When the diffusion length increases, for example, impurities in the drain portion or the source portion diffuse into the LDD portion, and the effective LDD length of the LDD portion becomes zero. In the case where the LDD portion is made non-self-aligning using a photoresist, the LDD length is determined by the mask size of the photoresist. For example, consider a case where the dimension of the LDD length determined by this mask is 4 μm. In this embodiment, since the gate electrode length is set to 5 μm or less to shorten the channel, the LDD length cannot be increased so much for miniaturization of the element, and the LDD length is, for example, 4 μm or less. Is desirable. However, in this case, if the dose amount of the source / drain portion becomes larger than 1 × 10 ¹⁶ cm ⁻² , the diffusion length becomes larger than 4 μm as apparent from FIG. Then, impurities in the source / drain portion are diffused by 4 μm in the LDD portion, and the effective LDD length becomes zero. When the effective LDD length becomes zero, the LDD portion does not function, and for example, the source-drain breakdown voltage is significantly reduced. Therefore, the dose of the source / drain part is desirably 1 × 10 ¹⁶ cm ⁻² or less.

On the other hand, when the dose amount of the source / drain portion is lowered, the contact resistance (Rc1, Rc2 in FIG. 56B) in the source / drain portion is increased. One major reason for adopting the LDD type TFT in this embodiment is to reduce the contact resistance. Therefore, the contact resistance is desirably as low as possible, for example, 3 KΩ / 10 μm □ or less. In this case, as shown in FIG. 39, it is desirable that the dose amount of the source / drain portion is 5 × 10 ¹⁴ cm ⁻² or more. Thereby, the contact resistance can be reduced and the speed of the LDD type TFT can be increased.

Further, considering the gate electrode length of 5 μm or less and considering the miniaturization of the element, the LDD length is more preferably in the range of about 1 μm to 2 μm. Accordingly, in this case, as is apparent from FIG. 38, the dose amount of the source / drain region is in the range of about 1 × 10 ¹⁵ cm ^{−2 to} 3 × 10 ¹⁵ cm ⁻² .

As described above, in the source / drain region, the dose amount is about 5 × 10 ¹⁴ cm ⁻² to 1 × 10 ¹⁶ cm ⁻² and the maximum impurity concentration is about 5 × 10 ¹⁹ cm ⁻³ to 1 × 10 ²¹ 1 cm ⁻³ . A range is desirable. More preferably, in the source / drain region, the dose amount is about 1 × 10 ¹⁵ cm ^{−2 to} 3 × 10 ¹⁵ cm ⁻² and the maximum impurity concentration is 1 × 10 ²⁰ cm ^{−3 to} 3 × 10 ²⁰ cm ^−. A range of about ³ is desirable. By doing so, the maximum impurity concentration of the source / drain portion is optimized.

JP-A-6-102531 discloses that the dose amount of the source / drain portion is 1 × 10 ¹⁴ cm ⁻² to 1 × 10 ¹⁷ cm ⁻² as described above. However, the lower limit value of 1 × 10 ¹⁴ cm ⁻² , which is the numerical limit, is merely a limitation that the dose must be higher than that of the LDD portion. As a practical matter, when the dose is 1 × 10 ¹⁴ cm ⁻² , the contact resistance is about 50 KΩ / 10 μm □ as shown in FIG. Then I can't stand it. That is, in this prior art, the gate channel length is 6 μm and the on-resistance is much higher than that of the present embodiment, so there is no interest in reducing such contact resistance. Furthermore, in this prior art, the upper limit value of the dose amount is 1 × 10 ¹⁷ cm ⁻² , but when the dose amount is this value, the diffusion length becomes very large as shown in FIG. . In this conventional technique, which has no interest in shortening the channel and miniaturizing the element, the gate channel length is 6 μm, so the LDD length does not have to be so small, so the upper limit value is thus large. Yes. As described above, this prior art does not disclose or suggest the idea of optimizing the maximum impurity concentration of the source / drain portion in order to operate the LDD type TFT at a high speed and with a high breakdown voltage. . Further, the idea of optimizing the maximum impurity concentration of the source / drain portion is an idea that cannot exist in the technique of the single crystal LDD type MOSFET. This is because, in a single crystal LDD type MOSFET, the phenomenon of accelerated diffusion along the crystal grain boundary does not occur, and therefore, it is not necessary to take much consideration into the impurity diffusion in the source / drain region. As evidence, the LDD length of a single crystal LDD type MOSFET is very short, for example, about 0.1 μm.

Next, optimization of the LDD length of the LDD part will be described. 40 and 41 are characteristic diagrams showing the relationship between the LDD length, the on-current, the off-current, and the source / drain breakdown voltage. In this case, the thickness of the polysilicon thin film in the channel portion and the LDD portion is 450 mm. The dose of the LDD part is 3 × 10 ¹³ cm ⁻² . As shown in FIG. 40, the off-state current rapidly decreases when the LDD length is longer than a certain LDD length, and only gradually decreases even when the LDD length is further increased. On the other hand, the on-current also decreases once at a certain LDD length or more and gradually decreases at a longer LDD length, but the off-current decreases by two digits or more, whereas the on-current is only about half. As shown in FIG. 41, the source-drain breakdown voltage (same as the source-gate breakdown voltage) is also greatly improved when the off-state current rapidly decreases. From these phenomena, it can be seen that the LDD length of all TFTs in the circuit should always be made longer than the length at which the off-state current rapidly decreases. If the LDD length is determined in a self-aligned manner by the sidewalls of the insulating film, the insulating film may be made thicker than the required LDD length. Even in the case of using a manufacturing method in which the LDD length varies depending on the mask alignment, the minimum value of the LDD length variation may be 1 μm or more. However, even if there is a TFT having a slightly large LDD length, the difference in on-current is relatively small as can be seen from FIG. In the case of an analog circuit, it is necessary to design the circuit so as to satisfy the resistance value required for the circuit even in the maximum LDD length expected in advance.

Note that the optimum value of the LDD length can be considered as follows. That is, as described above in the optimization of the source / drain portion, the LDD length is within a range where the effective LDD length does not become zero due to diffusion from the source / drain portion, and in consideration of miniaturization of elements. The shorter it is, the better. Therefore, corresponding to 5 × 10 ¹⁴ cm ⁻² to 1 × 10 ¹⁶ cm ⁻² and 1 × 10 ¹⁵ cm ^{−2 to} 3 × 10 ¹⁵ cm ⁻² which are optimum values of the dose amount of the source / drain portion, The LDD length is preferably in the range of about 0.6 μm to 4 μm, and more preferably in the range of about 1 μm to 2 μm.

  As described above, in a TFT using a non-single-crystal semiconductor thin film, accelerated diffusion occurs along the crystal grain boundary, so that the diffusion coefficient is larger by one digit or more than that of the single-crystal semiconductor. For this reason, the design method used in MOSFETs using single crystal semiconductors cannot be applied to LDD type CMOS TFT circuits using non-single crystal semiconductor thin films. For example, in the case of a polysilicon CMOS TFT, it is desirable to take an LDD length of 1 μm or more for both the p and n channels. However, in a TFT having an LDD length of 1 μm or more, a resistance of about 30 to 100% with respect to the on-resistance of the channel portion is connected in series at both ends of the channel. It is difficult to estimate accurately. In particular, when using a manufacturing method in which the LDD length is determined by non-self-alignment, the LDD length varies greatly from about 1 to 4 μm. Further, in order to improve the TFT characteristics, the film thickness of the channel portion and the LDD portion needs to be reduced to 1000 mm or less, preferably 500 mm or less, so that the sheet resistance of the LDD portion is likely to vary. However, even when the sheet resistance of the LDD portion is maximized and the LDD length is maximized, the TFT must ensure the necessary on-current or the TFT circuit must operate at the necessary speed. A special design method is required. Therefore, a model dedicated to the LDD-type CMOS TFT circuit was developed and simulated, in which the resistance of the LDD portion was greatly changed within the expected range, and as a result, the effective voltage applied to the channel portion was calculated and the on-current was estimated.

  On the other hand, in the manufacturing method, the technique used in MOSFETs using a single crystal semiconductor cannot be used. For example, in the case of a single crystal semiconductor, an LDD structure can be easily formed by using a side wall of a thin thermal oxide film of about 1000 mm, but a side wall having no defect is formed by a thick insulating film of about 1 μm. It is very difficult. Moreover, it is impractical to inject impurities into a thin semiconductor thin film having a thickness of 1000 mm or less from above such a thick insulating film from the viewpoint of throughput and variation. Therefore, a method of overetching the end face of the gate electrode by 1 μm or more or using a photoresist to make the boundary between the LDD part and the source / drain part by non-self-alignment can be considered. These methods have already been used for pixel TFTs on some active matrix substrates. However, these were developed mainly for the purpose of reducing the off-current, and cannot be used as they are for a CMOS TFT circuit intended for high-speed operation due to insufficient on-current. Therefore, in this embodiment, the channel length of both the p-channel TFT and the n-channel TFT is made shorter than before, and the LDD length and the impurity implantation amount of the LDD portion are optimized by focusing on the on-current. Furthermore, in this embodiment, since impurities are implanted from above the thin gate insulating film, it is possible to implant impurities with low energy and high throughput. As described above, an LDD type CMOS TFT suitable for high-speed operation can be realized only by optimizing the manufacturing process.

8). Eighth Embodiment In this embodiment, a method for manufacturing a CMOS circuit using LDD type TFTs will be described. 42A to 42D are process diagrams showing a typical method for manufacturing a polysilicon TFT. First, as shown in FIG. 42A, a polysilicon thin film 72 patterned on an island is thermally oxidized to form a thermally oxidized SiO ₂ film 73, and a gate electrode 74 is formed thereon. Next, as shown in FIG. 42B, the p-channel TFT is covered with a photoresist 75, and an impurity serving as a donor is implanted at a low concentration. Here, phosphorus ions are used. Further, as shown in FIG. 42C, the entire surface of the p-channel TFT and a portion slightly larger than the gate electrode of the n-channel TFT are covered again with photoresist, and an impurity serving as a donor is implanted at a high concentration. This completes the source / drain and channel portion of the n-channel LDD TFT. Similarly, an impurity serving as an acceptor such as boron ion is implanted into the p-channel TFT separately at low and high concentrations. Finally, as shown in FIG. 42D, an interlayer insulating film 76 is deposited, and the metal wiring 77 is patterned.

  In this method, the LDD length can be freely set according to the mask pattern, so that different LDD lengths can be used depending on the circuit. Further, in the case of an element that always has a constant bias, only one of the electrodes can have an LDD structure. For example, only the drain portion can have an LDD structure.

  In addition to this method, there is a method using an insulating film sidewall as a mask as a method of forming an LDD type TFT. For example, before the high concentration ion implantation in FIG. 42C, the gate electrode is covered with an insulating film by thermal oxidation or anodic oxidation, or a new insulating film is formed by a deposition method such as chemical vapor deposition. The surface layer portion of the gate electrode may be covered with an insulating film having a thickness greater than or equal to the LDD length. However, when the deposition method is used, an insulating film is also deposited on the source / drain portions. Therefore, if the insulating film becomes thick, ions must be implanted with a considerably high energy. Here, portions having different resistances are formed in the same semiconductor thin film by ion implantation, but it is also possible to pattern and overlap semiconductor thin films having different resistances in advance. In addition, if the same crystalline semiconductor film is used, the thinner the channel, the better the characteristics.However, in order to reduce the contact resistance of the source / drain, the thicker the film, the better. There is also a method of forming a thick impurity semiconductor thin film.

  The TFT manufacturing method of this embodiment can be applied to all LDD type CMOS TFTs using a non-single crystal semiconductor thin film.

9. Ninth Example The ninth example is an example in which an LDD type TFT manufacturing method is combined with a manufacturing method based on the principle of slowing the generation rate of nuclei and increasing the growth rate of islands. Furthermore, in the ninth embodiment, a solid phase growth method is used to change the deposited film from an amorphous state to a polycrystalline state. Hereinafter, the manufacturing method of the ninth embodiment will be described with reference to FIGS. 1 (A) and 1 (B) and FIGS. 42 (A) to (D).

In the ninth embodiment, an intrinsic silicon film is deposited on the substrate 201 by the LPCVD method. Here, quartz glass was used as the substrate, and the base protective film was not deposited in order to simplify the process. However, as shown in FIG. 25A, a silicon dioxide (SiO ₂ ) film as a base protective film may be deposited by a CVD method or the like before the semiconductor film is formed. As a result, the following effects can be obtained. B) The adhesion of the semiconductor film is improved. B) When low-quality and inexpensive glass is used as a substrate, diffusion of impurity ions (Na, K, Mg, etc.) into the semiconductor film can be prevented. C) Stabilization of nucleation and variation in nucleation speed between substrates can be reduced. That is, the grain size constituting the semiconductor film such as polycrystalline silicon after thermal oxidation can be made constant between the substrates.

As the LPCVD apparatus, the same apparatus as in the first embodiment was used, and an amorphous silicon film was first deposited. The film thickness after deposition is 950 mm. The deposition temperature was 495 ° C., monosilane (SiH ₄ ) having a purity of 99.99% or more was used as the source gas, and the gas was supplied to the reactor at a flow rate of 200 SCCM. The deposition pressure in this case was 1.3 torr, and the deposition rate of the silicon film was 16 Å / min under these conditions. Then, the silicon film thus deposited is patterned to obtain a silicon film 202 (FIG. 1A).

  Next, heat treatment is performed in a nitrogen atmosphere at 600 ° C. for about 24 hours to change the amorphous silicon film into a polycrystalline silicon film (solid phase growth method). However, the heat treatment temperature in this case is not limited to 600 ° C., and is preferably in the range of 500 ° C. to 700 ° C., more preferably in the range of 550 ° C. to 650 ° C.

  Next, a silicon oxide film 203 was formed on the surface of the silicon film 202 patterned by a thermal oxidation method. Thermal oxidation was performed at 1 atm in a 100% oxygen atmosphere at 1000 ° C. As a result, the silicon film was thinned to 600 mm, and a silicon oxide film having a thickness of 700 mm was obtained (FIG. 1B).

Thereafter, a gate electrode 74 is formed on the thermal silicon oxide film (FIG. 42A). Next, the p-channel TFT is covered with a photoresist 75, and an impurity serving as a donor is implanted at a low concentration (FIG. 42B). Further, the entire surface of the p-channel TFT and a portion slightly larger than the gate electrode of the n-channel TFT are covered again with a photoresist, and an impurity serving as a donor is implanted at a high concentration (FIG. 42C). This completes the source / drain and channel portion of the n-channel LDD TFT. Similarly, an impurity serving as an acceptor such as boron ion is implanted into the p-channel TFT separately at low and high concentrations. Finally, as shown in FIG. 42D, an interlayer insulating film 76 is deposited, and the metal wiring 77 is patterned. The LDD length of the LDD TFT produced as described above was 2.0 μm on both the p-channel side and the n-channel side. Further, the dose of the LDD region is 2 × ¹⁰ 13 ^{cm -2,} the dose of the low-resistance source and drain portions (high density area) was 1 × ¹⁰ 15 cm ^-2.

  FIG. 43 shows the transistor characteristics of the LDD TFT produced in this way. The transistor size is L / W = 2.5 μm / 10 μm for an n-channel LDD TFT (hereinafter abbreviated as NMOS LDD), and L / W = 1 for a p-channel LDD TFT (hereinafter abbreviated as PMOS LDD). .5 μm / 10 μm, which optimizes the balance of the current supply capabilities of NMOS LDD and PMOS LDD. As is clear from a comparison between FIG. 2 and FIG. 43, in the ninth embodiment, the off-current is kept very low. In addition, a sufficient on-current can be obtained even when Vgs is 5 V or -5 V, and thus the power supply voltage can be lowered. In this case, the on-current Ion of the NMOS LDD was 152 μA (Vds = Vgs = 5 V). The on-current Ion of the PMOS LDD was 30 μA (Vds = Vgs = −5V).

  According to the present embodiment, both the NMOS LDD and the PMOS LDD have a smaller threshold voltage dependency on Vds, and a short channel can be realized. That is, conventionally, when the channel length is 4 μm or less, the Vds dependence of the threshold voltage is very large and is not suitable for practical use. However, in this embodiment, the characteristics are better than this. In fact, in PMOS LDD, the threshold voltage shift is only about 1 V when Vds = −5 V and Vds = −12 V, and the shift is only about 0.3 V for NMOS LDD. Conventionally, when the channel length is 5 μm or less, the deviation of these threshold voltages due to the difference in Vds was several V or more (L = 4 μm and 5 V or more). Also, the contact resistance could be made sufficiently small. Furthermore, according to the present embodiment, since the film quality of the polysilicon film becomes high, the sheet resistance can be reduced even if the dose is low. That is, the parasitic resistance of the source / drain portion can be reduced, and the on-current can be increased.

  FIG. 44 shows a characteristic diagram showing the relationship between the maximum operating frequency of the shift register circuit using the LDD type TFT of this embodiment and the power supply voltage. As shown in FIG. 44, in this embodiment (Lgaten = 2.5 μm, Lgatep = 1.5 μm), the shift register circuit operates at 10 MHz even when the power supply voltage is 3 V, and the shift register circuit has a sufficient speed even when the power supply voltage is 2 V or less. It was confirmed to work with. On the other hand, in the comparative example (those having a normal structure), the operation speed was very slow when the power supply voltage was 3V, and hardly operated when the power supply voltage was less than 1.5V.

  FIG. 45 shows the contact resistance, source / drain resistance, and LDD resistance measured in this example and the comparative example. The comparative example is prepared by the first manufacturing method of the prior art. As shown in FIG. 45, in this embodiment, the contact resistance, source / drain resistance, and LDD resistance are all lower than in the comparative example. In particular, it is understood that the source / drain resistance is much lower than that of the comparative example (1/5 times to 1/50 times). In particular, in this embodiment, since the polysilicon film has high crystallinity, the sheet resistance of the LDD portion is low even if the dose amount of the LDD portion is low. Conventionally, in the case of the LDD structure, since the sheet resistance of the LDD portion is high, a significant decrease in on-current cannot be avoided. However, in this embodiment, the sheet resistance of the LDD portion is low, so that the parasitic resistance due to the LDD portion is reduced. It is possible to keep it to a minimum.

Here, the relationship between the implantation dose amount and the maximum impurity concentration in the semiconductor film will be described. For example, when the dose amount is N0 (cm ⁻² ) and the impurity concentration N (x) (cm ⁻³ )
N (x) = N0 / ( 2π) 1/2 (ΔRp) × exp {- (X-Rp) 2/2 (ΔRp) 2}
X: Distance from the surface N (x): Concentration at x Rp: Range ΔRp: Range deviation. Therefore, the maximum impurity concentration Nmax is
Nmax = N (X = Rp) = N0 / (2π) ^1/2 (ΔRp)
It becomes. When the thickness of the G-SiO ₂ film of the TFT is 1000 to 1500 mm, the range deviation when ions are implanted into the semiconductor film through the G-SiO ₂ is ΔRp to 400 mm. Therefore, Nmax is
Nmax = N0 / (2π) ^1/2 (ΔRp)
= N0 × 10 ⁵
It becomes. Therefore, in FIG. 45, when the dose amount N0 is 1 × 10 ¹³ cm ⁻² , the maximum impurity concentration Nmax in the semiconductor film is 1 × 10 ¹⁸ cm ⁻³ .

Hereinafter, based on the data of FIG. 45, various calculations for comparing the comparative example and the present example are performed. Since the contact resistance is inversely proportional to the contact hole area, the contact resistance is as follows.
Contact hole size Comparative Example 10 μm × 10 μm 1.4 kΩ 1.2 kΩ
6μm × 6μm 3.9kΩ 3.3kΩ
4μm × 4μm 8.8kΩ 7.5kΩ
2μm × 2μm 35kΩ 30kΩ
1μm × 1μm 140kΩ 120kΩ
First, the parasitic resistance of the NMOS TFT and PMOS TFT used in the shift register shown in FIG.

(1) This embodiment (NMOS)
In the shift register shown in FIG. 44, the dose amount of the LDD portion of the NMOS TFT is 2 × 10 ¹³ cm ⁻² . Therefore, from FIG. 45, the sheet resistance of the LDD portion is 36 kΩ / □. Therefore, the parasitic resistance in this case is calculated as follows.
Contact hole size 100μm2
Contact resistance 1.2kΩ
S / D section resistance (S / D section length ÷ S / D section width) × S / D section sheet resistance
= (7μm / 14μm) × 530Ω / □ = 0.265kΩ
Resistance of LDD part (length of LDD part ÷ width of LDD part) x sheet resistance of LDD part
= (2 μm / 10 μm) × 36 kΩ / □ = 7.2 kΩ
Total parasitic resistance = (Contact resistance + S / D part resistance + LDD part resistance) x 2
(1.2 kΩ + 0.265 kΩ + 7.2 kΩ) × 2
= 17.33 kΩ
Since the on-state channel resistance is 15.56 kΩ, the on-state total resistance Ron is
Ron = 17.33 kΩ + 15.56 kΩ = 32.89 kΩ
It becomes. Therefore, the on-current Ion is
Ion = Vds / Ron = 5 V / 32.89 kΩ = 152 μA
It becomes.

(2) NMOS (comparative example)
Contact resistance 1.4kΩ
Resistance of S / D part (7μm / 14μm) × 2.6kΩ / □ = 1.3kΩ
Resistance of LDD part (2μm / 10μm) × 180kΩ / □ = 36kΩ
Total parasitic resistance = (1.4kΩ + 1.3kΩ + 36kΩ) x 2
= 77.4kΩ
Thus, in the comparative example, even if the channel length is reduced and the channel resistance in the on state is lowered, the total parasitic resistance is large, and therefore the total resistance Ron in the on state cannot be lowered. In contrast, in this embodiment, the parasitic resistance does not increase even if LDD is used. This tendency is particularly noticeable with PMOS LDD.

(3) PMOS (this embodiment)
Contact resistance 1.18kΩ
Resistance of S / D part (7μm / 14μm) × 50kΩ = 0.025kΩ
Resistance of LDD part (2μm / 10μm) × 13kΩ = 2.6kΩ
Total parasitic resistance = (1.18 kΩ + 0.025 kΩ + 2.6 kΩ) × 2
= 7.61kΩ
(4) PMOS (comparative example)
Contact resistance 1.4kΩ
p + S / D resistance (7 μm / 14 μm) × 2.6 kΩ = 1.3 kΩ
p-S / D resistance (2 μm / 10 μm) × 375 kΩ = 75 kΩ
Total parasitic resistance = (1.4kΩ + 1.3kΩ + 75kΩ) x 2
= 155.4kΩ
Thus, in the case of PMOS, the difference between the total parasitic resistance of the present embodiment and the total parasitic resistance of the comparative example is particularly significant.

Next, the parasitic resistance when the contact hole becomes smaller due to miniaturization is calculated. As an example, consider the case where the contact size is 2 μm × 2 μm = 4 μm ² .

(5) Example (LDD structure)
As described above, reduction of contact resistance becomes an important issue when miniaturization progresses. Therefore, here, the contact portion is provided in the high concentration source / drain portion, the dose amount of the high concentration portion is 3 × 10 ¹⁵ cm ^−2, and the dose amount of the LDD portion (low concentration portion) is 2 × 10 ¹³ cm ^{−. 2} . The LDD length is assumed to be 1 μm. First, as can be seen from FIG. 39, when the dose amount of the source / drain portion is 3 × 10 ¹⁵ cm ⁻² , the contact resistance of the contact of 10 μm × 10 μm is reduced to about 0.1 KΩ. Therefore, the contact resistance of 2 μm × 2 μm is 2.5 KΩ.

Contact resistance ^{(100μm 2 / 4μm 2) ×} 0.1kΩ = 2.5kΩ
Next, the resistance values of the high concentration source / drain portion and the LDD portion are obtained. This will be described with reference to the model of FIG. The channel width is 10 μm and the channel length (gate length) is 2.5 μm. The distance from the end of the gate electrode to the center of the contact hole is 4.5 μm, and 1.0 μm of this is the LDD length. Since the LDD portion has a dose of 2 × 10 ¹³ cm ⁻² , the sheet resistance is 36 KΩ / □ from FIG. Since the LDD length is 1.0 μm and the width of the LDD part is 10 μm, the resistance of the LDD part is
1μm / 10μm × 36KΩ = 3.6KΩ
It becomes. On the other hand, since the dose amount of the high concentration source / drain portion is 3 × 10 ¹⁵ cm ^−2, which is three times as large as the example shown in FIG. 45, the sheet resistance is 1/3 or less of 30 ohm / □. The length of the high concentration source / drain portion is obtained by subtracting the LDD length (1 μm) from the distance (4.5 μm) to the center of the contact hole. Therefore, the source / drain resistance is
(4.5 μm-1.0 μm) / 10 μm × 530Ω / 3 = 0.062 kΩ
It becomes. Therefore,
Total parasitic resistance = (2.5 kΩ + 0.062 kΩ + 3.6 kΩ) × 2
= 12.32 kΩ
On-state channel resistance = 15.56 kΩ
Ron = 12.32 kΩ + 15.56 kΩ = 27.88 kΩ
(6) Comparative example (normal self-aligned structure)
On the other hand, in the normal self-aligned structure, the following results are obtained. As described above, in the normal structure, in order to avoid problems such as punch-through, the minimum channel length is 5 μm, and the implantation dose amount of the source / drain portion cannot be 1 × 10 ¹⁵ cm ⁻² or less. At this time, the contact resistance is as shown in FIG.
Contact resistance ^{(100μm 2 / 4μm 2) ×} 1.2kΩ = 30kΩ
It becomes. Assuming the same situation as the above (5), the length of the high concentration source / drain portion is 4.5 μm, so the length to the center of the contact hole is 4.5 μm.
Resistance of S / D section = 4.5 μm / 10 μm × 530Ω = 0.24 kΩ
It is. Therefore,
Total parasitic resistance = (30 kΩ + 0.24 kΩ) × 2 = 60.48 kΩ
It is. On the other hand, since the channel length is as long as 5 μm, the channel resistance in the on state doubles from 15.56 kΩ when the channel length is 2.5 μm, and is about 33 kΩ.

On-state channel resistance = 33 kΩ
as a result,
Ron = 60.48 kΩ + 33 kΩ = 93.48 kΩ
It becomes.

  As described above, when the miniaturization progresses and the contact becomes smaller, the total parasitic resistance in the LDD structure is significantly reduced as compared with the case of the normal structure. In addition, since the channel length is short and the channel resistance is low, the channel resistance also decreases, and Ron is further effectively reduced.

  Next, as shown in FIG. 29 described above, a calculation is performed to verify why the LDD structure has more on-current than the normal structure. The following calculation was performed using the model shown in FIG.

(7) This example (when L = 2.5 μm with LDD structure)
The contact hole size is 6 μm × 8 μm = 48 μm 2, the S / D part dose is 3 × 10 ¹⁵ cm ⁻² , the LDD part dose is 2 × 10 ¹³ cm ⁻² , and the LDD length Is assumed to be 1.0 μm.
Contact resistance ^{(100μm 2 / 48μm 2) ×} 0.1kΩ
= 0.208kΩ
Resistance of S / D part (4.5μm-1.0μm) / 10μm × (530Ω / 3)
= 0.062kΩ
Resistance of LDD part (1μm / 10μm) × 36kΩ = 3.6kΩ
Total parasitic resistance = (0.208 kΩ + 0.062 kΩ + 3.6 kΩ) × 2
= 7.74kΩ
On-state channel resistance (L / W = 2.5 μm / 10 μm) = 15.56 kΩ
Therefore, the total resistance in the on state is
Ron = 7.74 kΩ + 15.56 kΩ = 23.3 kΩ
It becomes.

(8) Comparative example (normal structure)
Minimum channel length is 5 [mu] m, the contact resistance (100μm ² / 48μm ²⁾ to consider the case dose of S / D portion is 1 × ¹⁰ 15 ^{cm -2} in order to avoid punch-through × 1.2k = 2. 5kΩ
Length of S / D part = Length to contact hole center = 4.5μm
Resistance of S / D part (4.5μm-1.0μm) / 10μm × 530Ω
= 0.24 kΩ
Total parasitic resistance = (2.5 kΩ + 0.24 kΩ) x 2
= 5.48kΩ
On-state channel resistance (L / W = 5 μm / 10 μm) = 33 kΩ
Therefore, the total resistance in the on state is
Ron = 5.48kΩ + 33kΩ = 38.48kΩ
It becomes.

  As described above, the total parasitic resistance of the LDD structure is somewhat larger as 7.74 kΩ, but the total ON-state resistance can be reduced by 40%.

  In the ninth embodiment, in order to set the maximum process temperature to 1000 ° C., an amorphous semiconductor film (a-Si) is deposited at a deposition temperature of 495 ° C. and a deposition rate of 16 Å / min, and then solid phase growth is performed. After performing crystallization, thermal oxidation was performed. However, the solid phase growth method has poor throughput and is impractical from the viewpoint of manufacturing. For this reason, when solid phase growth is not performed, the same result as that obtained by solid phase growth can be obtained by increasing the thermal oxidation temperature by about 100 ° C. That is, when solid phase growth is not performed in this embodiment, the thermal oxidation temperature may be set to 1100 ° C. When a CMOS circuit that operates at a high speed and lowers the process temperature is made of TFT, the deposition of the amorphous film is ideally 530 ° C. or lower as shown in FIG. In general, a film obtained by solid phase growth has many defects in the crystal. However, when a film deposited at a temperature of 530 ° C. or lower is crystallized, defects in the crystallized film are reduced. This is not only in FIG. 16 but also in FIG. 45, when impurity atoms such as B (boron) are implanted into the semiconductor film (polycrystalline silicon film) obtained in this embodiment, the sheet of the source / drain portion This is also demonstrated by the fact that the resistance is significantly reduced from 2.6 kΩ / □ in the comparative example to 50 ohm / □. After the implantation of B (boron) atoms, the implanted impurity atoms are activated by heat treatment at 800 ° C. to 1000 ° C. (in this example, 20 minutes in a nitrogen atmosphere at 1000 ° C. in this example) To do). When activation is performed at 1000 ° C. for 20 minutes, almost 100% of the implanted impurity atoms are activated. Thus, although the comparative example and the present example have the same impurity dose (see FIG. 45) and the activation rate is almost 100%, the value of the source / drain resistance as shown in FIG. There is a difference. The reason is that this example has fewer crystal defects than the comparative example. That is, the semiconductor film according to this example has fewer crystal defects than the comparative example. This reduces the off-state leakage current (see FIG. 16), increases the collision time of the electrical conductor (holes in PMOS, electrons in NMOS), and reduces the probability of scattering due to crystal defects, etc. -The drain resistance is reduced. In this way, regardless of whether solid phase growth is performed before thermal oxidation, crystal defects are greatly reduced when the amorphous film is at 530 ° C. or lower. Needless to say, in order to increase the grain of the polycrystalline film, the deposition rate is preferably 6 Å / min or more, and ideally more preferably 12 Å / min or more in consideration of mass productivity and transistor characteristics. This increases the grain and increases the mobility.

After all, the CMOS circuit using the LDD type TFT of the manufacturing method using the principle of slowing the nucleus generation speed and fast island growth realizes high-speed operation for the following reason.
(A) The semiconductor film is composed of large-area grains (high mobility), and there are few defects in the crystal (the leakage current in the off state is small and the steepness when changing from the off state to the on state is excellent). The channel resistance Rch (on) at the time decreases.
(B) For the same reason as described above, the sheet resistance of the LDD part and the source / drain part decreases. That is, increase in parasitic resistance can be suppressed to a minimum even if LDD is used.
(C) The contact resistance can be kept low even when miniaturized.
(D) It is possible to shorten the channel.
(E) The gate insulating film can be thinned.
(F) Yj (overlapping portion between source / drain and gate electrode) can be reduced.

  The on-current increases due to the above (A) to (E), and the transistor capacitance is reduced due to (D) and (F).

Furthermore, in the LDD TFT manufacturing method using the principle of slowing the nucleus generation rate and increasing island growth, the setting range of various parameters in manufacturing can be widened. As described in the seventh embodiment, the range (especially the lower limit value) of the dose amount of the LDD portion is determined by the condition that the on / off ratio of the transistor is optimized. On the other hand, in the ninth embodiment, as shown in FIG. 45, the sheet resistance is 1/5 or less of the conventional value, so when trying to obtain the same sheet resistance, the lower limit value of the dose amount Can also be 1/5 or less. That is, in the ninth embodiment, the dose amount of the LDD portion can be lowered to about 2 × 10 ¹² cm ⁻² . Thereby, in the LDD type TFT using the principle of slowing the nucleus generation rate and fast island growth, the preferable range of the impurity dose of the LDD part is 2 × 10 ¹² cm ⁻² to 1 × 10 ¹⁴ cm ^−2. It becomes. A preferable range of the maximum impurity concentration is 2 × 10 ¹⁷ cm ⁻³ to 1 × 10 ¹⁹ cm ⁻³ .

  In the seventh embodiment described above (LDD type TFT that does not use the principle of slowing the nucleus generation rate and fast island growth), the LDD length range is along the grain boundary from the high concentration region. Due to the limitation of accelerated diffusion, the range was 0.6 μm to 4 μm. On the other hand, when the principle of slowing the nucleus generation rate and fast island growth is used, the grain boundary is remarkably reduced (see FIG. 4 and FIG. 5 for comparison), so that the accelerated diffusion is also reduced. Therefore, if the principle of slowing the nucleus generation rate and fast island growth is used, the minimum LDD length can be reduced to about 0.3 μm. That is, in the LDD type TFT using the principle of slowing the nucleus generation rate and fast island growth, the desirable range of the LDD length is 0.3 μm to 4 μm. Needless to say, the fact that the LDD length can be shortened also means that the value of the parasitic resistance based on the LDD portion is lowered.

  Next, the positional relationship between the LDD portions 216 and 218 and the contact holes 232 and 234 will be described using the model of FIG. As described above, the LDD length is preferably shorter as long as the LDD length does not become zero due to enhanced diffusion from the high concentration source / drain portion. On the other hand, the positions of the contact holes 232 and 234 are preferably closer to the gate electrode 210 in order to reduce the sheet resistance of the source part 212 and the drain part 214 or to increase the degree of circuit integration. On the other hand, in order to reduce the contact resistance, it is desirable that the contact holes 232 and 234 are opened in the high concentration source / drain portions 212 and 214. Therefore, the edges 224 and 226 closest to the gate electrode 210 of the contact holes 232 and 234 are boundaries between the LDD portions 216 and 218 and the source / drain portions 212 and 214 (boundaries 220 and 222 indicated by dotted lines in FIG. 46). Ideally). This is because the contact resistance is reduced, the resistance of the source / drain portion is reduced, and the element can be miniaturized. However, in reality, since mask displacement or the like occurs, it is very difficult to match the end sides 224 and 226 of the contact hole with the boundaries 220 and 222. In this case, the contact holes 232 and 234 may be slightly inside the LDD portions 216 and 218 as shown in FIG. Alternatively, or conversely, it may be positioned slightly outside the LDD portions 216, 218. According to an experiment by the present inventor, it has been found that there is no problem even if the edges 224 and 226 and the boundaries 220 and 222 are shifted and about 20% of the contact hole area enters the LDD portion. In the example of FIG. 46, since the length of the contact hole is 6.0 μm, even if the contact hole enters the inside of the LDD portion by 1.2 μm, the contact resistance does not increase greatly. For example, consider a case where the end sides 224, 226 and the boundaries 220, 222 match in the mask. In this case, when the contact hole 232 enters the inside of the LDD portion 216 by 1.2 μm on the source portion side due to mask displacement or the like, the contact hole 234 is formed on the outside of the LDD portion 218. Only 2 μm will come out. Thus, the distance from the end side 224 to the gate electrode 210 is 0.8 μm, and the distance from the end side 226 to the gate electrode 210 is 3.2 μm.

The sum of the LDD length Lldds on the source side and the LDD length Llddd on the drain side (Lldds + Llddd) is the distance Lconts from the contact hole edge 224 on the source side to the gate electrode 210 and the gate hole 210 from the contact hole edge 226 on the drain side. Ideally, it is equal to the sum (Lconts + Lcontd) with the distance Lcontd to the electrode 210. In order to reduce parasitic resistance,
0.8 × Lldds ≦ Lconts ≦ 1.2 × Lldds
0.8 × Llddd ≦ Lcontd ≦ 1.2 × Llddd
It is desirable that

In this embodiment, both the NMOS and PMOS constituting the COMS TFT are configured with an LDD type structure. However, as shown in FIG. 45, when a semiconductor film is prepared by a deposition method that slows nucleation and accelerates island growth, the source / drain resistance of the PMOS is 50Ω even at a dose of 1 × 10 ¹⁵ cm ^−2. / □ and 2.6 kΩ / □ of the comparative example are 1/50 or less. The resistance of the LDD portion of the PMOS is 13 kΩ / □, which is about 1/30 of the 375 kΩ / □ of the comparative example. As described above, this is because the semiconductor film obtained in this embodiment is composed of large crystal grains and has few intra-crystal defects. In the case of using such a high-quality semiconductor film, at least the PMOS side, the source / drain portion into which the acceptor is implanted at a high concentration can be omitted, and the entire region of the source / drain portion can be made a low concentration region. That is, the NMOS side constituting the CMOS has an LDD structure like the NMOS of FIG. 26, and the PMOS side has a normal self-aligned structure like the PMOS of FIG. 27, and the dose amount of the acceptor simply injected into the source / drain regions. Is reduced to a low concentration. The parasitic resistance of the transistor is the resistance of the source / drain and the contact resistance, but in this embodiment, the sheet resistance is sufficiently low even with low concentration impurity implantation. In addition, the contact resistance is a P-type thin film on the bonding surface in contact with the semiconductor film such as aluminum (Al), indium (In), indium tin oxide (ITO), palladium (Pd), platinum (Pt), etc. as the wiring material. When a conductive material for forming a semiconductor layer is used, contact resistance can be kept low. This is because such metal particles form a P-type semiconductor layer together with silicon, and therefore have the same electrical characteristics as the source / drain of a P-type semiconductor into which boron (B) or the like is implanted, and good contact characteristics. It is for showing. Eventually, the source / drain portion of the PMOS is formed with a normal self-aligned structure, and its concentration is changed from 5 × 10 ¹⁷ cm ⁻³ (dose amount 5 × 10 ¹² cm ⁻² ) to 5 × 10 ¹⁹ cm ⁻³ (dose). If the amount is 5 × 10 ¹⁴ cm ⁻² ), a CMOS circuit capable of high-speed operation can be obtained without using the LDD type. The maximum impurity concentration of the source / drain portion of the PMOS is preferably changed depending on the gate length Lgatep. If the gate length is 4 μm or more, the maximum impurity concentration of the source / drain portion of the PMOS is 5 × 10 ¹⁸ cm ⁻³ (dose amount 5 × 10 ¹³ cm ⁻² ) to 5 × 10 ¹⁹ cm ⁻³ (dose amount 5 × 10). ¹⁴ cm ⁻² ) is preferable. When the gate length is 4 μm or less, 5 × 10 ¹⁷ cm ⁻³ (dose amount 5 × 10 ¹² cm ⁻² ) to 5 × 10 ¹⁸ cm ⁻³ (dose amount 5 × 10 ¹³ cm ⁻² ) is preferable. In this way, reducing the concentration of the source / drain region over the entire area using only PMOS reduces the number of photo processes by one compared to the production of PMOS LDD type TFTs, which not only simplifies the process but also integrates the circuit. However, it becomes much easier.

10. Tenth Embodiment In this embodiment, a case where the present invention is applied to an active matrix liquid crystal display device will be described. As shown in FIG. 47, the active matrix liquid crystal display device includes three parts, an active matrix part 81, a data driver part 82, and a scan driver part 83. Of these, the active matrix portion includes a signal line 90, a scanning line 91, a pixel TFT 92 provided at the intersection thereof, a liquid crystal capacitor 94 connected to the drain end of the pixel TFT, and a holding capacitor 93. Since this pixel TFT is of the LDD type like the peripheral drive circuit, it can realize a sufficiently high off-resistance compared to the liquid crystal and can prevent the occurrence of crosstalk. The liquid crystal material of the active matrix portion is not limited to the TN type as long as it is a field effect liquid crystal, and various materials can be used. For example, a polymer dispersion type liquid crystal or a guest / host type liquid crystal having a relatively high driving voltage can be easily driven by a high withstand voltage LDD type CMOS TFT circuit.

  The data driver unit includes a shift register 84, a level shifter 85, a video line 87, and an analog switch 86. When writing video signals serially for each signal line, the number of stages of the shift register is equal to the number of signal lines. However, when simultaneously writing to n signal lines, it is 1 / n of the number of signal lines. Good. In many cases, a liquid crystal display device using a color filter has a number of video lines that are an integral multiple of the number of colors of the color filter in order to eliminate color rotation of a video signal applied to the video line. The analog switch 86 needs a high gate voltage because it needs to write a video signal to the signal line at a very high speed. Therefore, the level shifter 85 converts the sampling pulse into a sufficiently high voltage. The scan driver unit 83 includes a shift register 88 and a level shifter 89, and selects a scan line of the active matrix unit in synchronization with the video signal. Since these peripheral drive circuits can be increased in speed by being composed of LDD type CMOS TFT circuits, a sufficient operation speed can be obtained even if the drive voltage is lowered. For example, a conventional shift register circuit using a TFT requires a high drive voltage of about 10 V, but a shift register circuit using an LDD type CMOS TFT of the present invention has a sufficient operating speed even at a voltage of TTL level, that is, 5 V. can get. Then, all the outputs of the external timing controller can be at the TTL level, and the circuit can be downsized and the power consumption can be reduced. Furthermore, if the controller is integrally formed using TFTs, the size can be further reduced.

  Here, the circuit diagram of the dot-sequential analog type active matrix liquid crystal display device is used. However, the LDD type CMOS TFT circuit can be applied to the line-sequential analog type and digital type to increase the speed.

  Next, a specific pixel pattern will be described. 48A and 48B are a plan view and a cross-sectional view of a pixel portion of a liquid crystal display device using LDD TFTs as pixels. In general, a liquid crystal display device needs to have a large pixel aperture to obtain a bright screen. However, if the resolution is increased, the pixel pitch becomes smaller. is important. In this example, the gate wiring 102 is used as it is as a gate electrode, and the pixel TFT is arranged under the metal wiring 103 so that the pixel TFT does not reduce the opening area. Also, the storage capacitor is formed by extending the semiconductor thin film 104 under the previous gate wiring so as not to reduce the opening area. Further, since the metal wiring 103 is sandwiched between the first interlayer insulating film 105 and the second interlayer insulating film 106, even if the transparent conductive film 101 that directly drives the liquid crystal overlaps both the gate wiring and the metal wiring, a short circuit is caused. do not do. When an opaque film such as a refractory metal is used for the gate wiring 102, it functions as a light-shielding layer together with the metal wiring, so that a black matrix usually formed on the counter substrate is not required, and a higher aperture ratio can be achieved. .

  Although the present embodiment has been described using the liquid crystal display device, the present LDD type CMOS TFT can also be used for other flat panel displays. For example, an active matrix display device can be realized using an electro-optic material other than liquid crystal. In particular, since the LDD type TFT circuit has a high breakdown voltage, it is suitable for driving a material having a high driving voltage. Further, if an active matrix switching circuit is an electro-optic conversion circuit, an EL display, a plasma display, or the like can be realized.

11. Eleventh Embodiment In this embodiment, a specific example of a CMOS circuit using an LDD type TFT will be described. 49A and 49B are circuit diagrams and timing charts of a bidirectional shift register. As shown in FIG. 49A, this shift register is a combination of four clocked gates. The arrows and symbols attached to each gate indicate that the signal operates as an inverter when the signal of the symbol is at a high level, and enters a high impedance state when the signal at the low level. If R is at a high level and L is at a low level, a right shift is performed, and if R is at a low level and L is at a high level, a left shift is performed. CL is a clock signal that determines the timing to shift data, and the bar on CL indicates that the phase is 180 degrees out of phase. Next, the operation of this circuit will be described with reference to FIG. First, in the case of a right shift, among the four gates, the gates with the symbol L are always in a high impedance state, so that data is sent through the remaining three gates. When a waveform as shown in the figure is applied to the leftmost DR portion, the same waveform is sent to the right every half cycle of the clock. As a result, a pulse corresponding to a half cycle of the clock as shown in the figure is output to P and Q. Similarly, in the case of the left shift, of the four gates, the gates with the symbol R are always in a high impedance state, so that data is sent through the remaining three gates. When a waveform as shown in the figure is applied to the rightmost DL portion, the same waveform is sent to the left every half cycle of the clock. As a result, a pulse corresponding to a half cycle of the clock as shown in the figure is output to P and Q.

  In general, the bidirectional shift register has a drawback that the operation speed is slower than that of the unidirectional shift register. However, when the LDD type CMOS TFT circuit of the present invention is used, the bidirectional shift register operates at an operation speed equivalent to or higher than the unidirectional. Is obtained. When a bidirectional shift register is used in a liquid crystal display device, the screen can be easily reversed left and right. For example, a front projector and a rear projector can be used separately in the same device. In the case of a liquid crystal projector that transmits R, G, and B light through three liquid crystal display devices and synthesizes and projects the light, at least one of the three liquid crystal display devices is required due to optical system limitations. Although it is necessary to display a reverse image, the system can be configured using three identical liquid crystal display devices by using this bidirectional shift register.

  50A and 50B are a circuit diagram and a timing chart of a unidirectional shift register. As shown in FIG. 50A, in this example, two series of shift registers are used. The outputs of these two shift registers are taken out through a NOR gate with a narrow pulse width. In FIG. 50B, the two clock signals CL2 are delayed in phase by 90 degrees with respect to CL1. When waveforms such as D1 and D2 are applied to the left end of this circuit, the two series of shift registers shift the waveform to the right every half cycle of each clock signal. As a result, waveforms as indicated by P and Q are output to the output of the NOR gate. In this circuit, the frequency of the output pulse can be made four times the clock frequency, resulting in a very high speed circuit. When this circuit is constituted by the LDD type CMOS TFT of the present invention, a high-speed data driver compatible with HDTV can be realized.

  51A and 51B are an example of a circuit diagram and timing chart of a level shifter. In the liquid crystal display device, it is used to convert the voltages of the logic portion and the portion that drives the active matrix. As shown in FIG. 51A, an input signal and an inverted signal of the input signal are input to two TFTs of n-channel and p-channel, respectively. On the other hand, the output portions OUT1 and OUT2 are taken out from the connection portion between the two p-channel TFTs connected in cascade and the TFT of the input portion. The two p-channel TFTs connected in cascade are connected to a power supply voltage VDD higher than the input signal level. As shown in FIG. 51B, when a VCC level input signal IN is applied, a VDD level signal is output to the two outputs OUT1 and OUT2. In this circuit, the p-channel TFT is also connected to the input side, and the current flowing through the p-channel TFT on the VDD side is limited to prevent malfunction. In general, the level shifter must operate at a sufficiently high speed even with a low input voltage, and the withstand voltage between the source and the drain when the output voltage is increased must be sufficient. However, the LDD type TFT of the present invention is sufficient for both the p and n channels. Since the operation speed and breakdown voltage can be realized, the performance of the level shifter TFT circuit is also greatly improved.

  FIG. 52 is an example of a circuit diagram of a line sequential analog data driver. The analog buffer circuit allows a current to flow for a long time with a DC bias, so far it has been difficult to realize the TFT circuit from the viewpoint of reliability. However, since the LDD type CMOS TFT has good reliability and its characteristics hardly change even when a current is continuously applied for a long period of time, a driver using an analog buffer circuit can be realized. The video signal on the video line Vid is temporarily held in the analog latch A, and is sent to the analog latch B by a latch pulse LP at a certain timing. Since the analog latch B always drives the analog buffer, sufficient writing can be performed on a signal line of a considerably large liquid crystal display device.

FIG. 53 is an example of a circuit diagram of a 2-bit digital data driver. In general, an n-bit digital driver has n digital input signals D1, D2,. . . The signal of Dn is written to n sets of latches A, and written to n sets of latches B at a certain timing. The data of the latch B is selected by the decoder from one of 2 ⁿ analog switches, and 2 ⁿ driving voltages V1, V2,. . . One voltage of Vn is written to the signal line. In the case of multiple bits, a part of the driving voltage may be complemented and generated internally. To simplify the driver circuit, frame rate control method that complements gradation using multiple frames, area gradation method that complements gradation with multiple pixels, etc., or pulse width modulation May be used for D / A conversion. Since the LDD type CMOS TFT circuit of the present invention can operate such a digital circuit at a high speed, a high-definition data display can be easily realized.

  By combining these circuits, a more complicated circuit can be configured. For example, a timing controller that supplies a timing signal to the peripheral drive circuit of the display device can also be constituted by the high-speed CMOS TFT circuit of the present invention. Further, since the LDD type CMOS TFT has high reliability without fear of causing breakdown, it is easy to configure an OP amplifier, a digital / analog conversion circuit, an analog / digital conversion circuit, a memory circuit, and the like. As a result, a complicated system such as a video signal amplifying device and a signal frequency converting device can be integrally formed with a TFT in a display device that can only include a peripheral driving circuit.

12 Twelfth Embodiment In this embodiment, a display system using an LDD type CMOS TFT will be described. FIG. 54 is a block diagram showing a display system using an active matrix liquid crystal display device. A video signal and a timing signal are simultaneously output from a video signal generation circuit such as a computer or a video source. Of these, the video signal needs to be amplified for driving the liquid crystal, so a dedicated video signal amplifier circuit is required. This amplifier circuit also performs frequency conversion and γ correction of the video signal as necessary. When performing frequency conversion of an analog video signal, an A / D conversion circuit, a memory circuit, a D / A conversion circuit, and the like are also required. On the other hand, the timing controller generates timing signals for driving the data driver and the scanning driver. Thus, the original performance of the liquid crystal display device can be exhibited by giving an optimum signal to the liquid crystal display device. Since the liquid crystal display device using the LDD type CMOS TFT circuit of the present invention operates at high speed, the video signal amplifier circuit does not need to reduce the frequency so much. In addition, since the logic unit can be driven at a low voltage, for example, all the output levels of the timing controller can be set to the TTL level. Further, part or all of the video signal amplifier circuit and the timing controller can be integrally formed with TFTs, and the video signal generator itself can be integrally formed with TFTs. In this way, by forming a complicated system with a high-speed TFT circuit, it becomes possible to realize ultra-compact portable information devices that were impossible in the past, and it is possible to apply TFT circuits to other than display systems. Sex will also spread.

  In addition, this invention is not limited to the said Example, A various deformation | transformation implementation is possible within the range of the summary of this invention.

  For example, the thin film semiconductor device of the present invention can be widely used not only in a liquid crystal display device but also in a digital circuit, an analog circuit, or the like in which a conventional single crystal MOSFET has been used. For example, FIG. 55 shows an example of mobility and on-current for each of an amorphous TFT, a conventional polycrystalline TFT (LDD and normal structure), this embodiment (LDD and normal structure), and a single crystal MOSFET. It is. As is clear from FIG. 55, according to this example, the on-current is a value not inferior to that of the single crystal MOSFET. Since the thin film semiconductor device is formed on an insulating material, noise from the substrate is hardly transmitted. Therefore, if the thin film semiconductor device of the present invention is used in a high performance analog circuit in which a single crystal MOSFET has been used, the performance can be remarkably improved. In terms of the degree of integration, the thin film semiconductor device of the present invention is not inferior to a single crystal MOSFET as can be understood by comparing FIG. 33B and FIG. As described above, the thin film semiconductor device of the present invention can be used for circuits in a very wide range of fields.

1A to 1D are manufacturing process diagrams of a thin film semiconductor device according to the first embodiment. It is a figure which shows the transistor characteristic of the n channel TFT and p channel TFT by a 1st Example. It is a characteristic view which shows the relationship between deposition temperature, deposition speed, and mobility. 3 is an electron microscope (SEM) photograph showing a crystal structure of a silicon film (deposition temperature = 510 ° C. after thermal oxidation) of a thin film semiconductor device. 3 is an electron microscope (SEM) photograph showing a crystal structure of a silicon film (deposition temperature = 600 ° C. after thermal oxidation) of a thin film semiconductor device. 6A and 6B are diagrams showing the distribution of grain areas. 7A to 7E are diagrams for explaining the principle of the present invention. 8A to 8H are also diagrams for explaining the principle of the present invention. It is an electron microscope (SEM) photograph which shows the amorphous state of the silicon film (Before thermal oxidation, deposition temperature = 510 degreeC) of a thin film semiconductor device. 2 is an electron microscope (AFM) photograph showing an amorphous state of a silicon film (before thermal oxidation, deposition temperature = 510 ° C.) of a thin film semiconductor device. 4 is an electron microscope (AFM) photograph showing an amorphous state of a silicon film (before thermal oxidation, deposition temperature = 570 ° C.) of a thin film semiconductor device. 4 is an electron microscope (SEM) photograph showing a crystal structure of a silicon film (deposition temperature = 570 ° C. after thermal oxidation) of a thin film semiconductor device. It is an electron microscope (SEM) photograph which shows the crystal structure of the silicon film (Before thermal oxidation, deposition temperature = 600 degreeC) of a thin film semiconductor device. It is a characteristic view which shows the relationship between deposition temperature and an average grain area. It is a figure which shows the data which determines the characteristic view of FIG. It is a characteristic view which shows the relationship between deposition temperature and the leakage current at the time of OFF. It is a figure which shows the source-gate breakdown voltage of the comparative example. It is a characteristic view which shows the relationship between thermal oxidation temperature and on-current. It is an electron microscope (SEM) photograph which shows the state of the MOS interface of the thin film semiconductor device of a present Example in case a thermal oxidation temperature is 1160 degreeC. It is an electron microscope (SEM) photograph which shows the state of the MOS interface of the thin film semiconductor device of a present Example in case a thermal oxidation temperature is 1050 degreeC. It is an electron microscope (SEM) photograph which shows the state of the MOS interface of the thin film semiconductor device of a present Example in case a thermal oxidation temperature is 900 degreeC. It is an electron microscope (SEM) photograph which shows the state of the MOS interface of the thin film semiconductor device of the comparative example in case a thermal oxidation temperature is 1160 degreeC. It is an electron microscope (SEM) photograph which shows the state of the MOS interface of the thin film semiconductor device of the comparative example in case a thermal oxidation temperature is 1050 degreeC. It is an electron microscope (SEM) photograph which shows the state of the MOS interface of the thin film semiconductor device of the comparative example in case a thermal oxidation temperature is 900 degreeC. 25A to 25D are manufacturing process diagrams of the thin film semiconductor device according to the fifth embodiment. It is sectional drawing of a LDD type TFT. It is sectional drawing of TFT of a normal structure. It is a characteristic view showing the relationship between the gate electrode length and the source / drain breakdown voltage of the LDD type TFT and the TFT having a normal structure. It is a characteristic view showing the relationship between the gate electrode length and the on-current of the LDD type TFT and the TFT having a normal structure. 30A to 30C are diagrams for explaining the operation of the CMOS inverter circuit. 31A and 31B are diagrams illustrating transfer characteristics of a thin film transistor. It is a figure which shows the highest operating frequency of a shift register circuit. 33A to 33C are a circuit diagram, a pattern diagram, and a wafer sectional view in the case where a CMOS inverter circuit is constituted by a single crystal MOSFET. It is a pattern figure at the time of comprising a CMOS inverter by TFT. It is a characteristic view showing the relationship between the dose amount of the LDD portion and the on-current and off-current. It is a characteristic view showing the relationship between the dose amount of the LDD portion and the on / off ratio. It is a characteristic view showing the relationship between the dose amount of the LDD portion and the sheet resistance. It is a characteristic view showing the relationship between the dose amount of the source / drain portion and the diffusion length. It is a characteristic view showing the relationship between the dose amount of the source / drain portion and the contact resistance. It is a characteristic view showing the relationship between the LDD length and the on-current and off-current. It is a characteristic view showing the relationship between LDD length and a source-drain breakdown voltage. 42A to 42D are process diagrams showing the manufacturing method of the eighth embodiment. It is a figure which shows the transistor characteristic of the LDD type TFT of a 9th Example. It is a figure which shows the highest operating frequency of the shift register circuit using the LDD type TFT of the 9th Example. It is a figure which shows the contact resistance of the 9th Example and a comparative example, source-drain resistance, and LDD resistance. It is a figure showing the model used in order to calculate parasitic resistance etc. FIG. 6 is a circuit diagram of an active matrix LCD with a built-in peripheral drive circuit. 48A and 48B are a pixel pattern diagram and a cross-sectional view of an active matrix LCD. 49A and 49B are a circuit diagram and a timing chart of a bidirectional shift register circuit. 50A and 50B are a circuit diagram and a timing chart of a unidirectional shift register circuit. 51A and 51B are a circuit diagram and a timing chart of the level shifter circuit. It is a circuit diagram of an analog line sequential data driver. It is a circuit diagram of a digital data driver. It is a block diagram of a display system using an active matrix LCD. It is a figure which shows an example of the mobility and ON current of an amorphous TFT, the conventional polycrystalline TFT, a present Example, and single crystal MOSFET. FIG. 56A illustrates an example of a structure of a thin film semiconductor device, and FIG. 56B is an equivalent circuit diagram of the thin film semiconductor device.

Explanation of symbols

1 insulating substrate, 2 a semiconductor thin film, 3 n ^- semiconductor thin film, 4 p ^- the semiconductor thin film,
5 Gate insulating film, 6 Gate electrode, 7 Interlayer insulating film, 8 Metal thin film,
9 n ^- semiconductor thin film, 10 p ^- semiconductor thin

Claims (43)

In a thin film semiconductor device including a non-single-crystal semiconductor film formed on the insulating material of the substrate, at least a part of the surface of which is an insulating material,
The semiconductor film is disposed in at least one of a first impurity semiconductor film disposed in a source portion and a drain portion of the thin film transistor, between the drain portion and the channel portion of the thin film transistor, and between the source portion and the channel portion. A high-resistance second impurity semiconductor film,
When the LDD length in the drain part is Llddd, and the distance from the end of the contact hole on the channel part side of the drain part to the gate electrode is Lcontd,
0.8 × Llddd ≦ Lcontd ≦ 1.2 × Llddd
A thin film semiconductor device characterized in that: In a thin film semiconductor device including a non-single-crystal semiconductor film formed on the insulating material of the substrate, at least a part of the surface of which is an insulating material,
The semiconductor film is disposed in at least one of a first impurity semiconductor film disposed in a source portion and a drain portion of the thin film transistor, between the drain portion and the channel portion of the thin film transistor, and between the source portion and the channel portion. A high-resistance second impurity semiconductor film,
When the LDD length in the source part is Lldds, and the distance from the end of the contact hole in the source part on the channel part side to the gate electrode is Lconts,
0.8 × Lldds ≦ Lconts ≦ 1.2 × Lldds
A thin film semiconductor device characterized in that: In any one of Claims 1 thru | or 3,
A p-type thin film transistor having the first and second impurity semiconductor films in which the implanted impurity is p-type, and an n-type thin film transistor having the first and second impurity semiconductor films in which the implanted impurity is n-type. A thin film semiconductor device comprising: In claim 3,
A thin film semiconductor device, wherein a gate electrode length of the p-type thin film transistor is smaller than a gate electrode length of the n-type thin film transistor. In claim 4,
The gate electrode length of the p-type thin film transistor and the gate electrode length of the n-type thin film transistor are both 5 μm or less. In any of claims 3 to 5,
A thin film semiconductor device, wherein a channel width of the n-type thin film transistor is smaller than a channel width of the p-type thin film transistor. In claim 6,
The gate electrode length of the p-type thin film transistor and the gate electrode length of the n-type thin film transistor are both 5 μm or less. In a method of manufacturing a thin film semiconductor device including a non-single-crystal semiconductor film formed on the insulating material of the substrate, at least a part of the surface of which is an insulating material,
A step of implanting impurities using the gate electrode as a mask, and a step of implanting impurities using the photoresist as a mask,
Ranges dose of ^{1 × 10 13 cm -2 ~1 ×} 10 14 cm ^-2 of impurities to be implanted using the gate electrode as a mask, a dose of impurity implanted using the photoresist as a mask of 5 × A method for producing a thin film semiconductor device, wherein the range is from 10 ¹⁴ cm ⁻² to 1 × 10 ¹⁶ cm ⁻² . In claim 8,
A method of manufacturing a thin film semiconductor device, comprising: forming an impurity semiconductor film in an island shape on a source portion and a drain portion of a thin film transistor; and forming an intrinsic semiconductor film on the impurity semiconductor film formed in the island shape . In a method of manufacturing a thin film semiconductor device including a non-single-crystal semiconductor film formed on the insulating material of the substrate, at least a part of the surface of which is an insulating material,
A step of implanting impurities using the gate electrode as a mask, and a step of implanting impurities after forming an insulating film on the surface layer of the gate electrode,
Impurities implanted using the gate electrode as a mask have an impurity dose in the range of 1 × 10 ¹³ cm ⁻² to 1 × 10 ¹⁴ cm ⁻² and an insulating film is formed on the surface layer of the gate electrode. A method for manufacturing a thin film semiconductor device, wherein the dose amount of the thin film semiconductor is in the range of 5 × 10 ¹⁴ cm ⁻² to 1 × 10 ¹⁶ cm ⁻² . In claim 10,
A method of manufacturing a thin film semiconductor device, comprising: forming an impurity semiconductor film in an island shape on a source portion and a drain portion of a thin film transistor; and forming an intrinsic semiconductor film on the impurity semiconductor film formed in the island shape . In either of claims 10 or 11,
A method of manufacturing a thin film semiconductor device, wherein the insulating film formed on the surface layer of the gate electrode is formed by thermally oxidizing or anodizing the material of the gate electrode, or by a predetermined deposition method. In a display system using a thin film semiconductor device including a non-single-crystal semiconductor film formed on the insulating material of the substrate, at least a part of the surface of which is an insulating material,
An active matrix portion formed on the insulating material, and a data driver portion and a scan driver portion formed on the insulating material and configured by the thin film semiconductor device,
The semiconductor film is disposed in at least one of a first impurity semiconductor film disposed in a source portion and a drain portion of the thin film transistor, between the drain portion and the channel portion of the thin film transistor, and between the source portion and the channel portion. A high-resistance second impurity semiconductor film,
The maximum impurity concentration of the second impurity semiconductor film is in the range of 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ¹⁹ cm ⁻³ . In a display system using a thin film semiconductor device including a non-single-crystal semiconductor film formed on the insulating material of the substrate, at least a part of the surface of which is an insulating material,
An active matrix portion formed on the insulating material, and a data driver portion and a scan driver portion formed on the insulating material and configured by the thin film semiconductor device,
The semiconductor film is disposed in at least one of a first impurity semiconductor film disposed in a source portion and a drain portion of the thin film transistor, between the drain portion and the channel portion of the thin film transistor, and between the source portion and the channel portion. A high-resistance second impurity semiconductor film,
Display system, characterized in that the maximum impurity concentration of the first impurity semiconductor film is in the range of ^{5 × 10 19 cm -3 ~1 ×} 10 21 cm -3. In a display system using a thin film semiconductor device including a non-single-crystal semiconductor film formed on the insulating material of the substrate, at least a part of the surface of which is an insulating material,
An active matrix portion formed on the insulating material, and a data driver portion and a scan driver portion formed on the insulating material and configured by the thin film semiconductor device,
The semiconductor film is disposed in at least one of a first impurity semiconductor film disposed in a source portion and a drain portion of the thin film transistor, between the drain portion and the channel portion of the thin film transistor, and between the source portion and the channel portion. A high-resistance second impurity semiconductor film,
The data driver unit and the scan driver unit are composed of an n-type thin film transistor having an LDD structure and a p-type thin film transistor having an LDD structure. A display system having a range of 6 μm to 4 μm. In a display system using a thin film semiconductor device including a non-single-crystal semiconductor film formed on the insulating material of the substrate, at least a part of the surface of which is an insulating material,
An active matrix portion formed on the insulating material, and a data driver portion and a scan driver portion formed on the insulating material and configured by the thin film semiconductor device,
The semiconductor film is disposed in at least one of a first impurity semiconductor film disposed in a source portion and a drain portion of the thin film transistor, between the drain portion and the channel portion of the thin film transistor, and between the source portion and the channel portion. A high-resistance second impurity semiconductor film,
A display system, wherein a length of a gate electrode formed on the semiconductor film via a gate insulating film is 5 μm or less. In any of claims 13 to 16,
The display system, wherein the data driver unit or the scan driver unit includes a bidirectional shift register circuit using a clocked gate. In any of claims 13 to 16,
The display system, wherein the data driver unit or the scan driver unit includes a plurality of shift register circuits having different phases of clock signals, and includes a gate for inputting outputs of the plurality of shift registers. In any of claims 13 to 16,
The display system, wherein the data driver unit or the scan driver unit includes a level shifter circuit and a shift register circuit, and the shift register circuit is driven at a TTL level or less. In claim 19,
The display system, wherein the input portion of the level shifter circuit includes a p-type thin film transistor and an n-type thin film transistor connected in series. In any of claims 13 to 16,
The data driver unit includes a shift register circuit, a video line, and an analog switch, and the output of the shift register circuit is input to the gate terminal of the analog switch via a level shifter circuit or directly, thereby dot-sequentially A display system characterized in that element driving is performed in an analog manner. In any of claims 13 to 16,
The data driver unit includes a first-stage analog latch connected to a video line, a second-stage analog latch to which an output of the first-stage analog latch is input, and an output of the second-stage analog latch And an analog buffer connected to the signal line, thereby driving the elements in a line-sequential analog manner. In any of claims 13 to 16,
The data driver unit includes n sets of first-stage latches connected to n digital signal input lines, n sets of second-stage latches to which outputs of the first-stage latches are input, And a decoder connected to the gate of a ²ⁿ analog switch, to which element driving is performed in a digital manner. In any of claims 13 to 16,
A video signal amplifying circuit for amplifying a video signal output from the video signal generator; and a timing controller for generating a timing signal synchronized with the video signal output from the video signal generator; A display system, wherein a driver unit is driven by the timing signal. In claim 24,
The display system, wherein the timing controller, the data driver unit, and the scan driver unit are driven below a TTL level. In claim 24 or 25,
The display system, wherein the timing controller is constituted by the thin film semiconductor device. 27.
The display system, wherein the video signal amplification circuit includes a signal frequency conversion circuit or a γ correction circuit for converting the video signal into a plurality of low frequency signals. Any of claims 24 to 27
The display system, wherein the video signal amplifier circuit is constituted by the thin film semiconductor device. In a thin film semiconductor device including a non-single-crystal semiconductor film formed on the insulating material of the substrate, at least a part of the surface of which is an insulating material,
The semiconductor film is deposited by a chemical vapor deposition method under a condition that slows the generation rate of nuclei as seeds for film formation and increases the growth rate of islands generated from the nuclei. A high resistance film is disposed in at least one of the first impurity semiconductor film disposed in the source portion and the drain portion of the thin film transistor, and between the drain portion and the channel portion of the thin film transistor and between the source portion and the channel portion. A thin film semiconductor device comprising: a second impurity semiconductor film. In a thin film semiconductor device including a non-single-crystal semiconductor film formed on the insulating material of the substrate, at least a part of the surface of which is an insulating material,
When the semiconductor film is in a polycrystalline state, the average grain area is 10000 nm ² or more, and the semiconductor film includes a first impurity semiconductor film disposed in a source portion and a drain portion of the thin film transistor, and a drain of the thin film transistor A thin film semiconductor device comprising: a high-resistance second impurity semiconductor film disposed between at least one of the first portion and the channel portion and between the source portion and the channel portion. In a thin film semiconductor device including a non-single-crystal semiconductor film formed on the insulating material of the substrate, at least a part of the surface of which is an insulating material,
A first impurity semiconductor film in which an average area of islands generated from nuclei as seeds of the semiconductor film generation is 10000 nm ² or more, and the semiconductor film is disposed in a source part and a drain part of the thin film transistor, and a thin film transistor A high-resistance second impurity semiconductor film disposed between at least one of the drain portion and the channel portion and between the source portion and the channel portion. Any one of claims 29 to 31
Thin film semiconductor device characterized by maximum impurity concentration of the second impurity semiconductor film is in the range of ^{2 × 10 17 cm -3 ~1 ×} 10 19 cm -3. A device according to any of claims 29 to 32.
The thin film semiconductor device, wherein the first impurity semiconductor film has a maximum impurity concentration in a range of 5 × 10 ¹⁹ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ . 34. Any one of claims 29 to 33.
A thin film semiconductor device, wherein an LDD length in a drain portion or a source portion is in a range of 0.3 μm to 4 μm. Any one of claims 29 to 34
A thin film semiconductor device, wherein a length of a gate electrode formed on the semiconductor film through a gate insulating film is 5 μm or less. In any of claims 29 to 35
When the LDD length in the drain part is Llddd, and the distance from the end of the contact hole on the channel part side of the drain part to the gate electrode is Lcontd,
0.8 × Llddd ≦ Lcontd ≦ 1.2 × Llddd
A thin film semiconductor device characterized in that: A device according to any of claims 29 to 36.
When the LDD length in the source part is Lldds, and the distance from the end of the contact hole in the source part on the channel part side to the gate electrode is Lconts,
0.8 × Lldds ≦ Lconts ≦ 1.2 × Lldds
A thin film semiconductor device characterized in that: A device according to any of claims 29 to 37.
A thin film semiconductor device, wherein the second impurity semiconductor film is arranged in the entire region of the source portion and drain portion of a p-type thin film transistor in which an impurity injected into the impurity semiconductor film is p-type. In a method of manufacturing a thin film semiconductor device including a non-single-crystal semiconductor film formed on the insulating material of the substrate, at least a part of the surface of which is an insulating material,
Depositing a semiconductor film by a chemical vapor deposition method under the condition of slowing the generation rate of nuclei as seeds for film formation and increasing the growth rate of islands generated from the nuclei;
A step of implanting impurities using the gate electrode as a mask, and a step of implanting impurities using the photoresist as a mask,
A method of manufacturing a thin film semiconductor device, wherein a dose amount of an impurity implanted using the gate electrode as a mask is lower than a dose amount of an impurity implanted using the photoresist as a mask. In a method of manufacturing a thin film semiconductor device including a non-single-crystal semiconductor film formed on the insulating material of the substrate, at least a part of the surface of which is an insulating material,
Depositing a semiconductor film by a chemical vapor deposition method under the condition of slowing the generation rate of nuclei as seeds for film formation and increasing the growth rate of islands generated from the nuclei;
A step of implanting impurities using the gate electrode as a mask, and a step of implanting impurities after forming an insulating film on the surface layer of the gate electrode,
A method of manufacturing a thin film semiconductor device, wherein a dose amount of an impurity implanted using the gate electrode as a mask is lower than a dose amount of an impurity implanted after forming an insulating film in the gate electrode surface layer portion. In any of claims 39 or 40,
A thin film semiconductor characterized in that a generation rate of the nuclei is controlled by a deposition temperature, a growth rate of the island is controlled by a deposition rate, the deposition temperature is 580 ° C. or less, and the deposition rate is 6 Å / min or more. Device manufacturing method. In any of claims 39 to 41,
A method of manufacturing a thin film semiconductor device, comprising a step of performing a heat treatment on the semiconductor film at a temperature in a range of 500 ° C. to 700 ° C. after the step of depositing the semiconductor film. In any of claims 39 to 42,
The dose of impurities implanted using the gate electrode as a mask is in the range of 2 × 10 ¹² cm ⁻² to 1 × 10 ¹⁴ cm ⁻² , and the dose of impurities implanted using the photoresist as a mask or the gate A method of manufacturing a thin film semiconductor device, wherein a dose amount of impurities implanted after forming an insulating film in an electrode surface layer portion is in a range of 5 × 10 ¹⁴ cm ⁻² to 1 × 10 ¹⁶ cm ⁻² .